setup-res.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Support routines for initializing a PCI subsystem
  4. *
  5. * Extruded from code written by
  6. * Dave Rusling ([email protected])
  7. * David Mosberger ([email protected])
  8. * David Miller ([email protected])
  9. *
  10. * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <[email protected]>
  11. *
  12. * Nov 2000, Ivan Kokshaysky <[email protected]>
  13. * Resource sorting
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/export.h>
  17. #include <linux/pci.h>
  18. #include <linux/errno.h>
  19. #include <linux/ioport.h>
  20. #include <linux/cache.h>
  21. #include <linux/slab.h>
  22. #include "pci.h"
  23. static void pci_std_update_resource(struct pci_dev *dev, int resno)
  24. {
  25. struct pci_bus_region region;
  26. bool disable;
  27. u16 cmd;
  28. u32 new, check, mask;
  29. int reg;
  30. struct resource *res = dev->resource + resno;
  31. /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
  32. if (dev->is_virtfn)
  33. return;
  34. /*
  35. * Ignore resources for unimplemented BARs and unused resource slots
  36. * for 64 bit BARs.
  37. */
  38. if (!res->flags)
  39. return;
  40. if (res->flags & IORESOURCE_UNSET)
  41. return;
  42. /*
  43. * Ignore non-moveable resources. This might be legacy resources for
  44. * which no functional BAR register exists or another important
  45. * system resource we shouldn't move around.
  46. */
  47. if (res->flags & IORESOURCE_PCI_FIXED)
  48. return;
  49. pcibios_resource_to_bus(dev->bus, &region, res);
  50. new = region.start;
  51. if (res->flags & IORESOURCE_IO) {
  52. mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  53. new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
  54. } else if (resno == PCI_ROM_RESOURCE) {
  55. mask = PCI_ROM_ADDRESS_MASK;
  56. } else {
  57. mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  58. new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
  59. }
  60. if (resno < PCI_ROM_RESOURCE) {
  61. reg = PCI_BASE_ADDRESS_0 + 4 * resno;
  62. } else if (resno == PCI_ROM_RESOURCE) {
  63. /*
  64. * Apparently some Matrox devices have ROM BARs that read
  65. * as zero when disabled, so don't update ROM BARs unless
  66. * they're enabled. See
  67. * https://lore.kernel.org/r/[email protected]/
  68. * But we must update ROM BAR for buggy devices where even a
  69. * disabled ROM can conflict with other BARs.
  70. */
  71. if (!(res->flags & IORESOURCE_ROM_ENABLE) &&
  72. !dev->rom_bar_overlap)
  73. return;
  74. reg = dev->rom_base_reg;
  75. if (res->flags & IORESOURCE_ROM_ENABLE)
  76. new |= PCI_ROM_ADDRESS_ENABLE;
  77. } else
  78. return;
  79. /*
  80. * We can't update a 64-bit BAR atomically, so when possible,
  81. * disable decoding so that a half-updated BAR won't conflict
  82. * with another device.
  83. */
  84. disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
  85. if (disable) {
  86. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  87. pci_write_config_word(dev, PCI_COMMAND,
  88. cmd & ~PCI_COMMAND_MEMORY);
  89. }
  90. pci_write_config_dword(dev, reg, new);
  91. pci_read_config_dword(dev, reg, &check);
  92. if ((new ^ check) & mask) {
  93. pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
  94. resno, new, check);
  95. }
  96. if (res->flags & IORESOURCE_MEM_64) {
  97. new = region.start >> 16 >> 16;
  98. pci_write_config_dword(dev, reg + 4, new);
  99. pci_read_config_dword(dev, reg + 4, &check);
  100. if (check != new) {
  101. pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
  102. resno, new, check);
  103. }
  104. }
  105. if (disable)
  106. pci_write_config_word(dev, PCI_COMMAND, cmd);
  107. }
  108. void pci_update_resource(struct pci_dev *dev, int resno)
  109. {
  110. if (resno <= PCI_ROM_RESOURCE)
  111. pci_std_update_resource(dev, resno);
  112. #ifdef CONFIG_PCI_IOV
  113. else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
  114. pci_iov_update_resource(dev, resno);
  115. #endif
  116. }
  117. int pci_claim_resource(struct pci_dev *dev, int resource)
  118. {
  119. struct resource *res = &dev->resource[resource];
  120. struct resource *root, *conflict;
  121. if (res->flags & IORESOURCE_UNSET) {
  122. pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
  123. resource, res);
  124. return -EINVAL;
  125. }
  126. /*
  127. * If we have a shadow copy in RAM, the PCI device doesn't respond
  128. * to the shadow range, so we don't need to claim it, and upstream
  129. * bridges don't need to route the range to the device.
  130. */
  131. if (res->flags & IORESOURCE_ROM_SHADOW)
  132. return 0;
  133. root = pci_find_parent_resource(dev, res);
  134. if (!root) {
  135. pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
  136. resource, res);
  137. res->flags |= IORESOURCE_UNSET;
  138. return -EINVAL;
  139. }
  140. conflict = request_resource_conflict(root, res);
  141. if (conflict) {
  142. pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
  143. resource, res, conflict->name, conflict);
  144. res->flags |= IORESOURCE_UNSET;
  145. return -EBUSY;
  146. }
  147. return 0;
  148. }
  149. EXPORT_SYMBOL(pci_claim_resource);
  150. void pci_disable_bridge_window(struct pci_dev *dev)
  151. {
  152. /* MMIO Base/Limit */
  153. pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
  154. /* Prefetchable MMIO Base/Limit */
  155. pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
  156. pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
  157. pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
  158. }
  159. /*
  160. * Generic function that returns a value indicating that the device's
  161. * original BIOS BAR address was not saved and so is not available for
  162. * reinstatement.
  163. *
  164. * Can be over-ridden by architecture specific code that implements
  165. * reinstatement functionality rather than leaving it disabled when
  166. * normal allocation attempts fail.
  167. */
  168. resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
  169. {
  170. return 0;
  171. }
  172. static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
  173. int resno, resource_size_t size)
  174. {
  175. struct resource *root, *conflict;
  176. resource_size_t fw_addr, start, end;
  177. fw_addr = pcibios_retrieve_fw_addr(dev, resno);
  178. if (!fw_addr)
  179. return -ENOMEM;
  180. start = res->start;
  181. end = res->end;
  182. res->start = fw_addr;
  183. res->end = res->start + size - 1;
  184. res->flags &= ~IORESOURCE_UNSET;
  185. root = pci_find_parent_resource(dev, res);
  186. if (!root) {
  187. /*
  188. * If dev is behind a bridge, accesses will only reach it
  189. * if res is inside the relevant bridge window.
  190. */
  191. if (pci_upstream_bridge(dev))
  192. return -ENXIO;
  193. /*
  194. * On the root bus, assume the host bridge will forward
  195. * everything.
  196. */
  197. if (res->flags & IORESOURCE_IO)
  198. root = &ioport_resource;
  199. else
  200. root = &iomem_resource;
  201. }
  202. pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
  203. resno, res);
  204. conflict = request_resource_conflict(root, res);
  205. if (conflict) {
  206. pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
  207. resno, res, conflict->name, conflict);
  208. res->start = start;
  209. res->end = end;
  210. res->flags |= IORESOURCE_UNSET;
  211. return -EBUSY;
  212. }
  213. return 0;
  214. }
  215. /*
  216. * We don't have to worry about legacy ISA devices, so nothing to do here.
  217. * This is marked as __weak because multiple architectures define it; it should
  218. * eventually go away.
  219. */
  220. resource_size_t __weak pcibios_align_resource(void *data,
  221. const struct resource *res,
  222. resource_size_t size,
  223. resource_size_t align)
  224. {
  225. return res->start;
  226. }
  227. static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
  228. int resno, resource_size_t size, resource_size_t align)
  229. {
  230. struct resource *res = dev->resource + resno;
  231. resource_size_t min;
  232. int ret;
  233. min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
  234. /*
  235. * First, try exact prefetching match. Even if a 64-bit
  236. * prefetchable bridge window is below 4GB, we can't put a 32-bit
  237. * prefetchable resource in it because pbus_size_mem() assumes a
  238. * 64-bit window will contain no 32-bit resources. If we assign
  239. * things differently than they were sized, not everything will fit.
  240. */
  241. ret = pci_bus_alloc_resource(bus, res, size, align, min,
  242. IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
  243. pcibios_align_resource, dev);
  244. if (ret == 0)
  245. return 0;
  246. /*
  247. * If the prefetchable window is only 32 bits wide, we can put
  248. * 64-bit prefetchable resources in it.
  249. */
  250. if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
  251. (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
  252. ret = pci_bus_alloc_resource(bus, res, size, align, min,
  253. IORESOURCE_PREFETCH,
  254. pcibios_align_resource, dev);
  255. if (ret == 0)
  256. return 0;
  257. }
  258. /*
  259. * If we didn't find a better match, we can put any memory resource
  260. * in a non-prefetchable window. If this resource is 32 bits and
  261. * non-prefetchable, the first call already tried the only possibility
  262. * so we don't need to try again.
  263. */
  264. if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
  265. ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
  266. pcibios_align_resource, dev);
  267. return ret;
  268. }
  269. static int _pci_assign_resource(struct pci_dev *dev, int resno,
  270. resource_size_t size, resource_size_t min_align)
  271. {
  272. struct pci_bus *bus;
  273. int ret;
  274. bus = dev->bus;
  275. while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
  276. if (!bus->parent || !bus->self->transparent)
  277. break;
  278. bus = bus->parent;
  279. }
  280. return ret;
  281. }
  282. int pci_assign_resource(struct pci_dev *dev, int resno)
  283. {
  284. struct resource *res = dev->resource + resno;
  285. resource_size_t align, size;
  286. int ret;
  287. if (res->flags & IORESOURCE_PCI_FIXED)
  288. return 0;
  289. res->flags |= IORESOURCE_UNSET;
  290. align = pci_resource_alignment(dev, res);
  291. if (!align) {
  292. pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
  293. resno, res);
  294. return -EINVAL;
  295. }
  296. size = resource_size(res);
  297. ret = _pci_assign_resource(dev, resno, size, align);
  298. /*
  299. * If we failed to assign anything, let's try the address
  300. * where firmware left it. That at least has a chance of
  301. * working, which is better than just leaving it disabled.
  302. */
  303. if (ret < 0) {
  304. pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
  305. ret = pci_revert_fw_address(res, dev, resno, size);
  306. }
  307. if (ret < 0) {
  308. pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
  309. return ret;
  310. }
  311. res->flags &= ~IORESOURCE_UNSET;
  312. res->flags &= ~IORESOURCE_STARTALIGN;
  313. pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
  314. if (resno < PCI_BRIDGE_RESOURCES)
  315. pci_update_resource(dev, resno);
  316. return 0;
  317. }
  318. EXPORT_SYMBOL(pci_assign_resource);
  319. int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
  320. resource_size_t min_align)
  321. {
  322. struct resource *res = dev->resource + resno;
  323. unsigned long flags;
  324. resource_size_t new_size;
  325. int ret;
  326. if (res->flags & IORESOURCE_PCI_FIXED)
  327. return 0;
  328. flags = res->flags;
  329. res->flags |= IORESOURCE_UNSET;
  330. if (!res->parent) {
  331. pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
  332. resno, res);
  333. return -EINVAL;
  334. }
  335. /* already aligned with min_align */
  336. new_size = resource_size(res) + addsize;
  337. ret = _pci_assign_resource(dev, resno, new_size, min_align);
  338. if (ret) {
  339. res->flags = flags;
  340. pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
  341. resno, res, (unsigned long long) addsize);
  342. return ret;
  343. }
  344. res->flags &= ~IORESOURCE_UNSET;
  345. res->flags &= ~IORESOURCE_STARTALIGN;
  346. pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
  347. resno, res, (unsigned long long) addsize);
  348. if (resno < PCI_BRIDGE_RESOURCES)
  349. pci_update_resource(dev, resno);
  350. return 0;
  351. }
  352. void pci_release_resource(struct pci_dev *dev, int resno)
  353. {
  354. struct resource *res = dev->resource + resno;
  355. pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
  356. if (!res->parent)
  357. return;
  358. release_resource(res);
  359. res->end = resource_size(res) - 1;
  360. res->start = 0;
  361. res->flags |= IORESOURCE_UNSET;
  362. }
  363. EXPORT_SYMBOL(pci_release_resource);
  364. int pci_resize_resource(struct pci_dev *dev, int resno, int size)
  365. {
  366. struct resource *res = dev->resource + resno;
  367. struct pci_host_bridge *host;
  368. int old, ret;
  369. u32 sizes;
  370. u16 cmd;
  371. /* Check if we must preserve the firmware's resource assignment */
  372. host = pci_find_host_bridge(dev->bus);
  373. if (host->preserve_config)
  374. return -ENOTSUPP;
  375. /* Make sure the resource isn't assigned before resizing it. */
  376. if (!(res->flags & IORESOURCE_UNSET))
  377. return -EBUSY;
  378. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  379. if (cmd & PCI_COMMAND_MEMORY)
  380. return -EBUSY;
  381. sizes = pci_rebar_get_possible_sizes(dev, resno);
  382. if (!sizes)
  383. return -ENOTSUPP;
  384. if (!(sizes & BIT(size)))
  385. return -EINVAL;
  386. old = pci_rebar_get_current_size(dev, resno);
  387. if (old < 0)
  388. return old;
  389. ret = pci_rebar_set_size(dev, resno, size);
  390. if (ret)
  391. return ret;
  392. res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
  393. /* Check if the new config works by trying to assign everything. */
  394. if (dev->bus->self) {
  395. ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
  396. if (ret)
  397. goto error_resize;
  398. }
  399. return 0;
  400. error_resize:
  401. pci_rebar_set_size(dev, resno, old);
  402. res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
  403. return ret;
  404. }
  405. EXPORT_SYMBOL(pci_resize_resource);
  406. int pci_enable_resources(struct pci_dev *dev, int mask)
  407. {
  408. u16 cmd, old_cmd;
  409. int i;
  410. struct resource *r;
  411. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  412. old_cmd = cmd;
  413. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  414. if (!(mask & (1 << i)))
  415. continue;
  416. r = &dev->resource[i];
  417. if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  418. continue;
  419. if ((i == PCI_ROM_RESOURCE) &&
  420. (!(r->flags & IORESOURCE_ROM_ENABLE)))
  421. continue;
  422. if (r->flags & IORESOURCE_UNSET) {
  423. pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
  424. i, r);
  425. return -EINVAL;
  426. }
  427. if (!r->parent) {
  428. pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
  429. i, r);
  430. return -EINVAL;
  431. }
  432. if (r->flags & IORESOURCE_IO)
  433. cmd |= PCI_COMMAND_IO;
  434. if (r->flags & IORESOURCE_MEM)
  435. cmd |= PCI_COMMAND_MEMORY;
  436. }
  437. if (cmd != old_cmd) {
  438. pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
  439. pci_write_config_word(dev, PCI_COMMAND, cmd);
  440. }
  441. return 0;
  442. }