aer.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Implement the AER root port service driver. The driver registers an IRQ
  4. * handler. When a root port triggers an AER interrupt, the IRQ handler
  5. * collects root port status and schedules work.
  6. *
  7. * Copyright (C) 2006 Intel Corp.
  8. * Tom Long Nguyen ([email protected])
  9. * Zhang Yanmin ([email protected])
  10. *
  11. * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
  12. * Andrew Patterson <[email protected]>
  13. */
  14. #define pr_fmt(fmt) "AER: " fmt
  15. #define dev_fmt pr_fmt
  16. #include <linux/bitops.h>
  17. #include <linux/cper.h>
  18. #include <linux/pci.h>
  19. #include <linux/pci-acpi.h>
  20. #include <linux/sched.h>
  21. #include <linux/kernel.h>
  22. #include <linux/errno.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/delay.h>
  27. #include <linux/kfifo.h>
  28. #include <linux/slab.h>
  29. #include <acpi/apei.h>
  30. #include <ras/ras_event.h>
  31. #include "../pci.h"
  32. #include "portdrv.h"
  33. #define AER_ERROR_SOURCES_MAX 128
  34. #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
  35. #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/
  36. struct aer_err_source {
  37. unsigned int status;
  38. unsigned int id;
  39. };
  40. struct aer_rpc {
  41. struct pci_dev *rpd; /* Root Port device */
  42. DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX);
  43. };
  44. /* AER stats for the device */
  45. struct aer_stats {
  46. /*
  47. * Fields for all AER capable devices. They indicate the errors
  48. * "as seen by this device". Note that this may mean that if an
  49. * end point is causing problems, the AER counters may increment
  50. * at its link partner (e.g. root port) because the errors will be
  51. * "seen" by the link partner and not the problematic end point
  52. * itself (which may report all counters as 0 as it never saw any
  53. * problems).
  54. */
  55. /* Counters for different type of correctable errors */
  56. u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
  57. /* Counters for different type of fatal uncorrectable errors */
  58. u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
  59. /* Counters for different type of nonfatal uncorrectable errors */
  60. u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
  61. /* Total number of ERR_COR sent by this device */
  62. u64 dev_total_cor_errs;
  63. /* Total number of ERR_FATAL sent by this device */
  64. u64 dev_total_fatal_errs;
  65. /* Total number of ERR_NONFATAL sent by this device */
  66. u64 dev_total_nonfatal_errs;
  67. /*
  68. * Fields for Root ports & root complex event collectors only, these
  69. * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
  70. * messages received by the root port / event collector, INCLUDING the
  71. * ones that are generated internally (by the rootport itself)
  72. */
  73. u64 rootport_total_cor_errs;
  74. u64 rootport_total_fatal_errs;
  75. u64 rootport_total_nonfatal_errs;
  76. };
  77. #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
  78. PCI_ERR_UNC_ECRC| \
  79. PCI_ERR_UNC_UNSUP| \
  80. PCI_ERR_UNC_COMP_ABORT| \
  81. PCI_ERR_UNC_UNX_COMP| \
  82. PCI_ERR_UNC_MALF_TLP)
  83. #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
  84. PCI_EXP_RTCTL_SENFEE| \
  85. PCI_EXP_RTCTL_SEFEE)
  86. #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
  87. PCI_ERR_ROOT_CMD_NONFATAL_EN| \
  88. PCI_ERR_ROOT_CMD_FATAL_EN)
  89. #define ERR_COR_ID(d) (d & 0xffff)
  90. #define ERR_UNCOR_ID(d) (d >> 16)
  91. #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \
  92. PCI_ERR_ROOT_COR_RCV | \
  93. PCI_ERR_ROOT_MULTI_COR_RCV | \
  94. PCI_ERR_ROOT_MULTI_UNCOR_RCV)
  95. static int pcie_aer_disable;
  96. static pci_ers_result_t aer_root_reset(struct pci_dev *dev);
  97. void pci_no_aer(void)
  98. {
  99. pcie_aer_disable = 1;
  100. }
  101. bool pci_aer_available(void)
  102. {
  103. return !pcie_aer_disable && pci_msi_enabled();
  104. }
  105. #ifdef CONFIG_PCIE_ECRC
  106. #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
  107. #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
  108. #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
  109. static int ecrc_policy = ECRC_POLICY_DEFAULT;
  110. static const char * const ecrc_policy_str[] = {
  111. [ECRC_POLICY_DEFAULT] = "bios",
  112. [ECRC_POLICY_OFF] = "off",
  113. [ECRC_POLICY_ON] = "on"
  114. };
  115. /**
  116. * enable_ecrc_checking - enable PCIe ECRC checking for a device
  117. * @dev: the PCI device
  118. *
  119. * Returns 0 on success, or negative on failure.
  120. */
  121. static int enable_ecrc_checking(struct pci_dev *dev)
  122. {
  123. int aer = dev->aer_cap;
  124. u32 reg32;
  125. if (!aer)
  126. return -ENODEV;
  127. pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);
  128. if (reg32 & PCI_ERR_CAP_ECRC_GENC)
  129. reg32 |= PCI_ERR_CAP_ECRC_GENE;
  130. if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
  131. reg32 |= PCI_ERR_CAP_ECRC_CHKE;
  132. pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
  133. return 0;
  134. }
  135. /**
  136. * disable_ecrc_checking - disables PCIe ECRC checking for a device
  137. * @dev: the PCI device
  138. *
  139. * Returns 0 on success, or negative on failure.
  140. */
  141. static int disable_ecrc_checking(struct pci_dev *dev)
  142. {
  143. int aer = dev->aer_cap;
  144. u32 reg32;
  145. if (!aer)
  146. return -ENODEV;
  147. pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);
  148. reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
  149. pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);
  150. return 0;
  151. }
  152. /**
  153. * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
  154. * @dev: the PCI device
  155. */
  156. void pcie_set_ecrc_checking(struct pci_dev *dev)
  157. {
  158. switch (ecrc_policy) {
  159. case ECRC_POLICY_DEFAULT:
  160. return;
  161. case ECRC_POLICY_OFF:
  162. disable_ecrc_checking(dev);
  163. break;
  164. case ECRC_POLICY_ON:
  165. enable_ecrc_checking(dev);
  166. break;
  167. default:
  168. return;
  169. }
  170. }
  171. /**
  172. * pcie_ecrc_get_policy - parse kernel command-line ecrc option
  173. * @str: ECRC policy from kernel command line to use
  174. */
  175. void pcie_ecrc_get_policy(char *str)
  176. {
  177. int i;
  178. i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str);
  179. if (i < 0)
  180. return;
  181. ecrc_policy = i;
  182. }
  183. #endif /* CONFIG_PCIE_ECRC */
  184. #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
  185. PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
  186. int pcie_aer_is_native(struct pci_dev *dev)
  187. {
  188. struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
  189. if (!dev->aer_cap)
  190. return 0;
  191. return pcie_ports_native || host->native_aer;
  192. }
  193. int pci_enable_pcie_error_reporting(struct pci_dev *dev)
  194. {
  195. int rc;
  196. if (!pcie_aer_is_native(dev))
  197. return -EIO;
  198. rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
  199. return pcibios_err_to_errno(rc);
  200. }
  201. EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
  202. int pci_disable_pcie_error_reporting(struct pci_dev *dev)
  203. {
  204. int rc;
  205. if (!pcie_aer_is_native(dev))
  206. return -EIO;
  207. rc = pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
  208. return pcibios_err_to_errno(rc);
  209. }
  210. EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
  211. int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
  212. {
  213. int aer = dev->aer_cap;
  214. u32 status, sev;
  215. if (!pcie_aer_is_native(dev))
  216. return -EIO;
  217. /* Clear status bits for ERR_NONFATAL errors only */
  218. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  219. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
  220. status &= ~sev;
  221. if (status)
  222. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
  223. return 0;
  224. }
  225. EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status);
  226. void pci_aer_clear_fatal_status(struct pci_dev *dev)
  227. {
  228. int aer = dev->aer_cap;
  229. u32 status, sev;
  230. if (!pcie_aer_is_native(dev))
  231. return;
  232. /* Clear status bits for ERR_FATAL errors only */
  233. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  234. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);
  235. status &= sev;
  236. if (status)
  237. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
  238. }
  239. /**
  240. * pci_aer_raw_clear_status - Clear AER error registers.
  241. * @dev: the PCI device
  242. *
  243. * Clearing AER error status registers unconditionally, regardless of
  244. * whether they're owned by firmware or the OS.
  245. *
  246. * Returns 0 on success, or negative on failure.
  247. */
  248. int pci_aer_raw_clear_status(struct pci_dev *dev)
  249. {
  250. int aer = dev->aer_cap;
  251. u32 status;
  252. int port_type;
  253. if (!aer)
  254. return -EIO;
  255. port_type = pci_pcie_type(dev);
  256. if (port_type == PCI_EXP_TYPE_ROOT_PORT ||
  257. port_type == PCI_EXP_TYPE_RC_EC) {
  258. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);
  259. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);
  260. }
  261. pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
  262. pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);
  263. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  264. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);
  265. return 0;
  266. }
  267. int pci_aer_clear_status(struct pci_dev *dev)
  268. {
  269. if (!pcie_aer_is_native(dev))
  270. return -EIO;
  271. return pci_aer_raw_clear_status(dev);
  272. }
  273. void pci_save_aer_state(struct pci_dev *dev)
  274. {
  275. int aer = dev->aer_cap;
  276. struct pci_cap_saved_state *save_state;
  277. u32 *cap;
  278. if (!aer)
  279. return;
  280. save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
  281. if (!save_state)
  282. return;
  283. cap = &save_state->cap.data[0];
  284. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);
  285. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);
  286. pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);
  287. pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);
  288. if (pcie_cap_has_rtctl(dev))
  289. pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);
  290. }
  291. void pci_restore_aer_state(struct pci_dev *dev)
  292. {
  293. int aer = dev->aer_cap;
  294. struct pci_cap_saved_state *save_state;
  295. u32 *cap;
  296. if (!aer)
  297. return;
  298. save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR);
  299. if (!save_state)
  300. return;
  301. cap = &save_state->cap.data[0];
  302. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);
  303. pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);
  304. pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);
  305. pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);
  306. if (pcie_cap_has_rtctl(dev))
  307. pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);
  308. }
  309. void pci_aer_init(struct pci_dev *dev)
  310. {
  311. int n;
  312. dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
  313. if (!dev->aer_cap)
  314. return;
  315. dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
  316. /*
  317. * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER,
  318. * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event
  319. * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec
  320. * 7.8.4).
  321. */
  322. n = pcie_cap_has_rtctl(dev) ? 5 : 4;
  323. pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n);
  324. pci_aer_clear_status(dev);
  325. if (pci_aer_available())
  326. pci_enable_pcie_error_reporting(dev);
  327. pcie_set_ecrc_checking(dev);
  328. }
  329. void pci_aer_exit(struct pci_dev *dev)
  330. {
  331. kfree(dev->aer_stats);
  332. dev->aer_stats = NULL;
  333. }
  334. #define AER_AGENT_RECEIVER 0
  335. #define AER_AGENT_REQUESTER 1
  336. #define AER_AGENT_COMPLETER 2
  337. #define AER_AGENT_TRANSMITTER 3
  338. #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
  339. 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
  340. #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
  341. 0 : PCI_ERR_UNC_COMP_ABORT)
  342. #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
  343. (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
  344. #define AER_GET_AGENT(t, e) \
  345. ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
  346. (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
  347. (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
  348. AER_AGENT_RECEIVER)
  349. #define AER_PHYSICAL_LAYER_ERROR 0
  350. #define AER_DATA_LINK_LAYER_ERROR 1
  351. #define AER_TRANSACTION_LAYER_ERROR 2
  352. #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
  353. PCI_ERR_COR_RCVR : 0)
  354. #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
  355. (PCI_ERR_COR_BAD_TLP| \
  356. PCI_ERR_COR_BAD_DLLP| \
  357. PCI_ERR_COR_REP_ROLL| \
  358. PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
  359. #define AER_GET_LAYER_ERROR(t, e) \
  360. ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
  361. (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
  362. AER_TRANSACTION_LAYER_ERROR)
  363. /*
  364. * AER error strings
  365. */
  366. static const char *aer_error_severity_string[] = {
  367. "Uncorrected (Non-Fatal)",
  368. "Uncorrected (Fatal)",
  369. "Corrected"
  370. };
  371. static const char *aer_error_layer[] = {
  372. "Physical Layer",
  373. "Data Link Layer",
  374. "Transaction Layer"
  375. };
  376. static const char *aer_correctable_error_string[] = {
  377. "RxErr", /* Bit Position 0 */
  378. NULL,
  379. NULL,
  380. NULL,
  381. NULL,
  382. NULL,
  383. "BadTLP", /* Bit Position 6 */
  384. "BadDLLP", /* Bit Position 7 */
  385. "Rollover", /* Bit Position 8 */
  386. NULL,
  387. NULL,
  388. NULL,
  389. "Timeout", /* Bit Position 12 */
  390. "NonFatalErr", /* Bit Position 13 */
  391. "CorrIntErr", /* Bit Position 14 */
  392. "HeaderOF", /* Bit Position 15 */
  393. NULL, /* Bit Position 16 */
  394. NULL, /* Bit Position 17 */
  395. NULL, /* Bit Position 18 */
  396. NULL, /* Bit Position 19 */
  397. NULL, /* Bit Position 20 */
  398. NULL, /* Bit Position 21 */
  399. NULL, /* Bit Position 22 */
  400. NULL, /* Bit Position 23 */
  401. NULL, /* Bit Position 24 */
  402. NULL, /* Bit Position 25 */
  403. NULL, /* Bit Position 26 */
  404. NULL, /* Bit Position 27 */
  405. NULL, /* Bit Position 28 */
  406. NULL, /* Bit Position 29 */
  407. NULL, /* Bit Position 30 */
  408. NULL, /* Bit Position 31 */
  409. };
  410. static const char *aer_uncorrectable_error_string[] = {
  411. "Undefined", /* Bit Position 0 */
  412. NULL,
  413. NULL,
  414. NULL,
  415. "DLP", /* Bit Position 4 */
  416. "SDES", /* Bit Position 5 */
  417. NULL,
  418. NULL,
  419. NULL,
  420. NULL,
  421. NULL,
  422. NULL,
  423. "TLP", /* Bit Position 12 */
  424. "FCP", /* Bit Position 13 */
  425. "CmpltTO", /* Bit Position 14 */
  426. "CmpltAbrt", /* Bit Position 15 */
  427. "UnxCmplt", /* Bit Position 16 */
  428. "RxOF", /* Bit Position 17 */
  429. "MalfTLP", /* Bit Position 18 */
  430. "ECRC", /* Bit Position 19 */
  431. "UnsupReq", /* Bit Position 20 */
  432. "ACSViol", /* Bit Position 21 */
  433. "UncorrIntErr", /* Bit Position 22 */
  434. "BlockedTLP", /* Bit Position 23 */
  435. "AtomicOpBlocked", /* Bit Position 24 */
  436. "TLPBlockedErr", /* Bit Position 25 */
  437. "PoisonTLPBlocked", /* Bit Position 26 */
  438. NULL, /* Bit Position 27 */
  439. NULL, /* Bit Position 28 */
  440. NULL, /* Bit Position 29 */
  441. NULL, /* Bit Position 30 */
  442. NULL, /* Bit Position 31 */
  443. };
  444. static const char *aer_agent_string[] = {
  445. "Receiver ID",
  446. "Requester ID",
  447. "Completer ID",
  448. "Transmitter ID"
  449. };
  450. #define aer_stats_dev_attr(name, stats_array, strings_array, \
  451. total_string, total_field) \
  452. static ssize_t \
  453. name##_show(struct device *dev, struct device_attribute *attr, \
  454. char *buf) \
  455. { \
  456. unsigned int i; \
  457. struct pci_dev *pdev = to_pci_dev(dev); \
  458. u64 *stats = pdev->aer_stats->stats_array; \
  459. size_t len = 0; \
  460. \
  461. for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\
  462. if (strings_array[i]) \
  463. len += sysfs_emit_at(buf, len, "%s %llu\n", \
  464. strings_array[i], \
  465. stats[i]); \
  466. else if (stats[i]) \
  467. len += sysfs_emit_at(buf, len, \
  468. #stats_array "_bit[%d] %llu\n",\
  469. i, stats[i]); \
  470. } \
  471. len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \
  472. pdev->aer_stats->total_field); \
  473. return len; \
  474. } \
  475. static DEVICE_ATTR_RO(name)
  476. aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
  477. aer_correctable_error_string, "ERR_COR",
  478. dev_total_cor_errs);
  479. aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
  480. aer_uncorrectable_error_string, "ERR_FATAL",
  481. dev_total_fatal_errs);
  482. aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
  483. aer_uncorrectable_error_string, "ERR_NONFATAL",
  484. dev_total_nonfatal_errs);
  485. #define aer_stats_rootport_attr(name, field) \
  486. static ssize_t \
  487. name##_show(struct device *dev, struct device_attribute *attr, \
  488. char *buf) \
  489. { \
  490. struct pci_dev *pdev = to_pci_dev(dev); \
  491. return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \
  492. } \
  493. static DEVICE_ATTR_RO(name)
  494. aer_stats_rootport_attr(aer_rootport_total_err_cor,
  495. rootport_total_cor_errs);
  496. aer_stats_rootport_attr(aer_rootport_total_err_fatal,
  497. rootport_total_fatal_errs);
  498. aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
  499. rootport_total_nonfatal_errs);
  500. static struct attribute *aer_stats_attrs[] __ro_after_init = {
  501. &dev_attr_aer_dev_correctable.attr,
  502. &dev_attr_aer_dev_fatal.attr,
  503. &dev_attr_aer_dev_nonfatal.attr,
  504. &dev_attr_aer_rootport_total_err_cor.attr,
  505. &dev_attr_aer_rootport_total_err_fatal.attr,
  506. &dev_attr_aer_rootport_total_err_nonfatal.attr,
  507. NULL
  508. };
  509. static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
  510. struct attribute *a, int n)
  511. {
  512. struct device *dev = kobj_to_dev(kobj);
  513. struct pci_dev *pdev = to_pci_dev(dev);
  514. if (!pdev->aer_stats)
  515. return 0;
  516. if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
  517. a == &dev_attr_aer_rootport_total_err_fatal.attr ||
  518. a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
  519. ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
  520. (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC)))
  521. return 0;
  522. return a->mode;
  523. }
  524. const struct attribute_group aer_stats_attr_group = {
  525. .attrs = aer_stats_attrs,
  526. .is_visible = aer_stats_attrs_are_visible,
  527. };
  528. static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
  529. struct aer_err_info *info)
  530. {
  531. unsigned long status = info->status & ~info->mask;
  532. int i, max = -1;
  533. u64 *counter = NULL;
  534. struct aer_stats *aer_stats = pdev->aer_stats;
  535. if (!aer_stats)
  536. return;
  537. switch (info->severity) {
  538. case AER_CORRECTABLE:
  539. aer_stats->dev_total_cor_errs++;
  540. counter = &aer_stats->dev_cor_errs[0];
  541. max = AER_MAX_TYPEOF_COR_ERRS;
  542. break;
  543. case AER_NONFATAL:
  544. aer_stats->dev_total_nonfatal_errs++;
  545. counter = &aer_stats->dev_nonfatal_errs[0];
  546. max = AER_MAX_TYPEOF_UNCOR_ERRS;
  547. break;
  548. case AER_FATAL:
  549. aer_stats->dev_total_fatal_errs++;
  550. counter = &aer_stats->dev_fatal_errs[0];
  551. max = AER_MAX_TYPEOF_UNCOR_ERRS;
  552. break;
  553. }
  554. for_each_set_bit(i, &status, max)
  555. counter[i]++;
  556. }
  557. static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
  558. struct aer_err_source *e_src)
  559. {
  560. struct aer_stats *aer_stats = pdev->aer_stats;
  561. if (!aer_stats)
  562. return;
  563. if (e_src->status & PCI_ERR_ROOT_COR_RCV)
  564. aer_stats->rootport_total_cor_errs++;
  565. if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
  566. if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
  567. aer_stats->rootport_total_fatal_errs++;
  568. else
  569. aer_stats->rootport_total_nonfatal_errs++;
  570. }
  571. }
  572. static void __print_tlp_header(struct pci_dev *dev,
  573. struct aer_header_log_regs *t)
  574. {
  575. pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
  576. t->dw0, t->dw1, t->dw2, t->dw3);
  577. }
  578. static void __aer_print_error(struct pci_dev *dev,
  579. struct aer_err_info *info)
  580. {
  581. const char **strings;
  582. unsigned long status = info->status & ~info->mask;
  583. const char *level, *errmsg;
  584. int i;
  585. if (info->severity == AER_CORRECTABLE) {
  586. strings = aer_correctable_error_string;
  587. level = KERN_WARNING;
  588. } else {
  589. strings = aer_uncorrectable_error_string;
  590. level = KERN_ERR;
  591. }
  592. for_each_set_bit(i, &status, 32) {
  593. errmsg = strings[i];
  594. if (!errmsg)
  595. errmsg = "Unknown Error Bit";
  596. pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg,
  597. info->first_error == i ? " (First)" : "");
  598. }
  599. pci_dev_aer_stats_incr(dev, info);
  600. }
  601. void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
  602. {
  603. int layer, agent;
  604. int id = ((dev->bus->number << 8) | dev->devfn);
  605. const char *level;
  606. if (!info->status) {
  607. pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
  608. aer_error_severity_string[info->severity]);
  609. goto out;
  610. }
  611. layer = AER_GET_LAYER_ERROR(info->severity, info->status);
  612. agent = AER_GET_AGENT(info->severity, info->status);
  613. level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
  614. pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
  615. aer_error_severity_string[info->severity],
  616. aer_error_layer[layer], aer_agent_string[agent]);
  617. pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
  618. dev->vendor, dev->device, info->status, info->mask);
  619. __aer_print_error(dev, info);
  620. if (info->tlp_header_valid)
  621. __print_tlp_header(dev, &info->tlp);
  622. out:
  623. if (info->id && info->error_dev_num > 1 && info->id == id)
  624. pci_err(dev, " Error of this Agent is reported first\n");
  625. trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
  626. info->severity, info->tlp_header_valid, &info->tlp);
  627. }
  628. static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
  629. {
  630. u8 bus = info->id >> 8;
  631. u8 devfn = info->id & 0xff;
  632. pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n",
  633. info->multi_error_valid ? "Multiple " : "",
  634. aer_error_severity_string[info->severity],
  635. pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn),
  636. PCI_FUNC(devfn));
  637. }
  638. #ifdef CONFIG_ACPI_APEI_PCIEAER
  639. int cper_severity_to_aer(int cper_severity)
  640. {
  641. switch (cper_severity) {
  642. case CPER_SEV_RECOVERABLE:
  643. return AER_NONFATAL;
  644. case CPER_SEV_FATAL:
  645. return AER_FATAL;
  646. default:
  647. return AER_CORRECTABLE;
  648. }
  649. }
  650. EXPORT_SYMBOL_GPL(cper_severity_to_aer);
  651. void cper_print_aer(struct pci_dev *dev, int aer_severity,
  652. struct aer_capability_regs *aer)
  653. {
  654. int layer, agent, tlp_header_valid = 0;
  655. u32 status, mask;
  656. struct aer_err_info info;
  657. if (aer_severity == AER_CORRECTABLE) {
  658. status = aer->cor_status;
  659. mask = aer->cor_mask;
  660. } else {
  661. status = aer->uncor_status;
  662. mask = aer->uncor_mask;
  663. tlp_header_valid = status & AER_LOG_TLP_MASKS;
  664. }
  665. layer = AER_GET_LAYER_ERROR(aer_severity, status);
  666. agent = AER_GET_AGENT(aer_severity, status);
  667. memset(&info, 0, sizeof(info));
  668. info.severity = aer_severity;
  669. info.status = status;
  670. info.mask = mask;
  671. info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
  672. pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
  673. __aer_print_error(dev, &info);
  674. pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
  675. aer_error_layer[layer], aer_agent_string[agent]);
  676. if (aer_severity != AER_CORRECTABLE)
  677. pci_err(dev, "aer_uncor_severity: 0x%08x\n",
  678. aer->uncor_severity);
  679. if (tlp_header_valid)
  680. __print_tlp_header(dev, &aer->header_log);
  681. trace_aer_event(dev_name(&dev->dev), (status & ~mask),
  682. aer_severity, tlp_header_valid, &aer->header_log);
  683. }
  684. #endif
  685. /**
  686. * add_error_device - list device to be handled
  687. * @e_info: pointer to error info
  688. * @dev: pointer to pci_dev to be added
  689. */
  690. static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
  691. {
  692. if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
  693. e_info->dev[e_info->error_dev_num] = pci_dev_get(dev);
  694. e_info->error_dev_num++;
  695. return 0;
  696. }
  697. return -ENOSPC;
  698. }
  699. /**
  700. * is_error_source - check whether the device is source of reported error
  701. * @dev: pointer to pci_dev to be checked
  702. * @e_info: pointer to reported error info
  703. */
  704. static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
  705. {
  706. int aer = dev->aer_cap;
  707. u32 status, mask;
  708. u16 reg16;
  709. /*
  710. * When bus id is equal to 0, it might be a bad id
  711. * reported by root port.
  712. */
  713. if ((PCI_BUS_NUM(e_info->id) != 0) &&
  714. !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
  715. /* Device ID match? */
  716. if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
  717. return true;
  718. /* Continue id comparing if there is no multiple error */
  719. if (!e_info->multi_error_valid)
  720. return false;
  721. }
  722. /*
  723. * When either
  724. * 1) bus id is equal to 0. Some ports might lose the bus
  725. * id of error source id;
  726. * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
  727. * 3) There are multiple errors and prior ID comparing fails;
  728. * We check AER status registers to find possible reporter.
  729. */
  730. if (atomic_read(&dev->enable_cnt) == 0)
  731. return false;
  732. /* Check if AER is enabled */
  733. pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &reg16);
  734. if (!(reg16 & PCI_EXP_AER_FLAGS))
  735. return false;
  736. if (!aer)
  737. return false;
  738. /* Check if error is recorded */
  739. if (e_info->severity == AER_CORRECTABLE) {
  740. pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);
  741. pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
  742. } else {
  743. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);
  744. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
  745. }
  746. if (status & ~mask)
  747. return true;
  748. return false;
  749. }
  750. static int find_device_iter(struct pci_dev *dev, void *data)
  751. {
  752. struct aer_err_info *e_info = (struct aer_err_info *)data;
  753. if (is_error_source(dev, e_info)) {
  754. /* List this device */
  755. if (add_error_device(e_info, dev)) {
  756. /* We cannot handle more... Stop iteration */
  757. /* TODO: Should print error message here? */
  758. return 1;
  759. }
  760. /* If there is only a single error, stop iteration */
  761. if (!e_info->multi_error_valid)
  762. return 1;
  763. }
  764. return 0;
  765. }
  766. /**
  767. * find_source_device - search through device hierarchy for source device
  768. * @parent: pointer to Root Port pci_dev data structure
  769. * @e_info: including detailed error information such like id
  770. *
  771. * Return true if found.
  772. *
  773. * Invoked by DPC when error is detected at the Root Port.
  774. * Caller of this function must set id, severity, and multi_error_valid of
  775. * struct aer_err_info pointed by @e_info properly. This function must fill
  776. * e_info->error_dev_num and e_info->dev[], based on the given information.
  777. */
  778. static bool find_source_device(struct pci_dev *parent,
  779. struct aer_err_info *e_info)
  780. {
  781. struct pci_dev *dev = parent;
  782. int result;
  783. /* Must reset in this function */
  784. e_info->error_dev_num = 0;
  785. /* Is Root Port an agent that sends error message? */
  786. result = find_device_iter(dev, e_info);
  787. if (result)
  788. return true;
  789. if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC)
  790. pcie_walk_rcec(parent, find_device_iter, e_info);
  791. else
  792. pci_walk_bus(parent->subordinate, find_device_iter, e_info);
  793. if (!e_info->error_dev_num) {
  794. pci_info(parent, "can't find device of ID%04x\n", e_info->id);
  795. return false;
  796. }
  797. return true;
  798. }
  799. /**
  800. * handle_error_source - handle logging error into an event log
  801. * @dev: pointer to pci_dev data structure of error source device
  802. * @info: comprehensive error information
  803. *
  804. * Invoked when an error being detected by Root Port.
  805. */
  806. static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
  807. {
  808. int aer = dev->aer_cap;
  809. if (info->severity == AER_CORRECTABLE) {
  810. /*
  811. * Correctable error does not need software intervention.
  812. * No need to go through error recovery process.
  813. */
  814. if (aer)
  815. pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,
  816. info->status);
  817. if (pcie_aer_is_native(dev))
  818. pcie_clear_device_status(dev);
  819. } else if (info->severity == AER_NONFATAL)
  820. pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
  821. else if (info->severity == AER_FATAL)
  822. pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
  823. pci_dev_put(dev);
  824. }
  825. #ifdef CONFIG_ACPI_APEI_PCIEAER
  826. #define AER_RECOVER_RING_ORDER 4
  827. #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
  828. struct aer_recover_entry {
  829. u8 bus;
  830. u8 devfn;
  831. u16 domain;
  832. int severity;
  833. struct aer_capability_regs *regs;
  834. };
  835. static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
  836. AER_RECOVER_RING_SIZE);
  837. static void aer_recover_work_func(struct work_struct *work)
  838. {
  839. struct aer_recover_entry entry;
  840. struct pci_dev *pdev;
  841. while (kfifo_get(&aer_recover_ring, &entry)) {
  842. pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
  843. entry.devfn);
  844. if (!pdev) {
  845. pr_err("no pci_dev for %04x:%02x:%02x.%x\n",
  846. entry.domain, entry.bus,
  847. PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
  848. continue;
  849. }
  850. cper_print_aer(pdev, entry.severity, entry.regs);
  851. if (entry.severity == AER_NONFATAL)
  852. pcie_do_recovery(pdev, pci_channel_io_normal,
  853. aer_root_reset);
  854. else if (entry.severity == AER_FATAL)
  855. pcie_do_recovery(pdev, pci_channel_io_frozen,
  856. aer_root_reset);
  857. pci_dev_put(pdev);
  858. }
  859. }
  860. /*
  861. * Mutual exclusion for writers of aer_recover_ring, reader side don't
  862. * need lock, because there is only one reader and lock is not needed
  863. * between reader and writer.
  864. */
  865. static DEFINE_SPINLOCK(aer_recover_ring_lock);
  866. static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
  867. void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
  868. int severity, struct aer_capability_regs *aer_regs)
  869. {
  870. struct aer_recover_entry entry = {
  871. .bus = bus,
  872. .devfn = devfn,
  873. .domain = domain,
  874. .severity = severity,
  875. .regs = aer_regs,
  876. };
  877. if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1,
  878. &aer_recover_ring_lock))
  879. schedule_work(&aer_recover_work);
  880. else
  881. pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n",
  882. domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
  883. }
  884. EXPORT_SYMBOL_GPL(aer_recover_queue);
  885. #endif
  886. /**
  887. * aer_get_device_error_info - read error status from dev and store it to info
  888. * @dev: pointer to the device expected to have a error record
  889. * @info: pointer to structure to store the error record
  890. *
  891. * Return 1 on success, 0 on error.
  892. *
  893. * Note that @info is reused among all error devices. Clear fields properly.
  894. */
  895. int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
  896. {
  897. int type = pci_pcie_type(dev);
  898. int aer = dev->aer_cap;
  899. int temp;
  900. /* Must reset in this function */
  901. info->status = 0;
  902. info->tlp_header_valid = 0;
  903. /* The device might not support AER */
  904. if (!aer)
  905. return 0;
  906. if (info->severity == AER_CORRECTABLE) {
  907. pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,
  908. &info->status);
  909. pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,
  910. &info->mask);
  911. if (!(info->status & ~info->mask))
  912. return 0;
  913. } else if (type == PCI_EXP_TYPE_ROOT_PORT ||
  914. type == PCI_EXP_TYPE_RC_EC ||
  915. type == PCI_EXP_TYPE_DOWNSTREAM ||
  916. info->severity == AER_NONFATAL) {
  917. /* Link is still healthy for IO reads */
  918. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,
  919. &info->status);
  920. pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
  921. &info->mask);
  922. if (!(info->status & ~info->mask))
  923. return 0;
  924. /* Get First Error Pointer */
  925. pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);
  926. info->first_error = PCI_ERR_CAP_FEP(temp);
  927. if (info->status & AER_LOG_TLP_MASKS) {
  928. info->tlp_header_valid = 1;
  929. pci_read_config_dword(dev,
  930. aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
  931. pci_read_config_dword(dev,
  932. aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
  933. pci_read_config_dword(dev,
  934. aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
  935. pci_read_config_dword(dev,
  936. aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
  937. }
  938. }
  939. return 1;
  940. }
  941. static inline void aer_process_err_devices(struct aer_err_info *e_info)
  942. {
  943. int i;
  944. /* Report all before handle them, not to lost records by reset etc. */
  945. for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
  946. if (aer_get_device_error_info(e_info->dev[i], e_info))
  947. aer_print_error(e_info->dev[i], e_info);
  948. }
  949. for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
  950. if (aer_get_device_error_info(e_info->dev[i], e_info))
  951. handle_error_source(e_info->dev[i], e_info);
  952. }
  953. }
  954. /**
  955. * aer_isr_one_error - consume an error detected by root port
  956. * @rpc: pointer to the root port which holds an error
  957. * @e_src: pointer to an error source
  958. */
  959. static void aer_isr_one_error(struct aer_rpc *rpc,
  960. struct aer_err_source *e_src)
  961. {
  962. struct pci_dev *pdev = rpc->rpd;
  963. struct aer_err_info e_info;
  964. pci_rootport_aer_stats_incr(pdev, e_src);
  965. /*
  966. * There is a possibility that both correctable error and
  967. * uncorrectable error being logged. Report correctable error first.
  968. */
  969. if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
  970. e_info.id = ERR_COR_ID(e_src->id);
  971. e_info.severity = AER_CORRECTABLE;
  972. if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
  973. e_info.multi_error_valid = 1;
  974. else
  975. e_info.multi_error_valid = 0;
  976. aer_print_port_info(pdev, &e_info);
  977. if (find_source_device(pdev, &e_info))
  978. aer_process_err_devices(&e_info);
  979. }
  980. if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
  981. e_info.id = ERR_UNCOR_ID(e_src->id);
  982. if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
  983. e_info.severity = AER_FATAL;
  984. else
  985. e_info.severity = AER_NONFATAL;
  986. if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
  987. e_info.multi_error_valid = 1;
  988. else
  989. e_info.multi_error_valid = 0;
  990. aer_print_port_info(pdev, &e_info);
  991. if (find_source_device(pdev, &e_info))
  992. aer_process_err_devices(&e_info);
  993. }
  994. }
  995. /**
  996. * aer_isr - consume errors detected by root port
  997. * @irq: IRQ assigned to Root Port
  998. * @context: pointer to Root Port data structure
  999. *
  1000. * Invoked, as DPC, when root port records new detected error
  1001. */
  1002. static irqreturn_t aer_isr(int irq, void *context)
  1003. {
  1004. struct pcie_device *dev = (struct pcie_device *)context;
  1005. struct aer_rpc *rpc = get_service_data(dev);
  1006. struct aer_err_source e_src;
  1007. if (kfifo_is_empty(&rpc->aer_fifo))
  1008. return IRQ_NONE;
  1009. while (kfifo_get(&rpc->aer_fifo, &e_src))
  1010. aer_isr_one_error(rpc, &e_src);
  1011. return IRQ_HANDLED;
  1012. }
  1013. /**
  1014. * aer_irq - Root Port's ISR
  1015. * @irq: IRQ assigned to Root Port
  1016. * @context: pointer to Root Port data structure
  1017. *
  1018. * Invoked when Root Port detects AER messages.
  1019. */
  1020. static irqreturn_t aer_irq(int irq, void *context)
  1021. {
  1022. struct pcie_device *pdev = (struct pcie_device *)context;
  1023. struct aer_rpc *rpc = get_service_data(pdev);
  1024. struct pci_dev *rp = rpc->rpd;
  1025. int aer = rp->aer_cap;
  1026. struct aer_err_source e_src = {};
  1027. pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);
  1028. if (!(e_src.status & AER_ERR_STATUS_MASK))
  1029. return IRQ_NONE;
  1030. pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);
  1031. pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);
  1032. if (!kfifo_put(&rpc->aer_fifo, e_src))
  1033. return IRQ_HANDLED;
  1034. return IRQ_WAKE_THREAD;
  1035. }
  1036. static int set_device_error_reporting(struct pci_dev *dev, void *data)
  1037. {
  1038. bool enable = *((bool *)data);
  1039. int type = pci_pcie_type(dev);
  1040. if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
  1041. (type == PCI_EXP_TYPE_RC_EC) ||
  1042. (type == PCI_EXP_TYPE_UPSTREAM) ||
  1043. (type == PCI_EXP_TYPE_DOWNSTREAM)) {
  1044. if (enable)
  1045. pci_enable_pcie_error_reporting(dev);
  1046. else
  1047. pci_disable_pcie_error_reporting(dev);
  1048. }
  1049. return 0;
  1050. }
  1051. /**
  1052. * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
  1053. * @dev: pointer to root port's pci_dev data structure
  1054. * @enable: true = enable error reporting, false = disable error reporting.
  1055. */
  1056. static void set_downstream_devices_error_reporting(struct pci_dev *dev,
  1057. bool enable)
  1058. {
  1059. set_device_error_reporting(dev, &enable);
  1060. if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC)
  1061. pcie_walk_rcec(dev, set_device_error_reporting, &enable);
  1062. else if (dev->subordinate)
  1063. pci_walk_bus(dev->subordinate, set_device_error_reporting,
  1064. &enable);
  1065. }
  1066. /**
  1067. * aer_enable_rootport - enable Root Port's interrupts when receiving messages
  1068. * @rpc: pointer to a Root Port data structure
  1069. *
  1070. * Invoked when PCIe bus loads AER service driver.
  1071. */
  1072. static void aer_enable_rootport(struct aer_rpc *rpc)
  1073. {
  1074. struct pci_dev *pdev = rpc->rpd;
  1075. int aer = pdev->aer_cap;
  1076. u16 reg16;
  1077. u32 reg32;
  1078. /* Clear PCIe Capability's Device Status */
  1079. pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, &reg16);
  1080. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
  1081. /* Disable system error generation in response to error messages */
  1082. pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
  1083. SYSTEM_ERROR_INTR_ON_MESG_MASK);
  1084. /* Clear error status */
  1085. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);
  1086. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
  1087. pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);
  1088. pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);
  1089. pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);
  1090. pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);
  1091. /*
  1092. * Enable error reporting for the root port device and downstream port
  1093. * devices.
  1094. */
  1095. set_downstream_devices_error_reporting(pdev, true);
  1096. /* Enable Root Port's interrupt in response to error messages */
  1097. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1098. reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
  1099. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1100. }
  1101. /**
  1102. * aer_disable_rootport - disable Root Port's interrupts when receiving messages
  1103. * @rpc: pointer to a Root Port data structure
  1104. *
  1105. * Invoked when PCIe bus unloads AER service driver.
  1106. */
  1107. static void aer_disable_rootport(struct aer_rpc *rpc)
  1108. {
  1109. struct pci_dev *pdev = rpc->rpd;
  1110. int aer = pdev->aer_cap;
  1111. u32 reg32;
  1112. /*
  1113. * Disable error reporting for the root port device and downstream port
  1114. * devices.
  1115. */
  1116. set_downstream_devices_error_reporting(pdev, false);
  1117. /* Disable Root's interrupt in response to error messages */
  1118. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1119. reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
  1120. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1121. /* Clear Root's error status reg */
  1122. pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);
  1123. pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);
  1124. }
  1125. /**
  1126. * aer_remove - clean up resources
  1127. * @dev: pointer to the pcie_dev data structure
  1128. *
  1129. * Invoked when PCI Express bus unloads or AER probe fails.
  1130. */
  1131. static void aer_remove(struct pcie_device *dev)
  1132. {
  1133. struct aer_rpc *rpc = get_service_data(dev);
  1134. aer_disable_rootport(rpc);
  1135. }
  1136. /**
  1137. * aer_probe - initialize resources
  1138. * @dev: pointer to the pcie_dev data structure
  1139. *
  1140. * Invoked when PCI Express bus loads AER service driver.
  1141. */
  1142. static int aer_probe(struct pcie_device *dev)
  1143. {
  1144. int status;
  1145. struct aer_rpc *rpc;
  1146. struct device *device = &dev->device;
  1147. struct pci_dev *port = dev->port;
  1148. BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) <
  1149. AER_MAX_TYPEOF_COR_ERRS);
  1150. BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) <
  1151. AER_MAX_TYPEOF_UNCOR_ERRS);
  1152. /* Limit to Root Ports or Root Complex Event Collectors */
  1153. if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) &&
  1154. (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT))
  1155. return -ENODEV;
  1156. rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL);
  1157. if (!rpc)
  1158. return -ENOMEM;
  1159. rpc->rpd = port;
  1160. INIT_KFIFO(rpc->aer_fifo);
  1161. set_service_data(dev, rpc);
  1162. status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr,
  1163. IRQF_SHARED, "aerdrv", dev);
  1164. if (status) {
  1165. pci_err(port, "request AER IRQ %d failed\n", dev->irq);
  1166. return status;
  1167. }
  1168. aer_enable_rootport(rpc);
  1169. pci_info(port, "enabled with IRQ %d\n", dev->irq);
  1170. return 0;
  1171. }
  1172. /**
  1173. * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP
  1174. * @dev: pointer to Root Port, RCEC, or RCiEP
  1175. *
  1176. * Invoked by Port Bus driver when performing reset.
  1177. */
  1178. static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
  1179. {
  1180. int type = pci_pcie_type(dev);
  1181. struct pci_dev *root;
  1182. int aer;
  1183. struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
  1184. u32 reg32;
  1185. int rc;
  1186. /*
  1187. * Only Root Ports and RCECs have AER Root Command and Root Status
  1188. * registers. If "dev" is an RCiEP, the relevant registers are in
  1189. * the RCEC.
  1190. */
  1191. if (type == PCI_EXP_TYPE_RC_END)
  1192. root = dev->rcec;
  1193. else
  1194. root = pcie_find_root_port(dev);
  1195. /*
  1196. * If the platform retained control of AER, an RCiEP may not have
  1197. * an RCEC visible to us, so dev->rcec ("root") may be NULL. In
  1198. * that case, firmware is responsible for these registers.
  1199. */
  1200. aer = root ? root->aer_cap : 0;
  1201. if ((host->native_aer || pcie_ports_native) && aer) {
  1202. /* Disable Root's interrupt in response to error messages */
  1203. pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1204. reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
  1205. pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1206. }
  1207. if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) {
  1208. rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET);
  1209. if (!rc)
  1210. pci_info(dev, "has been reset\n");
  1211. else
  1212. pci_info(dev, "not reset (no FLR support: %d)\n", rc);
  1213. } else {
  1214. rc = pci_bus_error_reset(dev);
  1215. pci_info(dev, "%s Port link has been reset (%d)\n",
  1216. pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc);
  1217. }
  1218. if ((host->native_aer || pcie_ports_native) && aer) {
  1219. /* Clear Root Error Status */
  1220. pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32);
  1221. pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);
  1222. /* Enable Root Port's interrupt in response to error messages */
  1223. pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);
  1224. reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
  1225. pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);
  1226. }
  1227. return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
  1228. }
  1229. static struct pcie_port_service_driver aerdriver = {
  1230. .name = "aer",
  1231. .port_type = PCIE_ANY_PORT,
  1232. .service = PCIE_PORT_SERVICE_AER,
  1233. .probe = aer_probe,
  1234. .remove = aer_remove,
  1235. };
  1236. /**
  1237. * pcie_aer_init - register AER root service driver
  1238. *
  1239. * Invoked when AER root service driver is loaded.
  1240. */
  1241. int __init pcie_aer_init(void)
  1242. {
  1243. if (!pci_aer_available())
  1244. return -ENXIO;
  1245. return pcie_port_service_register(&aerdriver);
  1246. }