pcie-hisi.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe host controller driver for HiSilicon SoCs
  4. *
  5. * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
  6. *
  7. * Authors: Zhou Wang <[email protected]>
  8. * Dacai Zhu <[email protected]>
  9. * Gabriele Paoloni <[email protected]>
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/init.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pci.h>
  15. #include <linux/pci-acpi.h>
  16. #include <linux/pci-ecam.h>
  17. #include "../../pci.h"
  18. #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
  19. struct hisi_pcie {
  20. void __iomem *reg_base;
  21. };
  22. static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  23. int size, u32 *val)
  24. {
  25. struct pci_config_window *cfg = bus->sysdata;
  26. int dev = PCI_SLOT(devfn);
  27. if (bus->number == cfg->busr.start) {
  28. /* access only one slot on each root port */
  29. if (dev > 0)
  30. return PCIBIOS_DEVICE_NOT_FOUND;
  31. else
  32. return pci_generic_config_read32(bus, devfn, where,
  33. size, val);
  34. }
  35. return pci_generic_config_read(bus, devfn, where, size, val);
  36. }
  37. static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
  38. int where, int size, u32 val)
  39. {
  40. struct pci_config_window *cfg = bus->sysdata;
  41. int dev = PCI_SLOT(devfn);
  42. if (bus->number == cfg->busr.start) {
  43. /* access only one slot on each root port */
  44. if (dev > 0)
  45. return PCIBIOS_DEVICE_NOT_FOUND;
  46. else
  47. return pci_generic_config_write32(bus, devfn, where,
  48. size, val);
  49. }
  50. return pci_generic_config_write(bus, devfn, where, size, val);
  51. }
  52. static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
  53. int where)
  54. {
  55. struct pci_config_window *cfg = bus->sysdata;
  56. struct hisi_pcie *pcie = cfg->priv;
  57. if (bus->number == cfg->busr.start)
  58. return pcie->reg_base + where;
  59. else
  60. return pci_ecam_map_bus(bus, devfn, where);
  61. }
  62. #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
  63. static int hisi_pcie_init(struct pci_config_window *cfg)
  64. {
  65. struct device *dev = cfg->parent;
  66. struct hisi_pcie *pcie;
  67. struct acpi_device *adev = to_acpi_device(dev);
  68. struct acpi_pci_root *root = acpi_driver_data(adev);
  69. struct resource *res;
  70. int ret;
  71. pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  72. if (!pcie)
  73. return -ENOMEM;
  74. /*
  75. * Retrieve RC base and size from a HISI0081 device with _UID
  76. * matching our segment.
  77. */
  78. res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
  79. if (!res)
  80. return -ENOMEM;
  81. ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
  82. if (ret) {
  83. dev_err(dev, "can't get rc base address\n");
  84. return -ENOMEM;
  85. }
  86. pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
  87. if (!pcie->reg_base)
  88. return -ENOMEM;
  89. cfg->priv = pcie;
  90. return 0;
  91. }
  92. const struct pci_ecam_ops hisi_pcie_ops = {
  93. .init = hisi_pcie_init,
  94. .pci_ops = {
  95. .map_bus = hisi_pcie_map_bus,
  96. .read = hisi_pcie_rd_conf,
  97. .write = hisi_pcie_wr_conf,
  98. }
  99. };
  100. #endif
  101. #ifdef CONFIG_PCI_HISI
  102. static int hisi_pcie_platform_init(struct pci_config_window *cfg)
  103. {
  104. struct device *dev = cfg->parent;
  105. struct hisi_pcie *pcie;
  106. struct platform_device *pdev = to_platform_device(dev);
  107. struct resource *res;
  108. pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
  109. if (!pcie)
  110. return -ENOMEM;
  111. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  112. if (!res) {
  113. dev_err(dev, "missing \"reg[1]\"property\n");
  114. return -EINVAL;
  115. }
  116. pcie->reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
  117. if (!pcie->reg_base)
  118. return -ENOMEM;
  119. cfg->priv = pcie;
  120. return 0;
  121. }
  122. static const struct pci_ecam_ops hisi_pcie_platform_ops = {
  123. .init = hisi_pcie_platform_init,
  124. .pci_ops = {
  125. .map_bus = hisi_pcie_map_bus,
  126. .read = hisi_pcie_rd_conf,
  127. .write = hisi_pcie_wr_conf,
  128. }
  129. };
  130. static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
  131. {
  132. .compatible = "hisilicon,hip06-pcie-ecam",
  133. .data = &hisi_pcie_platform_ops,
  134. },
  135. {
  136. .compatible = "hisilicon,hip07-pcie-ecam",
  137. .data = &hisi_pcie_platform_ops,
  138. },
  139. {},
  140. };
  141. static struct platform_driver hisi_pcie_almost_ecam_driver = {
  142. .probe = pci_host_common_probe,
  143. .driver = {
  144. .name = "hisi-pcie-almost-ecam",
  145. .of_match_table = hisi_pcie_almost_ecam_of_match,
  146. .suppress_bind_attrs = true,
  147. },
  148. };
  149. builtin_platform_driver(hisi_pcie_almost_ecam_driver);
  150. #endif
  151. #endif