pcie-designware-plat.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe RC driver for Synopsys DesignWare Core
  4. *
  5. * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
  6. *
  7. * Authors: Joao Pinto <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/gpio.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/of_device.h>
  16. #include <linux/pci.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/resource.h>
  19. #include <linux/types.h>
  20. #include "pcie-designware.h"
  21. struct dw_plat_pcie {
  22. struct dw_pcie *pci;
  23. enum dw_pcie_device_mode mode;
  24. };
  25. struct dw_plat_pcie_of_data {
  26. enum dw_pcie_device_mode mode;
  27. };
  28. static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
  29. };
  30. static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
  31. {
  32. struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  33. enum pci_barno bar;
  34. for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
  35. dw_pcie_ep_reset_bar(pci, bar);
  36. }
  37. static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
  38. enum pci_epc_irq_type type,
  39. u16 interrupt_num)
  40. {
  41. struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
  42. switch (type) {
  43. case PCI_EPC_IRQ_LEGACY:
  44. return dw_pcie_ep_raise_legacy_irq(ep, func_no);
  45. case PCI_EPC_IRQ_MSI:
  46. return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
  47. case PCI_EPC_IRQ_MSIX:
  48. return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
  49. default:
  50. dev_err(pci->dev, "UNKNOWN IRQ type\n");
  51. }
  52. return 0;
  53. }
  54. static const struct pci_epc_features dw_plat_pcie_epc_features = {
  55. .linkup_notifier = false,
  56. .msi_capable = true,
  57. .msix_capable = true,
  58. };
  59. static const struct pci_epc_features*
  60. dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
  61. {
  62. return &dw_plat_pcie_epc_features;
  63. }
  64. static const struct dw_pcie_ep_ops pcie_ep_ops = {
  65. .ep_init = dw_plat_pcie_ep_init,
  66. .raise_irq = dw_plat_pcie_ep_raise_irq,
  67. .get_features = dw_plat_pcie_get_features,
  68. };
  69. static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
  70. struct platform_device *pdev)
  71. {
  72. struct dw_pcie *pci = dw_plat_pcie->pci;
  73. struct dw_pcie_rp *pp = &pci->pp;
  74. struct device *dev = &pdev->dev;
  75. int ret;
  76. pp->irq = platform_get_irq(pdev, 1);
  77. if (pp->irq < 0)
  78. return pp->irq;
  79. pp->num_vectors = MAX_MSI_IRQS;
  80. pp->ops = &dw_plat_pcie_host_ops;
  81. ret = dw_pcie_host_init(pp);
  82. if (ret) {
  83. dev_err(dev, "Failed to initialize host\n");
  84. return ret;
  85. }
  86. return 0;
  87. }
  88. static int dw_plat_pcie_probe(struct platform_device *pdev)
  89. {
  90. struct device *dev = &pdev->dev;
  91. struct dw_plat_pcie *dw_plat_pcie;
  92. struct dw_pcie *pci;
  93. int ret;
  94. const struct dw_plat_pcie_of_data *data;
  95. enum dw_pcie_device_mode mode;
  96. data = of_device_get_match_data(dev);
  97. if (!data)
  98. return -EINVAL;
  99. mode = (enum dw_pcie_device_mode)data->mode;
  100. dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
  101. if (!dw_plat_pcie)
  102. return -ENOMEM;
  103. pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
  104. if (!pci)
  105. return -ENOMEM;
  106. pci->dev = dev;
  107. dw_plat_pcie->pci = pci;
  108. dw_plat_pcie->mode = mode;
  109. platform_set_drvdata(pdev, dw_plat_pcie);
  110. switch (dw_plat_pcie->mode) {
  111. case DW_PCIE_RC_TYPE:
  112. if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
  113. return -ENODEV;
  114. ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
  115. break;
  116. case DW_PCIE_EP_TYPE:
  117. if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
  118. return -ENODEV;
  119. pci->ep.ops = &pcie_ep_ops;
  120. ret = dw_pcie_ep_init(&pci->ep);
  121. break;
  122. default:
  123. dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
  124. ret = -EINVAL;
  125. break;
  126. }
  127. return ret;
  128. }
  129. static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
  130. .mode = DW_PCIE_RC_TYPE,
  131. };
  132. static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
  133. .mode = DW_PCIE_EP_TYPE,
  134. };
  135. static const struct of_device_id dw_plat_pcie_of_match[] = {
  136. {
  137. .compatible = "snps,dw-pcie",
  138. .data = &dw_plat_pcie_rc_of_data,
  139. },
  140. {
  141. .compatible = "snps,dw-pcie-ep",
  142. .data = &dw_plat_pcie_ep_of_data,
  143. },
  144. {},
  145. };
  146. static struct platform_driver dw_plat_pcie_driver = {
  147. .driver = {
  148. .name = "dw-pcie",
  149. .of_match_table = dw_plat_pcie_of_match,
  150. .suppress_bind_attrs = true,
  151. },
  152. .probe = dw_plat_pcie_probe,
  153. };
  154. builtin_platform_driver(dw_plat_pcie_driver);