pci.c 97 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NVM Express device driver
  4. * Copyright (c) 2011-2014, Intel Corporation.
  5. */
  6. #include <linux/acpi.h>
  7. #include <linux/aer.h>
  8. #include <linux/async.h>
  9. #include <linux/blkdev.h>
  10. #include <linux/blk-mq.h>
  11. #include <linux/blk-mq-pci.h>
  12. #include <linux/blk-integrity.h>
  13. #include <linux/dmi.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/memremap.h>
  18. #include <linux/mm.h>
  19. #include <linux/module.h>
  20. #include <linux/mutex.h>
  21. #include <linux/once.h>
  22. #include <linux/pci.h>
  23. #include <linux/suspend.h>
  24. #include <linux/t10-pi.h>
  25. #include <linux/types.h>
  26. #include <linux/io-64-nonatomic-lo-hi.h>
  27. #include <linux/io-64-nonatomic-hi-lo.h>
  28. #include <linux/sed-opal.h>
  29. #include <linux/pci-p2pdma.h>
  30. #include "trace.h"
  31. #include "nvme.h"
  32. #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
  33. #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
  34. #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  35. /*
  36. * These can be higher, but we need to ensure that any command doesn't
  37. * require an sg allocation that needs more than a page of data.
  38. */
  39. #define NVME_MAX_KB_SZ 4096
  40. #define NVME_MAX_SEGS 127
  41. static int use_threaded_interrupts;
  42. module_param(use_threaded_interrupts, int, 0444);
  43. static bool use_cmb_sqes = true;
  44. module_param(use_cmb_sqes, bool, 0444);
  45. MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  46. static unsigned int max_host_mem_size_mb = 128;
  47. module_param(max_host_mem_size_mb, uint, 0444);
  48. MODULE_PARM_DESC(max_host_mem_size_mb,
  49. "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  50. static unsigned int sgl_threshold = SZ_32K;
  51. module_param(sgl_threshold, uint, 0644);
  52. MODULE_PARM_DESC(sgl_threshold,
  53. "Use SGLs when average request segment size is larger or equal to "
  54. "this size. Use 0 to disable SGLs.");
  55. #define NVME_PCI_MIN_QUEUE_SIZE 2
  56. #define NVME_PCI_MAX_QUEUE_SIZE 4095
  57. static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  58. static const struct kernel_param_ops io_queue_depth_ops = {
  59. .set = io_queue_depth_set,
  60. .get = param_get_uint,
  61. };
  62. static unsigned int io_queue_depth = 1024;
  63. module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  64. MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  65. static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  66. {
  67. unsigned int n;
  68. int ret;
  69. ret = kstrtouint(val, 10, &n);
  70. if (ret != 0 || n > num_possible_cpus())
  71. return -EINVAL;
  72. return param_set_uint(val, kp);
  73. }
  74. static const struct kernel_param_ops io_queue_count_ops = {
  75. .set = io_queue_count_set,
  76. .get = param_get_uint,
  77. };
  78. static unsigned int write_queues;
  79. module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  80. MODULE_PARM_DESC(write_queues,
  81. "Number of queues to use for writes. If not set, reads and writes "
  82. "will share a queue set.");
  83. static unsigned int poll_queues;
  84. module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  85. MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  86. static bool noacpi;
  87. module_param(noacpi, bool, 0444);
  88. MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
  89. struct nvme_dev;
  90. struct nvme_queue;
  91. static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  92. static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
  93. static void nvme_update_attrs(struct nvme_dev *dev);
  94. /*
  95. * Represents an NVM Express device. Each nvme_dev is a PCI function.
  96. */
  97. struct nvme_dev {
  98. struct nvme_queue *queues;
  99. struct blk_mq_tag_set tagset;
  100. struct blk_mq_tag_set admin_tagset;
  101. u32 __iomem *dbs;
  102. struct device *dev;
  103. struct dma_pool *prp_page_pool;
  104. struct dma_pool *prp_small_pool;
  105. unsigned online_queues;
  106. unsigned max_qid;
  107. unsigned io_queues[HCTX_MAX_TYPES];
  108. unsigned int num_vecs;
  109. u32 q_depth;
  110. int io_sqes;
  111. u32 db_stride;
  112. void __iomem *bar;
  113. unsigned long bar_mapped_size;
  114. struct work_struct remove_work;
  115. struct mutex shutdown_lock;
  116. bool subsystem;
  117. u64 cmb_size;
  118. bool cmb_use_sqes;
  119. u32 cmbsz;
  120. u32 cmbloc;
  121. struct nvme_ctrl ctrl;
  122. u32 last_ps;
  123. bool hmb;
  124. mempool_t *iod_mempool;
  125. /* shadow doorbell buffer support: */
  126. __le32 *dbbuf_dbs;
  127. dma_addr_t dbbuf_dbs_dma_addr;
  128. __le32 *dbbuf_eis;
  129. dma_addr_t dbbuf_eis_dma_addr;
  130. /* host memory buffer support: */
  131. u64 host_mem_size;
  132. u32 nr_host_mem_descs;
  133. dma_addr_t host_mem_descs_dma;
  134. struct nvme_host_mem_buf_desc *host_mem_descs;
  135. void **host_mem_desc_bufs;
  136. unsigned int nr_allocated_queues;
  137. unsigned int nr_write_queues;
  138. unsigned int nr_poll_queues;
  139. };
  140. static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
  141. {
  142. return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
  143. NVME_PCI_MAX_QUEUE_SIZE);
  144. }
  145. static inline unsigned int sq_idx(unsigned int qid, u32 stride)
  146. {
  147. return qid * 2 * stride;
  148. }
  149. static inline unsigned int cq_idx(unsigned int qid, u32 stride)
  150. {
  151. return (qid * 2 + 1) * stride;
  152. }
  153. static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
  154. {
  155. return container_of(ctrl, struct nvme_dev, ctrl);
  156. }
  157. /*
  158. * An NVM Express queue. Each device has at least two (one for admin
  159. * commands and one for I/O commands).
  160. */
  161. struct nvme_queue {
  162. struct nvme_dev *dev;
  163. spinlock_t sq_lock;
  164. void *sq_cmds;
  165. /* only used for poll queues: */
  166. spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
  167. struct nvme_completion *cqes;
  168. dma_addr_t sq_dma_addr;
  169. dma_addr_t cq_dma_addr;
  170. u32 __iomem *q_db;
  171. u32 q_depth;
  172. u16 cq_vector;
  173. u16 sq_tail;
  174. u16 last_sq_tail;
  175. u16 cq_head;
  176. u16 qid;
  177. u8 cq_phase;
  178. u8 sqes;
  179. unsigned long flags;
  180. #define NVMEQ_ENABLED 0
  181. #define NVMEQ_SQ_CMB 1
  182. #define NVMEQ_DELETE_ERROR 2
  183. #define NVMEQ_POLLED 3
  184. __le32 *dbbuf_sq_db;
  185. __le32 *dbbuf_cq_db;
  186. __le32 *dbbuf_sq_ei;
  187. __le32 *dbbuf_cq_ei;
  188. struct completion delete_done;
  189. };
  190. /*
  191. * The nvme_iod describes the data in an I/O.
  192. *
  193. * The sg pointer contains the list of PRP/SGL chunk allocations in addition
  194. * to the actual struct scatterlist.
  195. */
  196. struct nvme_iod {
  197. struct nvme_request req;
  198. struct nvme_command cmd;
  199. bool use_sgl;
  200. bool aborted;
  201. s8 nr_allocations; /* PRP list pool allocations. 0 means small
  202. pool in use */
  203. unsigned int dma_len; /* length of single DMA segment mapping */
  204. dma_addr_t first_dma;
  205. dma_addr_t meta_dma;
  206. struct sg_table sgt;
  207. };
  208. static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
  209. {
  210. return dev->nr_allocated_queues * 8 * dev->db_stride;
  211. }
  212. static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
  213. {
  214. unsigned int mem_size = nvme_dbbuf_size(dev);
  215. if (dev->dbbuf_dbs) {
  216. /*
  217. * Clear the dbbuf memory so the driver doesn't observe stale
  218. * values from the previous instantiation.
  219. */
  220. memset(dev->dbbuf_dbs, 0, mem_size);
  221. memset(dev->dbbuf_eis, 0, mem_size);
  222. return 0;
  223. }
  224. dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
  225. &dev->dbbuf_dbs_dma_addr,
  226. GFP_KERNEL);
  227. if (!dev->dbbuf_dbs)
  228. return -ENOMEM;
  229. dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
  230. &dev->dbbuf_eis_dma_addr,
  231. GFP_KERNEL);
  232. if (!dev->dbbuf_eis) {
  233. dma_free_coherent(dev->dev, mem_size,
  234. dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
  235. dev->dbbuf_dbs = NULL;
  236. return -ENOMEM;
  237. }
  238. return 0;
  239. }
  240. static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
  241. {
  242. unsigned int mem_size = nvme_dbbuf_size(dev);
  243. if (dev->dbbuf_dbs) {
  244. dma_free_coherent(dev->dev, mem_size,
  245. dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
  246. dev->dbbuf_dbs = NULL;
  247. }
  248. if (dev->dbbuf_eis) {
  249. dma_free_coherent(dev->dev, mem_size,
  250. dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
  251. dev->dbbuf_eis = NULL;
  252. }
  253. }
  254. static void nvme_dbbuf_init(struct nvme_dev *dev,
  255. struct nvme_queue *nvmeq, int qid)
  256. {
  257. if (!dev->dbbuf_dbs || !qid)
  258. return;
  259. nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
  260. nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
  261. nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
  262. nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
  263. }
  264. static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
  265. {
  266. if (!nvmeq->qid)
  267. return;
  268. nvmeq->dbbuf_sq_db = NULL;
  269. nvmeq->dbbuf_cq_db = NULL;
  270. nvmeq->dbbuf_sq_ei = NULL;
  271. nvmeq->dbbuf_cq_ei = NULL;
  272. }
  273. static void nvme_dbbuf_set(struct nvme_dev *dev)
  274. {
  275. struct nvme_command c = { };
  276. unsigned int i;
  277. if (!dev->dbbuf_dbs)
  278. return;
  279. c.dbbuf.opcode = nvme_admin_dbbuf;
  280. c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
  281. c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
  282. if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
  283. dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
  284. /* Free memory and continue on */
  285. nvme_dbbuf_dma_free(dev);
  286. for (i = 1; i <= dev->online_queues; i++)
  287. nvme_dbbuf_free(&dev->queues[i]);
  288. }
  289. }
  290. static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
  291. {
  292. return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
  293. }
  294. /* Update dbbuf and return true if an MMIO is required */
  295. static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
  296. volatile __le32 *dbbuf_ei)
  297. {
  298. if (dbbuf_db) {
  299. u16 old_value, event_idx;
  300. /*
  301. * Ensure that the queue is written before updating
  302. * the doorbell in memory
  303. */
  304. wmb();
  305. old_value = le32_to_cpu(*dbbuf_db);
  306. *dbbuf_db = cpu_to_le32(value);
  307. /*
  308. * Ensure that the doorbell is updated before reading the event
  309. * index from memory. The controller needs to provide similar
  310. * ordering to ensure the envent index is updated before reading
  311. * the doorbell.
  312. */
  313. mb();
  314. event_idx = le32_to_cpu(*dbbuf_ei);
  315. if (!nvme_dbbuf_need_event(event_idx, value, old_value))
  316. return false;
  317. }
  318. return true;
  319. }
  320. /*
  321. * Will slightly overestimate the number of pages needed. This is OK
  322. * as it only leads to a small amount of wasted memory for the lifetime of
  323. * the I/O.
  324. */
  325. static int nvme_pci_npages_prp(void)
  326. {
  327. unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
  328. unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
  329. return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
  330. }
  331. /*
  332. * Calculates the number of pages needed for the SGL segments. For example a 4k
  333. * page can accommodate 256 SGL descriptors.
  334. */
  335. static int nvme_pci_npages_sgl(void)
  336. {
  337. return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
  338. NVME_CTRL_PAGE_SIZE);
  339. }
  340. static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  341. unsigned int hctx_idx)
  342. {
  343. struct nvme_dev *dev = data;
  344. struct nvme_queue *nvmeq = &dev->queues[0];
  345. WARN_ON(hctx_idx != 0);
  346. WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
  347. hctx->driver_data = nvmeq;
  348. return 0;
  349. }
  350. static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  351. unsigned int hctx_idx)
  352. {
  353. struct nvme_dev *dev = data;
  354. struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
  355. WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
  356. hctx->driver_data = nvmeq;
  357. return 0;
  358. }
  359. static int nvme_pci_init_request(struct blk_mq_tag_set *set,
  360. struct request *req, unsigned int hctx_idx,
  361. unsigned int numa_node)
  362. {
  363. struct nvme_dev *dev = set->driver_data;
  364. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  365. nvme_req(req)->ctrl = &dev->ctrl;
  366. nvme_req(req)->cmd = &iod->cmd;
  367. return 0;
  368. }
  369. static int queue_irq_offset(struct nvme_dev *dev)
  370. {
  371. /* if we have more than 1 vec, admin queue offsets us by 1 */
  372. if (dev->num_vecs > 1)
  373. return 1;
  374. return 0;
  375. }
  376. static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
  377. {
  378. struct nvme_dev *dev = set->driver_data;
  379. int i, qoff, offset;
  380. offset = queue_irq_offset(dev);
  381. for (i = 0, qoff = 0; i < set->nr_maps; i++) {
  382. struct blk_mq_queue_map *map = &set->map[i];
  383. map->nr_queues = dev->io_queues[i];
  384. if (!map->nr_queues) {
  385. BUG_ON(i == HCTX_TYPE_DEFAULT);
  386. continue;
  387. }
  388. /*
  389. * The poll queue(s) doesn't have an IRQ (and hence IRQ
  390. * affinity), so use the regular blk-mq cpu mapping
  391. */
  392. map->queue_offset = qoff;
  393. if (i != HCTX_TYPE_POLL && offset)
  394. blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
  395. else
  396. blk_mq_map_queues(map);
  397. qoff += map->nr_queues;
  398. offset += map->nr_queues;
  399. }
  400. }
  401. /*
  402. * Write sq tail if we are asked to, or if the next command would wrap.
  403. */
  404. static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
  405. {
  406. if (!write_sq) {
  407. u16 next_tail = nvmeq->sq_tail + 1;
  408. if (next_tail == nvmeq->q_depth)
  409. next_tail = 0;
  410. if (next_tail != nvmeq->last_sq_tail)
  411. return;
  412. }
  413. if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
  414. nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
  415. writel(nvmeq->sq_tail, nvmeq->q_db);
  416. nvmeq->last_sq_tail = nvmeq->sq_tail;
  417. }
  418. static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
  419. struct nvme_command *cmd)
  420. {
  421. memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
  422. absolute_pointer(cmd), sizeof(*cmd));
  423. if (++nvmeq->sq_tail == nvmeq->q_depth)
  424. nvmeq->sq_tail = 0;
  425. }
  426. static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
  427. {
  428. struct nvme_queue *nvmeq = hctx->driver_data;
  429. spin_lock(&nvmeq->sq_lock);
  430. if (nvmeq->sq_tail != nvmeq->last_sq_tail)
  431. nvme_write_sq_db(nvmeq, true);
  432. spin_unlock(&nvmeq->sq_lock);
  433. }
  434. static void **nvme_pci_iod_list(struct request *req)
  435. {
  436. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  437. return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
  438. }
  439. static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
  440. {
  441. struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
  442. int nseg = blk_rq_nr_phys_segments(req);
  443. unsigned int avg_seg_size;
  444. avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
  445. if (!nvme_ctrl_sgl_supported(&dev->ctrl))
  446. return false;
  447. if (!nvmeq->qid)
  448. return false;
  449. if (!sgl_threshold || avg_seg_size < sgl_threshold)
  450. return false;
  451. return true;
  452. }
  453. static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
  454. {
  455. const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
  456. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  457. dma_addr_t dma_addr = iod->first_dma;
  458. int i;
  459. for (i = 0; i < iod->nr_allocations; i++) {
  460. __le64 *prp_list = nvme_pci_iod_list(req)[i];
  461. dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
  462. dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
  463. dma_addr = next_dma_addr;
  464. }
  465. }
  466. static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
  467. {
  468. const int last_sg = SGES_PER_PAGE - 1;
  469. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  470. dma_addr_t dma_addr = iod->first_dma;
  471. int i;
  472. for (i = 0; i < iod->nr_allocations; i++) {
  473. struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
  474. dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
  475. dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
  476. dma_addr = next_dma_addr;
  477. }
  478. }
  479. static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
  480. {
  481. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  482. if (iod->dma_len) {
  483. dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
  484. rq_dma_dir(req));
  485. return;
  486. }
  487. WARN_ON_ONCE(!iod->sgt.nents);
  488. dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
  489. if (iod->nr_allocations == 0)
  490. dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
  491. iod->first_dma);
  492. else if (iod->use_sgl)
  493. nvme_free_sgls(dev, req);
  494. else
  495. nvme_free_prps(dev, req);
  496. mempool_free(iod->sgt.sgl, dev->iod_mempool);
  497. }
  498. static void nvme_print_sgl(struct scatterlist *sgl, int nents)
  499. {
  500. int i;
  501. struct scatterlist *sg;
  502. for_each_sg(sgl, sg, nents, i) {
  503. dma_addr_t phys = sg_phys(sg);
  504. pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
  505. "dma_address:%pad dma_length:%d\n",
  506. i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
  507. sg_dma_len(sg));
  508. }
  509. }
  510. static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
  511. struct request *req, struct nvme_rw_command *cmnd)
  512. {
  513. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  514. struct dma_pool *pool;
  515. int length = blk_rq_payload_bytes(req);
  516. struct scatterlist *sg = iod->sgt.sgl;
  517. int dma_len = sg_dma_len(sg);
  518. u64 dma_addr = sg_dma_address(sg);
  519. int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
  520. __le64 *prp_list;
  521. void **list = nvme_pci_iod_list(req);
  522. dma_addr_t prp_dma;
  523. int nprps, i;
  524. length -= (NVME_CTRL_PAGE_SIZE - offset);
  525. if (length <= 0) {
  526. iod->first_dma = 0;
  527. goto done;
  528. }
  529. dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
  530. if (dma_len) {
  531. dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
  532. } else {
  533. sg = sg_next(sg);
  534. dma_addr = sg_dma_address(sg);
  535. dma_len = sg_dma_len(sg);
  536. }
  537. if (length <= NVME_CTRL_PAGE_SIZE) {
  538. iod->first_dma = dma_addr;
  539. goto done;
  540. }
  541. nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
  542. if (nprps <= (256 / 8)) {
  543. pool = dev->prp_small_pool;
  544. iod->nr_allocations = 0;
  545. } else {
  546. pool = dev->prp_page_pool;
  547. iod->nr_allocations = 1;
  548. }
  549. prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
  550. if (!prp_list) {
  551. iod->nr_allocations = -1;
  552. return BLK_STS_RESOURCE;
  553. }
  554. list[0] = prp_list;
  555. iod->first_dma = prp_dma;
  556. i = 0;
  557. for (;;) {
  558. if (i == NVME_CTRL_PAGE_SIZE >> 3) {
  559. __le64 *old_prp_list = prp_list;
  560. prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
  561. if (!prp_list)
  562. goto free_prps;
  563. list[iod->nr_allocations++] = prp_list;
  564. prp_list[0] = old_prp_list[i - 1];
  565. old_prp_list[i - 1] = cpu_to_le64(prp_dma);
  566. i = 1;
  567. }
  568. prp_list[i++] = cpu_to_le64(dma_addr);
  569. dma_len -= NVME_CTRL_PAGE_SIZE;
  570. dma_addr += NVME_CTRL_PAGE_SIZE;
  571. length -= NVME_CTRL_PAGE_SIZE;
  572. if (length <= 0)
  573. break;
  574. if (dma_len > 0)
  575. continue;
  576. if (unlikely(dma_len < 0))
  577. goto bad_sgl;
  578. sg = sg_next(sg);
  579. dma_addr = sg_dma_address(sg);
  580. dma_len = sg_dma_len(sg);
  581. }
  582. done:
  583. cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
  584. cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
  585. return BLK_STS_OK;
  586. free_prps:
  587. nvme_free_prps(dev, req);
  588. return BLK_STS_RESOURCE;
  589. bad_sgl:
  590. WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
  591. "Invalid SGL for payload:%d nents:%d\n",
  592. blk_rq_payload_bytes(req), iod->sgt.nents);
  593. return BLK_STS_IOERR;
  594. }
  595. static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
  596. struct scatterlist *sg)
  597. {
  598. sge->addr = cpu_to_le64(sg_dma_address(sg));
  599. sge->length = cpu_to_le32(sg_dma_len(sg));
  600. sge->type = NVME_SGL_FMT_DATA_DESC << 4;
  601. }
  602. static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
  603. dma_addr_t dma_addr, int entries)
  604. {
  605. sge->addr = cpu_to_le64(dma_addr);
  606. if (entries < SGES_PER_PAGE) {
  607. sge->length = cpu_to_le32(entries * sizeof(*sge));
  608. sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
  609. } else {
  610. sge->length = cpu_to_le32(NVME_CTRL_PAGE_SIZE);
  611. sge->type = NVME_SGL_FMT_SEG_DESC << 4;
  612. }
  613. }
  614. static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
  615. struct request *req, struct nvme_rw_command *cmd)
  616. {
  617. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  618. struct dma_pool *pool;
  619. struct nvme_sgl_desc *sg_list;
  620. struct scatterlist *sg = iod->sgt.sgl;
  621. unsigned int entries = iod->sgt.nents;
  622. dma_addr_t sgl_dma;
  623. int i = 0;
  624. /* setting the transfer type as SGL */
  625. cmd->flags = NVME_CMD_SGL_METABUF;
  626. if (entries == 1) {
  627. nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
  628. return BLK_STS_OK;
  629. }
  630. if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
  631. pool = dev->prp_small_pool;
  632. iod->nr_allocations = 0;
  633. } else {
  634. pool = dev->prp_page_pool;
  635. iod->nr_allocations = 1;
  636. }
  637. sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
  638. if (!sg_list) {
  639. iod->nr_allocations = -1;
  640. return BLK_STS_RESOURCE;
  641. }
  642. nvme_pci_iod_list(req)[0] = sg_list;
  643. iod->first_dma = sgl_dma;
  644. nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
  645. do {
  646. if (i == SGES_PER_PAGE) {
  647. struct nvme_sgl_desc *old_sg_desc = sg_list;
  648. struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
  649. sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
  650. if (!sg_list)
  651. goto free_sgls;
  652. i = 0;
  653. nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
  654. sg_list[i++] = *link;
  655. nvme_pci_sgl_set_seg(link, sgl_dma, entries);
  656. }
  657. nvme_pci_sgl_set_data(&sg_list[i++], sg);
  658. sg = sg_next(sg);
  659. } while (--entries > 0);
  660. return BLK_STS_OK;
  661. free_sgls:
  662. nvme_free_sgls(dev, req);
  663. return BLK_STS_RESOURCE;
  664. }
  665. static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
  666. struct request *req, struct nvme_rw_command *cmnd,
  667. struct bio_vec *bv)
  668. {
  669. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  670. unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
  671. unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
  672. iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
  673. if (dma_mapping_error(dev->dev, iod->first_dma))
  674. return BLK_STS_RESOURCE;
  675. iod->dma_len = bv->bv_len;
  676. cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
  677. if (bv->bv_len > first_prp_len)
  678. cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
  679. else
  680. cmnd->dptr.prp2 = 0;
  681. return BLK_STS_OK;
  682. }
  683. static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
  684. struct request *req, struct nvme_rw_command *cmnd,
  685. struct bio_vec *bv)
  686. {
  687. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  688. iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
  689. if (dma_mapping_error(dev->dev, iod->first_dma))
  690. return BLK_STS_RESOURCE;
  691. iod->dma_len = bv->bv_len;
  692. cmnd->flags = NVME_CMD_SGL_METABUF;
  693. cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
  694. cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
  695. cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
  696. return BLK_STS_OK;
  697. }
  698. static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
  699. struct nvme_command *cmnd)
  700. {
  701. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  702. blk_status_t ret = BLK_STS_RESOURCE;
  703. int rc;
  704. if (blk_rq_nr_phys_segments(req) == 1) {
  705. struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
  706. struct bio_vec bv = req_bvec(req);
  707. if (!is_pci_p2pdma_page(bv.bv_page)) {
  708. if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
  709. return nvme_setup_prp_simple(dev, req,
  710. &cmnd->rw, &bv);
  711. if (nvmeq->qid && sgl_threshold &&
  712. nvme_ctrl_sgl_supported(&dev->ctrl))
  713. return nvme_setup_sgl_simple(dev, req,
  714. &cmnd->rw, &bv);
  715. }
  716. }
  717. iod->dma_len = 0;
  718. iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
  719. if (!iod->sgt.sgl)
  720. return BLK_STS_RESOURCE;
  721. sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
  722. iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
  723. if (!iod->sgt.orig_nents)
  724. goto out_free_sg;
  725. rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
  726. DMA_ATTR_NO_WARN);
  727. if (rc) {
  728. if (rc == -EREMOTEIO)
  729. ret = BLK_STS_TARGET;
  730. goto out_free_sg;
  731. }
  732. iod->use_sgl = nvme_pci_use_sgls(dev, req);
  733. if (iod->use_sgl)
  734. ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
  735. else
  736. ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
  737. if (ret != BLK_STS_OK)
  738. goto out_unmap_sg;
  739. return BLK_STS_OK;
  740. out_unmap_sg:
  741. dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
  742. out_free_sg:
  743. mempool_free(iod->sgt.sgl, dev->iod_mempool);
  744. return ret;
  745. }
  746. static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
  747. struct nvme_command *cmnd)
  748. {
  749. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  750. iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
  751. rq_dma_dir(req), 0);
  752. if (dma_mapping_error(dev->dev, iod->meta_dma))
  753. return BLK_STS_IOERR;
  754. cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
  755. return BLK_STS_OK;
  756. }
  757. static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
  758. {
  759. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  760. blk_status_t ret;
  761. iod->aborted = false;
  762. iod->nr_allocations = -1;
  763. iod->sgt.nents = 0;
  764. ret = nvme_setup_cmd(req->q->queuedata, req);
  765. if (ret)
  766. return ret;
  767. if (blk_rq_nr_phys_segments(req)) {
  768. ret = nvme_map_data(dev, req, &iod->cmd);
  769. if (ret)
  770. goto out_free_cmd;
  771. }
  772. if (blk_integrity_rq(req)) {
  773. ret = nvme_map_metadata(dev, req, &iod->cmd);
  774. if (ret)
  775. goto out_unmap_data;
  776. }
  777. blk_mq_start_request(req);
  778. return BLK_STS_OK;
  779. out_unmap_data:
  780. nvme_unmap_data(dev, req);
  781. out_free_cmd:
  782. nvme_cleanup_cmd(req);
  783. return ret;
  784. }
  785. /*
  786. * NOTE: ns is NULL when called on the admin queue.
  787. */
  788. static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
  789. const struct blk_mq_queue_data *bd)
  790. {
  791. struct nvme_queue *nvmeq = hctx->driver_data;
  792. struct nvme_dev *dev = nvmeq->dev;
  793. struct request *req = bd->rq;
  794. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  795. blk_status_t ret;
  796. /*
  797. * We should not need to do this, but we're still using this to
  798. * ensure we can drain requests on a dying queue.
  799. */
  800. if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
  801. return BLK_STS_IOERR;
  802. if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
  803. return nvme_fail_nonready_command(&dev->ctrl, req);
  804. ret = nvme_prep_rq(dev, req);
  805. if (unlikely(ret))
  806. return ret;
  807. spin_lock(&nvmeq->sq_lock);
  808. nvme_sq_copy_cmd(nvmeq, &iod->cmd);
  809. nvme_write_sq_db(nvmeq, bd->last);
  810. spin_unlock(&nvmeq->sq_lock);
  811. return BLK_STS_OK;
  812. }
  813. static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
  814. {
  815. spin_lock(&nvmeq->sq_lock);
  816. while (!rq_list_empty(*rqlist)) {
  817. struct request *req = rq_list_pop(rqlist);
  818. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  819. nvme_sq_copy_cmd(nvmeq, &iod->cmd);
  820. }
  821. nvme_write_sq_db(nvmeq, true);
  822. spin_unlock(&nvmeq->sq_lock);
  823. }
  824. static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
  825. {
  826. /*
  827. * We should not need to do this, but we're still using this to
  828. * ensure we can drain requests on a dying queue.
  829. */
  830. if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
  831. return false;
  832. if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
  833. return false;
  834. req->mq_hctx->tags->rqs[req->tag] = req;
  835. return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
  836. }
  837. static void nvme_queue_rqs(struct request **rqlist)
  838. {
  839. struct request *req, *next, *prev = NULL;
  840. struct request *requeue_list = NULL;
  841. rq_list_for_each_safe(rqlist, req, next) {
  842. struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
  843. if (!nvme_prep_rq_batch(nvmeq, req)) {
  844. /* detach 'req' and add to remainder list */
  845. rq_list_move(rqlist, &requeue_list, req, prev);
  846. req = prev;
  847. if (!req)
  848. continue;
  849. }
  850. if (!next || req->mq_hctx != next->mq_hctx) {
  851. /* detach rest of list, and submit */
  852. req->rq_next = NULL;
  853. nvme_submit_cmds(nvmeq, rqlist);
  854. *rqlist = next;
  855. prev = NULL;
  856. } else
  857. prev = req;
  858. }
  859. *rqlist = requeue_list;
  860. }
  861. static __always_inline void nvme_pci_unmap_rq(struct request *req)
  862. {
  863. struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
  864. struct nvme_dev *dev = nvmeq->dev;
  865. if (blk_integrity_rq(req)) {
  866. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  867. dma_unmap_page(dev->dev, iod->meta_dma,
  868. rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
  869. }
  870. if (blk_rq_nr_phys_segments(req))
  871. nvme_unmap_data(dev, req);
  872. }
  873. static void nvme_pci_complete_rq(struct request *req)
  874. {
  875. nvme_pci_unmap_rq(req);
  876. nvme_complete_rq(req);
  877. }
  878. static void nvme_pci_complete_batch(struct io_comp_batch *iob)
  879. {
  880. nvme_complete_batch(iob, nvme_pci_unmap_rq);
  881. }
  882. /* We read the CQE phase first to check if the rest of the entry is valid */
  883. static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
  884. {
  885. struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
  886. return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
  887. }
  888. static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
  889. {
  890. u16 head = nvmeq->cq_head;
  891. if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
  892. nvmeq->dbbuf_cq_ei))
  893. writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
  894. }
  895. static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
  896. {
  897. if (!nvmeq->qid)
  898. return nvmeq->dev->admin_tagset.tags[0];
  899. return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
  900. }
  901. static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
  902. struct io_comp_batch *iob, u16 idx)
  903. {
  904. struct nvme_completion *cqe = &nvmeq->cqes[idx];
  905. __u16 command_id = READ_ONCE(cqe->command_id);
  906. struct request *req;
  907. /*
  908. * AEN requests are special as they don't time out and can
  909. * survive any kind of queue freeze and often don't respond to
  910. * aborts. We don't even bother to allocate a struct request
  911. * for them but rather special case them here.
  912. */
  913. if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
  914. nvme_complete_async_event(&nvmeq->dev->ctrl,
  915. cqe->status, &cqe->result);
  916. return;
  917. }
  918. req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
  919. if (unlikely(!req)) {
  920. dev_warn(nvmeq->dev->ctrl.device,
  921. "invalid id %d completed on queue %d\n",
  922. command_id, le16_to_cpu(cqe->sq_id));
  923. return;
  924. }
  925. trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
  926. if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
  927. !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
  928. nvme_pci_complete_batch))
  929. nvme_pci_complete_rq(req);
  930. }
  931. static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
  932. {
  933. u32 tmp = nvmeq->cq_head + 1;
  934. if (tmp == nvmeq->q_depth) {
  935. nvmeq->cq_head = 0;
  936. nvmeq->cq_phase ^= 1;
  937. } else {
  938. nvmeq->cq_head = tmp;
  939. }
  940. }
  941. static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
  942. struct io_comp_batch *iob)
  943. {
  944. int found = 0;
  945. while (nvme_cqe_pending(nvmeq)) {
  946. found++;
  947. /*
  948. * load-load control dependency between phase and the rest of
  949. * the cqe requires a full read memory barrier
  950. */
  951. dma_rmb();
  952. nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
  953. nvme_update_cq_head(nvmeq);
  954. }
  955. if (found)
  956. nvme_ring_cq_doorbell(nvmeq);
  957. return found;
  958. }
  959. static irqreturn_t nvme_irq(int irq, void *data)
  960. {
  961. struct nvme_queue *nvmeq = data;
  962. DEFINE_IO_COMP_BATCH(iob);
  963. if (nvme_poll_cq(nvmeq, &iob)) {
  964. if (!rq_list_empty(iob.req_list))
  965. nvme_pci_complete_batch(&iob);
  966. return IRQ_HANDLED;
  967. }
  968. return IRQ_NONE;
  969. }
  970. static irqreturn_t nvme_irq_check(int irq, void *data)
  971. {
  972. struct nvme_queue *nvmeq = data;
  973. if (nvme_cqe_pending(nvmeq))
  974. return IRQ_WAKE_THREAD;
  975. return IRQ_NONE;
  976. }
  977. /*
  978. * Poll for completions for any interrupt driven queue
  979. * Can be called from any context.
  980. */
  981. static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
  982. {
  983. struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
  984. WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
  985. disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
  986. nvme_poll_cq(nvmeq, NULL);
  987. enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
  988. }
  989. static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
  990. {
  991. struct nvme_queue *nvmeq = hctx->driver_data;
  992. bool found;
  993. if (!nvme_cqe_pending(nvmeq))
  994. return 0;
  995. spin_lock(&nvmeq->cq_poll_lock);
  996. found = nvme_poll_cq(nvmeq, iob);
  997. spin_unlock(&nvmeq->cq_poll_lock);
  998. return found;
  999. }
  1000. static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
  1001. {
  1002. struct nvme_dev *dev = to_nvme_dev(ctrl);
  1003. struct nvme_queue *nvmeq = &dev->queues[0];
  1004. struct nvme_command c = { };
  1005. c.common.opcode = nvme_admin_async_event;
  1006. c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
  1007. spin_lock(&nvmeq->sq_lock);
  1008. nvme_sq_copy_cmd(nvmeq, &c);
  1009. nvme_write_sq_db(nvmeq, true);
  1010. spin_unlock(&nvmeq->sq_lock);
  1011. }
  1012. static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
  1013. {
  1014. struct nvme_command c = { };
  1015. c.delete_queue.opcode = opcode;
  1016. c.delete_queue.qid = cpu_to_le16(id);
  1017. return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  1018. }
  1019. static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
  1020. struct nvme_queue *nvmeq, s16 vector)
  1021. {
  1022. struct nvme_command c = { };
  1023. int flags = NVME_QUEUE_PHYS_CONTIG;
  1024. if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
  1025. flags |= NVME_CQ_IRQ_ENABLED;
  1026. /*
  1027. * Note: we (ab)use the fact that the prp fields survive if no data
  1028. * is attached to the request.
  1029. */
  1030. c.create_cq.opcode = nvme_admin_create_cq;
  1031. c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
  1032. c.create_cq.cqid = cpu_to_le16(qid);
  1033. c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  1034. c.create_cq.cq_flags = cpu_to_le16(flags);
  1035. c.create_cq.irq_vector = cpu_to_le16(vector);
  1036. return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  1037. }
  1038. static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
  1039. struct nvme_queue *nvmeq)
  1040. {
  1041. struct nvme_ctrl *ctrl = &dev->ctrl;
  1042. struct nvme_command c = { };
  1043. int flags = NVME_QUEUE_PHYS_CONTIG;
  1044. /*
  1045. * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
  1046. * set. Since URGENT priority is zeroes, it makes all queues
  1047. * URGENT.
  1048. */
  1049. if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
  1050. flags |= NVME_SQ_PRIO_MEDIUM;
  1051. /*
  1052. * Note: we (ab)use the fact that the prp fields survive if no data
  1053. * is attached to the request.
  1054. */
  1055. c.create_sq.opcode = nvme_admin_create_sq;
  1056. c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
  1057. c.create_sq.sqid = cpu_to_le16(qid);
  1058. c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  1059. c.create_sq.sq_flags = cpu_to_le16(flags);
  1060. c.create_sq.cqid = cpu_to_le16(qid);
  1061. return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  1062. }
  1063. static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
  1064. {
  1065. return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
  1066. }
  1067. static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
  1068. {
  1069. return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
  1070. }
  1071. static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
  1072. {
  1073. struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
  1074. dev_warn(nvmeq->dev->ctrl.device,
  1075. "Abort status: 0x%x", nvme_req(req)->status);
  1076. atomic_inc(&nvmeq->dev->ctrl.abort_limit);
  1077. blk_mq_free_request(req);
  1078. return RQ_END_IO_NONE;
  1079. }
  1080. static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
  1081. {
  1082. /* If true, indicates loss of adapter communication, possibly by a
  1083. * NVMe Subsystem reset.
  1084. */
  1085. bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
  1086. /* If there is a reset/reinit ongoing, we shouldn't reset again. */
  1087. switch (dev->ctrl.state) {
  1088. case NVME_CTRL_RESETTING:
  1089. case NVME_CTRL_CONNECTING:
  1090. return false;
  1091. default:
  1092. break;
  1093. }
  1094. /* We shouldn't reset unless the controller is on fatal error state
  1095. * _or_ if we lost the communication with it.
  1096. */
  1097. if (!(csts & NVME_CSTS_CFS) && !nssro)
  1098. return false;
  1099. return true;
  1100. }
  1101. static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
  1102. {
  1103. /* Read a config register to help see what died. */
  1104. u16 pci_status;
  1105. int result;
  1106. result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
  1107. &pci_status);
  1108. if (result == PCIBIOS_SUCCESSFUL)
  1109. dev_warn(dev->ctrl.device,
  1110. "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
  1111. csts, pci_status);
  1112. else
  1113. dev_warn(dev->ctrl.device,
  1114. "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
  1115. csts, result);
  1116. if (csts != ~0)
  1117. return;
  1118. dev_warn(dev->ctrl.device,
  1119. "Does your device have a faulty power saving mode enabled?\n");
  1120. dev_warn(dev->ctrl.device,
  1121. "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
  1122. }
  1123. static enum blk_eh_timer_return nvme_timeout(struct request *req)
  1124. {
  1125. struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
  1126. struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
  1127. struct nvme_dev *dev = nvmeq->dev;
  1128. struct request *abort_req;
  1129. struct nvme_command cmd = { };
  1130. u32 csts = readl(dev->bar + NVME_REG_CSTS);
  1131. /* If PCI error recovery process is happening, we cannot reset or
  1132. * the recovery mechanism will surely fail.
  1133. */
  1134. mb();
  1135. if (pci_channel_offline(to_pci_dev(dev->dev)))
  1136. return BLK_EH_RESET_TIMER;
  1137. /*
  1138. * Reset immediately if the controller is failed
  1139. */
  1140. if (nvme_should_reset(dev, csts)) {
  1141. nvme_warn_reset(dev, csts);
  1142. nvme_dev_disable(dev, false);
  1143. nvme_reset_ctrl(&dev->ctrl);
  1144. return BLK_EH_DONE;
  1145. }
  1146. /*
  1147. * Did we miss an interrupt?
  1148. */
  1149. if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
  1150. nvme_poll(req->mq_hctx, NULL);
  1151. else
  1152. nvme_poll_irqdisable(nvmeq);
  1153. if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
  1154. dev_warn(dev->ctrl.device,
  1155. "I/O %d QID %d timeout, completion polled\n",
  1156. req->tag, nvmeq->qid);
  1157. return BLK_EH_DONE;
  1158. }
  1159. /*
  1160. * Shutdown immediately if controller times out while starting. The
  1161. * reset work will see the pci device disabled when it gets the forced
  1162. * cancellation error. All outstanding requests are completed on
  1163. * shutdown, so we return BLK_EH_DONE.
  1164. */
  1165. switch (dev->ctrl.state) {
  1166. case NVME_CTRL_CONNECTING:
  1167. nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
  1168. fallthrough;
  1169. case NVME_CTRL_DELETING:
  1170. dev_warn_ratelimited(dev->ctrl.device,
  1171. "I/O %d QID %d timeout, disable controller\n",
  1172. req->tag, nvmeq->qid);
  1173. nvme_req(req)->flags |= NVME_REQ_CANCELLED;
  1174. nvme_dev_disable(dev, true);
  1175. return BLK_EH_DONE;
  1176. case NVME_CTRL_RESETTING:
  1177. return BLK_EH_RESET_TIMER;
  1178. default:
  1179. break;
  1180. }
  1181. /*
  1182. * Shutdown the controller immediately and schedule a reset if the
  1183. * command was already aborted once before and still hasn't been
  1184. * returned to the driver, or if this is the admin queue.
  1185. */
  1186. if (!nvmeq->qid || iod->aborted) {
  1187. dev_warn(dev->ctrl.device,
  1188. "I/O %d QID %d timeout, reset controller\n",
  1189. req->tag, nvmeq->qid);
  1190. nvme_req(req)->flags |= NVME_REQ_CANCELLED;
  1191. nvme_dev_disable(dev, false);
  1192. nvme_reset_ctrl(&dev->ctrl);
  1193. return BLK_EH_DONE;
  1194. }
  1195. if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
  1196. atomic_inc(&dev->ctrl.abort_limit);
  1197. return BLK_EH_RESET_TIMER;
  1198. }
  1199. iod->aborted = true;
  1200. cmd.abort.opcode = nvme_admin_abort_cmd;
  1201. cmd.abort.cid = nvme_cid(req);
  1202. cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
  1203. dev_warn(nvmeq->dev->ctrl.device,
  1204. "I/O %d (%s) QID %d timeout, aborting\n",
  1205. req->tag,
  1206. nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
  1207. nvmeq->qid);
  1208. abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
  1209. BLK_MQ_REQ_NOWAIT);
  1210. if (IS_ERR(abort_req)) {
  1211. atomic_inc(&dev->ctrl.abort_limit);
  1212. return BLK_EH_RESET_TIMER;
  1213. }
  1214. nvme_init_request(abort_req, &cmd);
  1215. abort_req->end_io = abort_endio;
  1216. abort_req->end_io_data = NULL;
  1217. blk_execute_rq_nowait(abort_req, false);
  1218. /*
  1219. * The aborted req will be completed on receiving the abort req.
  1220. * We enable the timer again. If hit twice, it'll cause a device reset,
  1221. * as the device then is in a faulty state.
  1222. */
  1223. return BLK_EH_RESET_TIMER;
  1224. }
  1225. static void nvme_free_queue(struct nvme_queue *nvmeq)
  1226. {
  1227. dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
  1228. (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
  1229. if (!nvmeq->sq_cmds)
  1230. return;
  1231. if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
  1232. pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
  1233. nvmeq->sq_cmds, SQ_SIZE(nvmeq));
  1234. } else {
  1235. dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
  1236. nvmeq->sq_cmds, nvmeq->sq_dma_addr);
  1237. }
  1238. }
  1239. static void nvme_free_queues(struct nvme_dev *dev, int lowest)
  1240. {
  1241. int i;
  1242. for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
  1243. dev->ctrl.queue_count--;
  1244. nvme_free_queue(&dev->queues[i]);
  1245. }
  1246. }
  1247. /**
  1248. * nvme_suspend_queue - put queue into suspended state
  1249. * @nvmeq: queue to suspend
  1250. */
  1251. static int nvme_suspend_queue(struct nvme_queue *nvmeq)
  1252. {
  1253. if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
  1254. return 1;
  1255. /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
  1256. mb();
  1257. nvmeq->dev->online_queues--;
  1258. if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
  1259. nvme_stop_admin_queue(&nvmeq->dev->ctrl);
  1260. if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
  1261. pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
  1262. return 0;
  1263. }
  1264. static void nvme_suspend_io_queues(struct nvme_dev *dev)
  1265. {
  1266. int i;
  1267. for (i = dev->ctrl.queue_count - 1; i > 0; i--)
  1268. nvme_suspend_queue(&dev->queues[i]);
  1269. }
  1270. static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
  1271. {
  1272. struct nvme_queue *nvmeq = &dev->queues[0];
  1273. if (shutdown)
  1274. nvme_shutdown_ctrl(&dev->ctrl);
  1275. else
  1276. nvme_disable_ctrl(&dev->ctrl);
  1277. nvme_poll_irqdisable(nvmeq);
  1278. }
  1279. /*
  1280. * Called only on a device that has been disabled and after all other threads
  1281. * that can check this device's completion queues have synced, except
  1282. * nvme_poll(). This is the last chance for the driver to see a natural
  1283. * completion before nvme_cancel_request() terminates all incomplete requests.
  1284. */
  1285. static void nvme_reap_pending_cqes(struct nvme_dev *dev)
  1286. {
  1287. int i;
  1288. for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
  1289. spin_lock(&dev->queues[i].cq_poll_lock);
  1290. nvme_poll_cq(&dev->queues[i], NULL);
  1291. spin_unlock(&dev->queues[i].cq_poll_lock);
  1292. }
  1293. }
  1294. static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
  1295. int entry_size)
  1296. {
  1297. int q_depth = dev->q_depth;
  1298. unsigned q_size_aligned = roundup(q_depth * entry_size,
  1299. NVME_CTRL_PAGE_SIZE);
  1300. if (q_size_aligned * nr_io_queues > dev->cmb_size) {
  1301. u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
  1302. mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
  1303. q_depth = div_u64(mem_per_q, entry_size);
  1304. /*
  1305. * Ensure the reduced q_depth is above some threshold where it
  1306. * would be better to map queues in system memory with the
  1307. * original depth
  1308. */
  1309. if (q_depth < 64)
  1310. return -ENOMEM;
  1311. }
  1312. return q_depth;
  1313. }
  1314. static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
  1315. int qid)
  1316. {
  1317. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1318. if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
  1319. nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
  1320. if (nvmeq->sq_cmds) {
  1321. nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
  1322. nvmeq->sq_cmds);
  1323. if (nvmeq->sq_dma_addr) {
  1324. set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
  1325. return 0;
  1326. }
  1327. pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
  1328. }
  1329. }
  1330. nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
  1331. &nvmeq->sq_dma_addr, GFP_KERNEL);
  1332. if (!nvmeq->sq_cmds)
  1333. return -ENOMEM;
  1334. return 0;
  1335. }
  1336. static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
  1337. {
  1338. struct nvme_queue *nvmeq = &dev->queues[qid];
  1339. if (dev->ctrl.queue_count > qid)
  1340. return 0;
  1341. nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
  1342. nvmeq->q_depth = depth;
  1343. nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
  1344. &nvmeq->cq_dma_addr, GFP_KERNEL);
  1345. if (!nvmeq->cqes)
  1346. goto free_nvmeq;
  1347. if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
  1348. goto free_cqdma;
  1349. nvmeq->dev = dev;
  1350. spin_lock_init(&nvmeq->sq_lock);
  1351. spin_lock_init(&nvmeq->cq_poll_lock);
  1352. nvmeq->cq_head = 0;
  1353. nvmeq->cq_phase = 1;
  1354. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1355. nvmeq->qid = qid;
  1356. dev->ctrl.queue_count++;
  1357. return 0;
  1358. free_cqdma:
  1359. dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
  1360. nvmeq->cq_dma_addr);
  1361. free_nvmeq:
  1362. return -ENOMEM;
  1363. }
  1364. static int queue_request_irq(struct nvme_queue *nvmeq)
  1365. {
  1366. struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
  1367. int nr = nvmeq->dev->ctrl.instance;
  1368. if (use_threaded_interrupts) {
  1369. return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
  1370. nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
  1371. } else {
  1372. return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
  1373. NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
  1374. }
  1375. }
  1376. static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
  1377. {
  1378. struct nvme_dev *dev = nvmeq->dev;
  1379. nvmeq->sq_tail = 0;
  1380. nvmeq->last_sq_tail = 0;
  1381. nvmeq->cq_head = 0;
  1382. nvmeq->cq_phase = 1;
  1383. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1384. memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
  1385. nvme_dbbuf_init(dev, nvmeq, qid);
  1386. dev->online_queues++;
  1387. wmb(); /* ensure the first interrupt sees the initialization */
  1388. }
  1389. /*
  1390. * Try getting shutdown_lock while setting up IO queues.
  1391. */
  1392. static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
  1393. {
  1394. /*
  1395. * Give up if the lock is being held by nvme_dev_disable.
  1396. */
  1397. if (!mutex_trylock(&dev->shutdown_lock))
  1398. return -ENODEV;
  1399. /*
  1400. * Controller is in wrong state, fail early.
  1401. */
  1402. if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
  1403. mutex_unlock(&dev->shutdown_lock);
  1404. return -ENODEV;
  1405. }
  1406. return 0;
  1407. }
  1408. static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
  1409. {
  1410. struct nvme_dev *dev = nvmeq->dev;
  1411. int result;
  1412. u16 vector = 0;
  1413. clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
  1414. /*
  1415. * A queue's vector matches the queue identifier unless the controller
  1416. * has only one vector available.
  1417. */
  1418. if (!polled)
  1419. vector = dev->num_vecs == 1 ? 0 : qid;
  1420. else
  1421. set_bit(NVMEQ_POLLED, &nvmeq->flags);
  1422. result = adapter_alloc_cq(dev, qid, nvmeq, vector);
  1423. if (result)
  1424. return result;
  1425. result = adapter_alloc_sq(dev, qid, nvmeq);
  1426. if (result < 0)
  1427. return result;
  1428. if (result)
  1429. goto release_cq;
  1430. nvmeq->cq_vector = vector;
  1431. result = nvme_setup_io_queues_trylock(dev);
  1432. if (result)
  1433. return result;
  1434. nvme_init_queue(nvmeq, qid);
  1435. if (!polled) {
  1436. result = queue_request_irq(nvmeq);
  1437. if (result < 0)
  1438. goto release_sq;
  1439. }
  1440. set_bit(NVMEQ_ENABLED, &nvmeq->flags);
  1441. mutex_unlock(&dev->shutdown_lock);
  1442. return result;
  1443. release_sq:
  1444. dev->online_queues--;
  1445. mutex_unlock(&dev->shutdown_lock);
  1446. adapter_delete_sq(dev, qid);
  1447. release_cq:
  1448. adapter_delete_cq(dev, qid);
  1449. return result;
  1450. }
  1451. static const struct blk_mq_ops nvme_mq_admin_ops = {
  1452. .queue_rq = nvme_queue_rq,
  1453. .complete = nvme_pci_complete_rq,
  1454. .init_hctx = nvme_admin_init_hctx,
  1455. .init_request = nvme_pci_init_request,
  1456. .timeout = nvme_timeout,
  1457. };
  1458. static const struct blk_mq_ops nvme_mq_ops = {
  1459. .queue_rq = nvme_queue_rq,
  1460. .queue_rqs = nvme_queue_rqs,
  1461. .complete = nvme_pci_complete_rq,
  1462. .commit_rqs = nvme_commit_rqs,
  1463. .init_hctx = nvme_init_hctx,
  1464. .init_request = nvme_pci_init_request,
  1465. .map_queues = nvme_pci_map_queues,
  1466. .timeout = nvme_timeout,
  1467. .poll = nvme_poll,
  1468. };
  1469. static void nvme_dev_remove_admin(struct nvme_dev *dev)
  1470. {
  1471. if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
  1472. /*
  1473. * If the controller was reset during removal, it's possible
  1474. * user requests may be waiting on a stopped queue. Start the
  1475. * queue to flush these to completion.
  1476. */
  1477. nvme_start_admin_queue(&dev->ctrl);
  1478. blk_mq_destroy_queue(dev->ctrl.admin_q);
  1479. blk_put_queue(dev->ctrl.admin_q);
  1480. blk_mq_free_tag_set(&dev->admin_tagset);
  1481. }
  1482. }
  1483. static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
  1484. {
  1485. struct blk_mq_tag_set *set = &dev->admin_tagset;
  1486. set->ops = &nvme_mq_admin_ops;
  1487. set->nr_hw_queues = 1;
  1488. set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
  1489. set->timeout = NVME_ADMIN_TIMEOUT;
  1490. set->numa_node = dev->ctrl.numa_node;
  1491. set->cmd_size = sizeof(struct nvme_iod);
  1492. set->flags = BLK_MQ_F_NO_SCHED;
  1493. set->driver_data = dev;
  1494. if (blk_mq_alloc_tag_set(set))
  1495. return -ENOMEM;
  1496. dev->ctrl.admin_tagset = set;
  1497. dev->ctrl.admin_q = blk_mq_init_queue(set);
  1498. if (IS_ERR(dev->ctrl.admin_q)) {
  1499. blk_mq_free_tag_set(set);
  1500. dev->ctrl.admin_q = NULL;
  1501. return -ENOMEM;
  1502. }
  1503. if (!blk_get_queue(dev->ctrl.admin_q)) {
  1504. nvme_dev_remove_admin(dev);
  1505. dev->ctrl.admin_q = NULL;
  1506. return -ENODEV;
  1507. }
  1508. return 0;
  1509. }
  1510. static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
  1511. {
  1512. return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
  1513. }
  1514. static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
  1515. {
  1516. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1517. if (size <= dev->bar_mapped_size)
  1518. return 0;
  1519. if (size > pci_resource_len(pdev, 0))
  1520. return -ENOMEM;
  1521. if (dev->bar)
  1522. iounmap(dev->bar);
  1523. dev->bar = ioremap(pci_resource_start(pdev, 0), size);
  1524. if (!dev->bar) {
  1525. dev->bar_mapped_size = 0;
  1526. return -ENOMEM;
  1527. }
  1528. dev->bar_mapped_size = size;
  1529. dev->dbs = dev->bar + NVME_REG_DBS;
  1530. return 0;
  1531. }
  1532. static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
  1533. {
  1534. int result;
  1535. u32 aqa;
  1536. struct nvme_queue *nvmeq;
  1537. result = nvme_remap_bar(dev, db_bar_size(dev, 0));
  1538. if (result < 0)
  1539. return result;
  1540. dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
  1541. NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
  1542. if (dev->subsystem &&
  1543. (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
  1544. writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
  1545. result = nvme_disable_ctrl(&dev->ctrl);
  1546. if (result < 0)
  1547. return result;
  1548. result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
  1549. if (result)
  1550. return result;
  1551. dev->ctrl.numa_node = dev_to_node(dev->dev);
  1552. nvmeq = &dev->queues[0];
  1553. aqa = nvmeq->q_depth - 1;
  1554. aqa |= aqa << 16;
  1555. writel(aqa, dev->bar + NVME_REG_AQA);
  1556. lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
  1557. lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
  1558. result = nvme_enable_ctrl(&dev->ctrl);
  1559. if (result)
  1560. return result;
  1561. nvmeq->cq_vector = 0;
  1562. nvme_init_queue(nvmeq, 0);
  1563. result = queue_request_irq(nvmeq);
  1564. if (result) {
  1565. dev->online_queues--;
  1566. return result;
  1567. }
  1568. set_bit(NVMEQ_ENABLED, &nvmeq->flags);
  1569. return result;
  1570. }
  1571. static int nvme_create_io_queues(struct nvme_dev *dev)
  1572. {
  1573. unsigned i, max, rw_queues;
  1574. int ret = 0;
  1575. for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
  1576. if (nvme_alloc_queue(dev, i, dev->q_depth)) {
  1577. ret = -ENOMEM;
  1578. break;
  1579. }
  1580. }
  1581. max = min(dev->max_qid, dev->ctrl.queue_count - 1);
  1582. if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
  1583. rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
  1584. dev->io_queues[HCTX_TYPE_READ];
  1585. } else {
  1586. rw_queues = max;
  1587. }
  1588. for (i = dev->online_queues; i <= max; i++) {
  1589. bool polled = i > rw_queues;
  1590. ret = nvme_create_queue(&dev->queues[i], i, polled);
  1591. if (ret)
  1592. break;
  1593. }
  1594. /*
  1595. * Ignore failing Create SQ/CQ commands, we can continue with less
  1596. * than the desired amount of queues, and even a controller without
  1597. * I/O queues can still be used to issue admin commands. This might
  1598. * be useful to upgrade a buggy firmware for example.
  1599. */
  1600. return ret >= 0 ? 0 : ret;
  1601. }
  1602. static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
  1603. {
  1604. u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
  1605. return 1ULL << (12 + 4 * szu);
  1606. }
  1607. static u32 nvme_cmb_size(struct nvme_dev *dev)
  1608. {
  1609. return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
  1610. }
  1611. static void nvme_map_cmb(struct nvme_dev *dev)
  1612. {
  1613. u64 size, offset;
  1614. resource_size_t bar_size;
  1615. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1616. int bar;
  1617. if (dev->cmb_size)
  1618. return;
  1619. if (NVME_CAP_CMBS(dev->ctrl.cap))
  1620. writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
  1621. dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
  1622. if (!dev->cmbsz)
  1623. return;
  1624. dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
  1625. size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
  1626. offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
  1627. bar = NVME_CMB_BIR(dev->cmbloc);
  1628. bar_size = pci_resource_len(pdev, bar);
  1629. if (offset > bar_size)
  1630. return;
  1631. /*
  1632. * Tell the controller about the host side address mapping the CMB,
  1633. * and enable CMB decoding for the NVMe 1.4+ scheme:
  1634. */
  1635. if (NVME_CAP_CMBS(dev->ctrl.cap)) {
  1636. hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
  1637. (pci_bus_address(pdev, bar) + offset),
  1638. dev->bar + NVME_REG_CMBMSC);
  1639. }
  1640. /*
  1641. * Controllers may support a CMB size larger than their BAR,
  1642. * for example, due to being behind a bridge. Reduce the CMB to
  1643. * the reported size of the BAR
  1644. */
  1645. if (size > bar_size - offset)
  1646. size = bar_size - offset;
  1647. if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
  1648. dev_warn(dev->ctrl.device,
  1649. "failed to register the CMB\n");
  1650. return;
  1651. }
  1652. dev->cmb_size = size;
  1653. dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
  1654. if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
  1655. (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
  1656. pci_p2pmem_publish(pdev, true);
  1657. nvme_update_attrs(dev);
  1658. }
  1659. static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
  1660. {
  1661. u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
  1662. u64 dma_addr = dev->host_mem_descs_dma;
  1663. struct nvme_command c = { };
  1664. int ret;
  1665. c.features.opcode = nvme_admin_set_features;
  1666. c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
  1667. c.features.dword11 = cpu_to_le32(bits);
  1668. c.features.dword12 = cpu_to_le32(host_mem_size);
  1669. c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
  1670. c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
  1671. c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
  1672. ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
  1673. if (ret) {
  1674. dev_warn(dev->ctrl.device,
  1675. "failed to set host mem (err %d, flags %#x).\n",
  1676. ret, bits);
  1677. } else
  1678. dev->hmb = bits & NVME_HOST_MEM_ENABLE;
  1679. return ret;
  1680. }
  1681. static void nvme_free_host_mem(struct nvme_dev *dev)
  1682. {
  1683. int i;
  1684. for (i = 0; i < dev->nr_host_mem_descs; i++) {
  1685. struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
  1686. size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
  1687. dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
  1688. le64_to_cpu(desc->addr),
  1689. DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
  1690. }
  1691. kfree(dev->host_mem_desc_bufs);
  1692. dev->host_mem_desc_bufs = NULL;
  1693. dma_free_coherent(dev->dev,
  1694. dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
  1695. dev->host_mem_descs, dev->host_mem_descs_dma);
  1696. dev->host_mem_descs = NULL;
  1697. dev->nr_host_mem_descs = 0;
  1698. }
  1699. static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
  1700. u32 chunk_size)
  1701. {
  1702. struct nvme_host_mem_buf_desc *descs;
  1703. u32 max_entries, len;
  1704. dma_addr_t descs_dma;
  1705. int i = 0;
  1706. void **bufs;
  1707. u64 size, tmp;
  1708. tmp = (preferred + chunk_size - 1);
  1709. do_div(tmp, chunk_size);
  1710. max_entries = tmp;
  1711. if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
  1712. max_entries = dev->ctrl.hmmaxd;
  1713. descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
  1714. &descs_dma, GFP_KERNEL);
  1715. if (!descs)
  1716. goto out;
  1717. bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
  1718. if (!bufs)
  1719. goto out_free_descs;
  1720. for (size = 0; size < preferred && i < max_entries; size += len) {
  1721. dma_addr_t dma_addr;
  1722. len = min_t(u64, chunk_size, preferred - size);
  1723. bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
  1724. DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
  1725. if (!bufs[i])
  1726. break;
  1727. descs[i].addr = cpu_to_le64(dma_addr);
  1728. descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
  1729. i++;
  1730. }
  1731. if (!size)
  1732. goto out_free_bufs;
  1733. dev->nr_host_mem_descs = i;
  1734. dev->host_mem_size = size;
  1735. dev->host_mem_descs = descs;
  1736. dev->host_mem_descs_dma = descs_dma;
  1737. dev->host_mem_desc_bufs = bufs;
  1738. return 0;
  1739. out_free_bufs:
  1740. while (--i >= 0) {
  1741. size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
  1742. dma_free_attrs(dev->dev, size, bufs[i],
  1743. le64_to_cpu(descs[i].addr),
  1744. DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
  1745. }
  1746. kfree(bufs);
  1747. out_free_descs:
  1748. dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
  1749. descs_dma);
  1750. out:
  1751. dev->host_mem_descs = NULL;
  1752. return -ENOMEM;
  1753. }
  1754. static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
  1755. {
  1756. u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
  1757. u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
  1758. u64 chunk_size;
  1759. /* start big and work our way down */
  1760. for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
  1761. if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
  1762. if (!min || dev->host_mem_size >= min)
  1763. return 0;
  1764. nvme_free_host_mem(dev);
  1765. }
  1766. }
  1767. return -ENOMEM;
  1768. }
  1769. static int nvme_setup_host_mem(struct nvme_dev *dev)
  1770. {
  1771. u64 max = (u64)max_host_mem_size_mb * SZ_1M;
  1772. u64 preferred = (u64)dev->ctrl.hmpre * 4096;
  1773. u64 min = (u64)dev->ctrl.hmmin * 4096;
  1774. u32 enable_bits = NVME_HOST_MEM_ENABLE;
  1775. int ret;
  1776. preferred = min(preferred, max);
  1777. if (min > max) {
  1778. dev_warn(dev->ctrl.device,
  1779. "min host memory (%lld MiB) above limit (%d MiB).\n",
  1780. min >> ilog2(SZ_1M), max_host_mem_size_mb);
  1781. nvme_free_host_mem(dev);
  1782. return 0;
  1783. }
  1784. /*
  1785. * If we already have a buffer allocated check if we can reuse it.
  1786. */
  1787. if (dev->host_mem_descs) {
  1788. if (dev->host_mem_size >= min)
  1789. enable_bits |= NVME_HOST_MEM_RETURN;
  1790. else
  1791. nvme_free_host_mem(dev);
  1792. }
  1793. if (!dev->host_mem_descs) {
  1794. if (nvme_alloc_host_mem(dev, min, preferred)) {
  1795. dev_warn(dev->ctrl.device,
  1796. "failed to allocate host memory buffer.\n");
  1797. return 0; /* controller must work without HMB */
  1798. }
  1799. dev_info(dev->ctrl.device,
  1800. "allocated %lld MiB host memory buffer.\n",
  1801. dev->host_mem_size >> ilog2(SZ_1M));
  1802. }
  1803. ret = nvme_set_host_mem(dev, enable_bits);
  1804. if (ret)
  1805. nvme_free_host_mem(dev);
  1806. return ret;
  1807. }
  1808. static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
  1809. char *buf)
  1810. {
  1811. struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
  1812. return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
  1813. ndev->cmbloc, ndev->cmbsz);
  1814. }
  1815. static DEVICE_ATTR_RO(cmb);
  1816. static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
  1817. char *buf)
  1818. {
  1819. struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
  1820. return sysfs_emit(buf, "%u\n", ndev->cmbloc);
  1821. }
  1822. static DEVICE_ATTR_RO(cmbloc);
  1823. static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
  1824. char *buf)
  1825. {
  1826. struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
  1827. return sysfs_emit(buf, "%u\n", ndev->cmbsz);
  1828. }
  1829. static DEVICE_ATTR_RO(cmbsz);
  1830. static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
  1831. char *buf)
  1832. {
  1833. struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
  1834. return sysfs_emit(buf, "%d\n", ndev->hmb);
  1835. }
  1836. static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
  1837. const char *buf, size_t count)
  1838. {
  1839. struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
  1840. bool new;
  1841. int ret;
  1842. if (strtobool(buf, &new) < 0)
  1843. return -EINVAL;
  1844. if (new == ndev->hmb)
  1845. return count;
  1846. if (new) {
  1847. ret = nvme_setup_host_mem(ndev);
  1848. } else {
  1849. ret = nvme_set_host_mem(ndev, 0);
  1850. if (!ret)
  1851. nvme_free_host_mem(ndev);
  1852. }
  1853. if (ret < 0)
  1854. return ret;
  1855. return count;
  1856. }
  1857. static DEVICE_ATTR_RW(hmb);
  1858. static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
  1859. struct attribute *a, int n)
  1860. {
  1861. struct nvme_ctrl *ctrl =
  1862. dev_get_drvdata(container_of(kobj, struct device, kobj));
  1863. struct nvme_dev *dev = to_nvme_dev(ctrl);
  1864. if (a == &dev_attr_cmb.attr ||
  1865. a == &dev_attr_cmbloc.attr ||
  1866. a == &dev_attr_cmbsz.attr) {
  1867. if (!dev->cmbsz)
  1868. return 0;
  1869. }
  1870. if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
  1871. return 0;
  1872. return a->mode;
  1873. }
  1874. static struct attribute *nvme_pci_attrs[] = {
  1875. &dev_attr_cmb.attr,
  1876. &dev_attr_cmbloc.attr,
  1877. &dev_attr_cmbsz.attr,
  1878. &dev_attr_hmb.attr,
  1879. NULL,
  1880. };
  1881. static const struct attribute_group nvme_pci_dev_attrs_group = {
  1882. .attrs = nvme_pci_attrs,
  1883. .is_visible = nvme_pci_attrs_are_visible,
  1884. };
  1885. static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
  1886. &nvme_dev_attrs_group,
  1887. &nvme_pci_dev_attrs_group,
  1888. NULL,
  1889. };
  1890. static void nvme_update_attrs(struct nvme_dev *dev)
  1891. {
  1892. sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
  1893. }
  1894. /*
  1895. * nirqs is the number of interrupts available for write and read
  1896. * queues. The core already reserved an interrupt for the admin queue.
  1897. */
  1898. static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
  1899. {
  1900. struct nvme_dev *dev = affd->priv;
  1901. unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
  1902. /*
  1903. * If there is no interrupt available for queues, ensure that
  1904. * the default queue is set to 1. The affinity set size is
  1905. * also set to one, but the irq core ignores it for this case.
  1906. *
  1907. * If only one interrupt is available or 'write_queue' == 0, combine
  1908. * write and read queues.
  1909. *
  1910. * If 'write_queues' > 0, ensure it leaves room for at least one read
  1911. * queue.
  1912. */
  1913. if (!nrirqs) {
  1914. nrirqs = 1;
  1915. nr_read_queues = 0;
  1916. } else if (nrirqs == 1 || !nr_write_queues) {
  1917. nr_read_queues = 0;
  1918. } else if (nr_write_queues >= nrirqs) {
  1919. nr_read_queues = 1;
  1920. } else {
  1921. nr_read_queues = nrirqs - nr_write_queues;
  1922. }
  1923. dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
  1924. affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
  1925. dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
  1926. affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
  1927. affd->nr_sets = nr_read_queues ? 2 : 1;
  1928. }
  1929. static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
  1930. {
  1931. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1932. struct irq_affinity affd = {
  1933. .pre_vectors = 1,
  1934. .calc_sets = nvme_calc_irq_sets,
  1935. .priv = dev,
  1936. };
  1937. unsigned int irq_queues, poll_queues;
  1938. /*
  1939. * Poll queues don't need interrupts, but we need at least one I/O queue
  1940. * left over for non-polled I/O.
  1941. */
  1942. poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
  1943. dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
  1944. /*
  1945. * Initialize for the single interrupt case, will be updated in
  1946. * nvme_calc_irq_sets().
  1947. */
  1948. dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
  1949. dev->io_queues[HCTX_TYPE_READ] = 0;
  1950. /*
  1951. * We need interrupts for the admin queue and each non-polled I/O queue,
  1952. * but some Apple controllers require all queues to use the first
  1953. * vector.
  1954. */
  1955. irq_queues = 1;
  1956. if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
  1957. irq_queues += (nr_io_queues - poll_queues);
  1958. return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
  1959. PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
  1960. }
  1961. static void nvme_disable_io_queues(struct nvme_dev *dev)
  1962. {
  1963. if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
  1964. __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
  1965. }
  1966. static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
  1967. {
  1968. /*
  1969. * If tags are shared with admin queue (Apple bug), then
  1970. * make sure we only use one IO queue.
  1971. */
  1972. if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
  1973. return 1;
  1974. return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
  1975. }
  1976. static int nvme_setup_io_queues(struct nvme_dev *dev)
  1977. {
  1978. struct nvme_queue *adminq = &dev->queues[0];
  1979. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1980. unsigned int nr_io_queues;
  1981. unsigned long size;
  1982. int result;
  1983. /*
  1984. * Sample the module parameters once at reset time so that we have
  1985. * stable values to work with.
  1986. */
  1987. dev->nr_write_queues = write_queues;
  1988. dev->nr_poll_queues = poll_queues;
  1989. nr_io_queues = dev->nr_allocated_queues - 1;
  1990. result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
  1991. if (result < 0)
  1992. return result;
  1993. if (nr_io_queues == 0)
  1994. return 0;
  1995. /*
  1996. * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
  1997. * from set to unset. If there is a window to it is truely freed,
  1998. * pci_free_irq_vectors() jumping into this window will crash.
  1999. * And take lock to avoid racing with pci_free_irq_vectors() in
  2000. * nvme_dev_disable() path.
  2001. */
  2002. result = nvme_setup_io_queues_trylock(dev);
  2003. if (result)
  2004. return result;
  2005. if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
  2006. pci_free_irq(pdev, 0, adminq);
  2007. if (dev->cmb_use_sqes) {
  2008. result = nvme_cmb_qdepth(dev, nr_io_queues,
  2009. sizeof(struct nvme_command));
  2010. if (result > 0)
  2011. dev->q_depth = result;
  2012. else
  2013. dev->cmb_use_sqes = false;
  2014. }
  2015. do {
  2016. size = db_bar_size(dev, nr_io_queues);
  2017. result = nvme_remap_bar(dev, size);
  2018. if (!result)
  2019. break;
  2020. if (!--nr_io_queues) {
  2021. result = -ENOMEM;
  2022. goto out_unlock;
  2023. }
  2024. } while (1);
  2025. adminq->q_db = dev->dbs;
  2026. retry:
  2027. /* Deregister the admin queue's interrupt */
  2028. if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
  2029. pci_free_irq(pdev, 0, adminq);
  2030. /*
  2031. * If we enable msix early due to not intx, disable it again before
  2032. * setting up the full range we need.
  2033. */
  2034. pci_free_irq_vectors(pdev);
  2035. result = nvme_setup_irqs(dev, nr_io_queues);
  2036. if (result <= 0) {
  2037. result = -EIO;
  2038. goto out_unlock;
  2039. }
  2040. dev->num_vecs = result;
  2041. result = max(result - 1, 1);
  2042. dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
  2043. /*
  2044. * Should investigate if there's a performance win from allocating
  2045. * more queues than interrupt vectors; it might allow the submission
  2046. * path to scale better, even if the receive path is limited by the
  2047. * number of interrupts.
  2048. */
  2049. result = queue_request_irq(adminq);
  2050. if (result)
  2051. goto out_unlock;
  2052. set_bit(NVMEQ_ENABLED, &adminq->flags);
  2053. mutex_unlock(&dev->shutdown_lock);
  2054. result = nvme_create_io_queues(dev);
  2055. if (result || dev->online_queues < 2)
  2056. return result;
  2057. if (dev->online_queues - 1 < dev->max_qid) {
  2058. nr_io_queues = dev->online_queues - 1;
  2059. nvme_disable_io_queues(dev);
  2060. result = nvme_setup_io_queues_trylock(dev);
  2061. if (result)
  2062. return result;
  2063. nvme_suspend_io_queues(dev);
  2064. goto retry;
  2065. }
  2066. dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
  2067. dev->io_queues[HCTX_TYPE_DEFAULT],
  2068. dev->io_queues[HCTX_TYPE_READ],
  2069. dev->io_queues[HCTX_TYPE_POLL]);
  2070. return 0;
  2071. out_unlock:
  2072. mutex_unlock(&dev->shutdown_lock);
  2073. return result;
  2074. }
  2075. static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
  2076. blk_status_t error)
  2077. {
  2078. struct nvme_queue *nvmeq = req->end_io_data;
  2079. blk_mq_free_request(req);
  2080. complete(&nvmeq->delete_done);
  2081. return RQ_END_IO_NONE;
  2082. }
  2083. static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
  2084. blk_status_t error)
  2085. {
  2086. struct nvme_queue *nvmeq = req->end_io_data;
  2087. if (error)
  2088. set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
  2089. return nvme_del_queue_end(req, error);
  2090. }
  2091. static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
  2092. {
  2093. struct request_queue *q = nvmeq->dev->ctrl.admin_q;
  2094. struct request *req;
  2095. struct nvme_command cmd = { };
  2096. cmd.delete_queue.opcode = opcode;
  2097. cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
  2098. req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
  2099. if (IS_ERR(req))
  2100. return PTR_ERR(req);
  2101. nvme_init_request(req, &cmd);
  2102. if (opcode == nvme_admin_delete_cq)
  2103. req->end_io = nvme_del_cq_end;
  2104. else
  2105. req->end_io = nvme_del_queue_end;
  2106. req->end_io_data = nvmeq;
  2107. init_completion(&nvmeq->delete_done);
  2108. blk_execute_rq_nowait(req, false);
  2109. return 0;
  2110. }
  2111. static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
  2112. {
  2113. int nr_queues = dev->online_queues - 1, sent = 0;
  2114. unsigned long timeout;
  2115. retry:
  2116. timeout = NVME_ADMIN_TIMEOUT;
  2117. while (nr_queues > 0) {
  2118. if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
  2119. break;
  2120. nr_queues--;
  2121. sent++;
  2122. }
  2123. while (sent) {
  2124. struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
  2125. timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
  2126. timeout);
  2127. if (timeout == 0)
  2128. return false;
  2129. sent--;
  2130. if (nr_queues)
  2131. goto retry;
  2132. }
  2133. return true;
  2134. }
  2135. static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
  2136. {
  2137. struct blk_mq_tag_set * set = &dev->tagset;
  2138. int ret;
  2139. set->ops = &nvme_mq_ops;
  2140. set->nr_hw_queues = dev->online_queues - 1;
  2141. set->nr_maps = 1;
  2142. if (dev->io_queues[HCTX_TYPE_READ])
  2143. set->nr_maps = 2;
  2144. if (dev->io_queues[HCTX_TYPE_POLL])
  2145. set->nr_maps = 3;
  2146. set->timeout = NVME_IO_TIMEOUT;
  2147. set->numa_node = dev->ctrl.numa_node;
  2148. set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
  2149. set->cmd_size = sizeof(struct nvme_iod);
  2150. set->flags = BLK_MQ_F_SHOULD_MERGE;
  2151. set->driver_data = dev;
  2152. /*
  2153. * Some Apple controllers requires tags to be unique
  2154. * across admin and IO queue, so reserve the first 32
  2155. * tags of the IO queue.
  2156. */
  2157. if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
  2158. set->reserved_tags = NVME_AQ_DEPTH;
  2159. ret = blk_mq_alloc_tag_set(set);
  2160. if (ret) {
  2161. dev_warn(dev->ctrl.device,
  2162. "IO queues tagset allocation failed %d\n", ret);
  2163. return;
  2164. }
  2165. dev->ctrl.tagset = set;
  2166. }
  2167. static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
  2168. {
  2169. blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
  2170. /* free previously allocated queues that are no longer usable */
  2171. nvme_free_queues(dev, dev->online_queues);
  2172. }
  2173. static int nvme_pci_enable(struct nvme_dev *dev)
  2174. {
  2175. int result = -ENOMEM;
  2176. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2177. int dma_address_bits = 64;
  2178. if (pci_enable_device_mem(pdev))
  2179. return result;
  2180. pci_set_master(pdev);
  2181. if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
  2182. dma_address_bits = 48;
  2183. if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
  2184. goto disable;
  2185. if (readl(dev->bar + NVME_REG_CSTS) == -1) {
  2186. result = -ENODEV;
  2187. goto disable;
  2188. }
  2189. /*
  2190. * Some devices and/or platforms don't advertise or work with INTx
  2191. * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
  2192. * adjust this later.
  2193. */
  2194. result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
  2195. if (result < 0)
  2196. return result;
  2197. dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
  2198. dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
  2199. io_queue_depth);
  2200. dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
  2201. dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
  2202. dev->dbs = dev->bar + 4096;
  2203. /*
  2204. * Some Apple controllers require a non-standard SQE size.
  2205. * Interestingly they also seem to ignore the CC:IOSQES register
  2206. * so we don't bother updating it here.
  2207. */
  2208. if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
  2209. dev->io_sqes = 7;
  2210. else
  2211. dev->io_sqes = NVME_NVM_IOSQES;
  2212. /*
  2213. * Temporary fix for the Apple controller found in the MacBook8,1 and
  2214. * some MacBook7,1 to avoid controller resets and data loss.
  2215. */
  2216. if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
  2217. dev->q_depth = 2;
  2218. dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
  2219. "set queue depth=%u to work around controller resets\n",
  2220. dev->q_depth);
  2221. } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
  2222. (pdev->device == 0xa821 || pdev->device == 0xa822) &&
  2223. NVME_CAP_MQES(dev->ctrl.cap) == 0) {
  2224. dev->q_depth = 64;
  2225. dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
  2226. "set queue depth=%u\n", dev->q_depth);
  2227. }
  2228. /*
  2229. * Controllers with the shared tags quirk need the IO queue to be
  2230. * big enough so that we get 32 tags for the admin queue
  2231. */
  2232. if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
  2233. (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
  2234. dev->q_depth = NVME_AQ_DEPTH + 2;
  2235. dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
  2236. dev->q_depth);
  2237. }
  2238. nvme_map_cmb(dev);
  2239. pci_enable_pcie_error_reporting(pdev);
  2240. pci_save_state(pdev);
  2241. return 0;
  2242. disable:
  2243. pci_disable_device(pdev);
  2244. return result;
  2245. }
  2246. static void nvme_dev_unmap(struct nvme_dev *dev)
  2247. {
  2248. if (dev->bar)
  2249. iounmap(dev->bar);
  2250. pci_release_mem_regions(to_pci_dev(dev->dev));
  2251. }
  2252. static void nvme_pci_disable(struct nvme_dev *dev)
  2253. {
  2254. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2255. pci_free_irq_vectors(pdev);
  2256. if (pci_is_enabled(pdev)) {
  2257. pci_disable_pcie_error_reporting(pdev);
  2258. pci_disable_device(pdev);
  2259. }
  2260. }
  2261. static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
  2262. {
  2263. bool dead = true, freeze = false;
  2264. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2265. mutex_lock(&dev->shutdown_lock);
  2266. if (pci_is_enabled(pdev)) {
  2267. u32 csts;
  2268. if (pci_device_is_present(pdev))
  2269. csts = readl(dev->bar + NVME_REG_CSTS);
  2270. else
  2271. csts = ~0;
  2272. if (dev->ctrl.state == NVME_CTRL_LIVE ||
  2273. dev->ctrl.state == NVME_CTRL_RESETTING) {
  2274. freeze = true;
  2275. nvme_start_freeze(&dev->ctrl);
  2276. }
  2277. dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
  2278. pdev->error_state != pci_channel_io_normal);
  2279. }
  2280. /*
  2281. * Give the controller a chance to complete all entered requests if
  2282. * doing a safe shutdown.
  2283. */
  2284. if (!dead && shutdown && freeze)
  2285. nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
  2286. nvme_stop_queues(&dev->ctrl);
  2287. if (!dead && dev->ctrl.queue_count > 0) {
  2288. nvme_disable_io_queues(dev);
  2289. nvme_disable_admin_queue(dev, shutdown);
  2290. }
  2291. nvme_suspend_io_queues(dev);
  2292. nvme_suspend_queue(&dev->queues[0]);
  2293. nvme_pci_disable(dev);
  2294. nvme_reap_pending_cqes(dev);
  2295. nvme_cancel_tagset(&dev->ctrl);
  2296. nvme_cancel_admin_tagset(&dev->ctrl);
  2297. /*
  2298. * The driver will not be starting up queues again if shutting down so
  2299. * must flush all entered requests to their failed completion to avoid
  2300. * deadlocking blk-mq hot-cpu notifier.
  2301. */
  2302. if (shutdown) {
  2303. nvme_start_queues(&dev->ctrl);
  2304. if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
  2305. nvme_start_admin_queue(&dev->ctrl);
  2306. }
  2307. mutex_unlock(&dev->shutdown_lock);
  2308. }
  2309. static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
  2310. {
  2311. if (!nvme_wait_reset(&dev->ctrl))
  2312. return -EBUSY;
  2313. nvme_dev_disable(dev, shutdown);
  2314. return 0;
  2315. }
  2316. static int nvme_setup_prp_pools(struct nvme_dev *dev)
  2317. {
  2318. dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
  2319. NVME_CTRL_PAGE_SIZE,
  2320. NVME_CTRL_PAGE_SIZE, 0);
  2321. if (!dev->prp_page_pool)
  2322. return -ENOMEM;
  2323. /* Optimisation for I/Os between 4k and 128k */
  2324. dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
  2325. 256, 256, 0);
  2326. if (!dev->prp_small_pool) {
  2327. dma_pool_destroy(dev->prp_page_pool);
  2328. return -ENOMEM;
  2329. }
  2330. return 0;
  2331. }
  2332. static void nvme_release_prp_pools(struct nvme_dev *dev)
  2333. {
  2334. dma_pool_destroy(dev->prp_page_pool);
  2335. dma_pool_destroy(dev->prp_small_pool);
  2336. }
  2337. static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
  2338. {
  2339. size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
  2340. size_t alloc_size = sizeof(__le64 *) * npages +
  2341. sizeof(struct scatterlist) * NVME_MAX_SEGS;
  2342. WARN_ON_ONCE(alloc_size > PAGE_SIZE);
  2343. dev->iod_mempool = mempool_create_node(1,
  2344. mempool_kmalloc, mempool_kfree,
  2345. (void *)alloc_size, GFP_KERNEL,
  2346. dev_to_node(dev->dev));
  2347. if (!dev->iod_mempool)
  2348. return -ENOMEM;
  2349. return 0;
  2350. }
  2351. static void nvme_free_tagset(struct nvme_dev *dev)
  2352. {
  2353. if (dev->tagset.tags)
  2354. blk_mq_free_tag_set(&dev->tagset);
  2355. dev->ctrl.tagset = NULL;
  2356. }
  2357. /* pairs with nvme_pci_alloc_dev */
  2358. static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
  2359. {
  2360. struct nvme_dev *dev = to_nvme_dev(ctrl);
  2361. nvme_dbbuf_dma_free(dev);
  2362. nvme_free_tagset(dev);
  2363. if (dev->ctrl.admin_q)
  2364. blk_put_queue(dev->ctrl.admin_q);
  2365. free_opal_dev(dev->ctrl.opal_dev);
  2366. mempool_destroy(dev->iod_mempool);
  2367. put_device(dev->dev);
  2368. kfree(dev->queues);
  2369. kfree(dev);
  2370. }
  2371. static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
  2372. {
  2373. /*
  2374. * Set state to deleting now to avoid blocking nvme_wait_reset(), which
  2375. * may be holding this pci_dev's device lock.
  2376. */
  2377. nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
  2378. nvme_get_ctrl(&dev->ctrl);
  2379. nvme_dev_disable(dev, false);
  2380. nvme_kill_queues(&dev->ctrl);
  2381. if (!queue_work(nvme_wq, &dev->remove_work))
  2382. nvme_put_ctrl(&dev->ctrl);
  2383. }
  2384. static void nvme_reset_work(struct work_struct *work)
  2385. {
  2386. struct nvme_dev *dev =
  2387. container_of(work, struct nvme_dev, ctrl.reset_work);
  2388. bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
  2389. int result;
  2390. if (dev->ctrl.state != NVME_CTRL_RESETTING) {
  2391. dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
  2392. dev->ctrl.state);
  2393. result = -ENODEV;
  2394. goto out;
  2395. }
  2396. /*
  2397. * If we're called to reset a live controller first shut it down before
  2398. * moving on.
  2399. */
  2400. if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
  2401. nvme_dev_disable(dev, false);
  2402. nvme_sync_queues(&dev->ctrl);
  2403. mutex_lock(&dev->shutdown_lock);
  2404. result = nvme_pci_enable(dev);
  2405. if (result)
  2406. goto out_unlock;
  2407. result = nvme_pci_configure_admin_queue(dev);
  2408. if (result)
  2409. goto out_unlock;
  2410. if (!dev->ctrl.admin_q) {
  2411. result = nvme_pci_alloc_admin_tag_set(dev);
  2412. if (result)
  2413. goto out_unlock;
  2414. } else {
  2415. nvme_start_admin_queue(&dev->ctrl);
  2416. }
  2417. dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
  2418. /*
  2419. * Limit the max command size to prevent iod->sg allocations going
  2420. * over a single page.
  2421. */
  2422. dev->ctrl.max_hw_sectors = min_t(u32,
  2423. NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
  2424. dev->ctrl.max_segments = NVME_MAX_SEGS;
  2425. /*
  2426. * Don't limit the IOMMU merged segment size.
  2427. */
  2428. dma_set_max_seg_size(dev->dev, 0xffffffff);
  2429. mutex_unlock(&dev->shutdown_lock);
  2430. /*
  2431. * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
  2432. * initializing procedure here.
  2433. */
  2434. if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
  2435. dev_warn(dev->ctrl.device,
  2436. "failed to mark controller CONNECTING\n");
  2437. result = -EBUSY;
  2438. goto out;
  2439. }
  2440. /*
  2441. * We do not support an SGL for metadata (yet), so we are limited to a
  2442. * single integrity segment for the separate metadata pointer.
  2443. */
  2444. dev->ctrl.max_integrity_segments = 1;
  2445. result = nvme_init_ctrl_finish(&dev->ctrl);
  2446. if (result)
  2447. goto out;
  2448. if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
  2449. if (!dev->ctrl.opal_dev)
  2450. dev->ctrl.opal_dev =
  2451. init_opal_dev(&dev->ctrl, &nvme_sec_submit);
  2452. else if (was_suspend)
  2453. opal_unlock_from_suspend(dev->ctrl.opal_dev);
  2454. } else {
  2455. free_opal_dev(dev->ctrl.opal_dev);
  2456. dev->ctrl.opal_dev = NULL;
  2457. }
  2458. if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
  2459. result = nvme_dbbuf_dma_alloc(dev);
  2460. if (result)
  2461. dev_warn(dev->dev,
  2462. "unable to allocate dma for dbbuf\n");
  2463. }
  2464. if (dev->ctrl.hmpre) {
  2465. result = nvme_setup_host_mem(dev);
  2466. if (result < 0)
  2467. goto out;
  2468. }
  2469. result = nvme_setup_io_queues(dev);
  2470. if (result)
  2471. goto out;
  2472. /*
  2473. * Keep the controller around but remove all namespaces if we don't have
  2474. * any working I/O queue.
  2475. */
  2476. if (dev->online_queues < 2) {
  2477. dev_warn(dev->ctrl.device, "IO queues not created\n");
  2478. nvme_kill_queues(&dev->ctrl);
  2479. nvme_remove_namespaces(&dev->ctrl);
  2480. nvme_free_tagset(dev);
  2481. } else {
  2482. nvme_start_queues(&dev->ctrl);
  2483. nvme_wait_freeze(&dev->ctrl);
  2484. if (!dev->ctrl.tagset)
  2485. nvme_pci_alloc_tag_set(dev);
  2486. else
  2487. nvme_pci_update_nr_queues(dev);
  2488. nvme_dbbuf_set(dev);
  2489. nvme_unfreeze(&dev->ctrl);
  2490. }
  2491. /*
  2492. * If only admin queue live, keep it to do further investigation or
  2493. * recovery.
  2494. */
  2495. if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
  2496. dev_warn(dev->ctrl.device,
  2497. "failed to mark controller live state\n");
  2498. result = -ENODEV;
  2499. goto out;
  2500. }
  2501. nvme_start_ctrl(&dev->ctrl);
  2502. return;
  2503. out_unlock:
  2504. mutex_unlock(&dev->shutdown_lock);
  2505. out:
  2506. if (result)
  2507. dev_warn(dev->ctrl.device,
  2508. "Removing after probe failure status: %d\n", result);
  2509. nvme_remove_dead_ctrl(dev);
  2510. }
  2511. static void nvme_remove_dead_ctrl_work(struct work_struct *work)
  2512. {
  2513. struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
  2514. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2515. if (pci_get_drvdata(pdev))
  2516. device_release_driver(&pdev->dev);
  2517. nvme_put_ctrl(&dev->ctrl);
  2518. }
  2519. static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
  2520. {
  2521. *val = readl(to_nvme_dev(ctrl)->bar + off);
  2522. return 0;
  2523. }
  2524. static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
  2525. {
  2526. writel(val, to_nvme_dev(ctrl)->bar + off);
  2527. return 0;
  2528. }
  2529. static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
  2530. {
  2531. *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
  2532. return 0;
  2533. }
  2534. static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
  2535. {
  2536. struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
  2537. return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
  2538. }
  2539. static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
  2540. {
  2541. struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
  2542. struct nvme_subsystem *subsys = ctrl->subsys;
  2543. dev_err(ctrl->device,
  2544. "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
  2545. pdev->vendor, pdev->device,
  2546. nvme_strlen(subsys->model, sizeof(subsys->model)),
  2547. subsys->model, nvme_strlen(subsys->firmware_rev,
  2548. sizeof(subsys->firmware_rev)),
  2549. subsys->firmware_rev);
  2550. }
  2551. static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
  2552. {
  2553. struct nvme_dev *dev = to_nvme_dev(ctrl);
  2554. return dma_pci_p2pdma_supported(dev->dev);
  2555. }
  2556. static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
  2557. .name = "pcie",
  2558. .module = THIS_MODULE,
  2559. .flags = NVME_F_METADATA_SUPPORTED,
  2560. .dev_attr_groups = nvme_pci_dev_attr_groups,
  2561. .reg_read32 = nvme_pci_reg_read32,
  2562. .reg_write32 = nvme_pci_reg_write32,
  2563. .reg_read64 = nvme_pci_reg_read64,
  2564. .free_ctrl = nvme_pci_free_ctrl,
  2565. .submit_async_event = nvme_pci_submit_async_event,
  2566. .get_address = nvme_pci_get_address,
  2567. .print_device_info = nvme_pci_print_device_info,
  2568. .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
  2569. };
  2570. static int nvme_dev_map(struct nvme_dev *dev)
  2571. {
  2572. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2573. if (pci_request_mem_regions(pdev, "nvme"))
  2574. return -ENODEV;
  2575. if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
  2576. goto release;
  2577. return 0;
  2578. release:
  2579. pci_release_mem_regions(pdev);
  2580. return -ENODEV;
  2581. }
  2582. static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
  2583. {
  2584. if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
  2585. /*
  2586. * Several Samsung devices seem to drop off the PCIe bus
  2587. * randomly when APST is on and uses the deepest sleep state.
  2588. * This has been observed on a Samsung "SM951 NVMe SAMSUNG
  2589. * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
  2590. * 950 PRO 256GB", but it seems to be restricted to two Dell
  2591. * laptops.
  2592. */
  2593. if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
  2594. (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
  2595. dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
  2596. return NVME_QUIRK_NO_DEEPEST_PS;
  2597. } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
  2598. /*
  2599. * Samsung SSD 960 EVO drops off the PCIe bus after system
  2600. * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
  2601. * within few minutes after bootup on a Coffee Lake board -
  2602. * ASUS PRIME Z370-A
  2603. */
  2604. if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
  2605. (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
  2606. dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
  2607. return NVME_QUIRK_NO_APST;
  2608. } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
  2609. pdev->device == 0xa808 || pdev->device == 0xa809)) ||
  2610. (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
  2611. /*
  2612. * Forcing to use host managed nvme power settings for
  2613. * lowest idle power with quick resume latency on
  2614. * Samsung and Toshiba SSDs based on suspend behavior
  2615. * on Coffee Lake board for LENOVO C640
  2616. */
  2617. if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
  2618. dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
  2619. return NVME_QUIRK_SIMPLE_SUSPEND;
  2620. } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
  2621. pdev->device == 0x500f)) {
  2622. /*
  2623. * Exclude some Kingston NV1 and A2000 devices from
  2624. * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
  2625. * lot fo energy with s2idle sleep on some TUXEDO platforms.
  2626. */
  2627. if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
  2628. dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
  2629. dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
  2630. dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
  2631. return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
  2632. }
  2633. return 0;
  2634. }
  2635. static void nvme_async_probe(void *data, async_cookie_t cookie)
  2636. {
  2637. struct nvme_dev *dev = data;
  2638. flush_work(&dev->ctrl.reset_work);
  2639. flush_work(&dev->ctrl.scan_work);
  2640. nvme_put_ctrl(&dev->ctrl);
  2641. }
  2642. static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
  2643. const struct pci_device_id *id)
  2644. {
  2645. unsigned long quirks = id->driver_data;
  2646. int node = dev_to_node(&pdev->dev);
  2647. struct nvme_dev *dev;
  2648. int ret = -ENOMEM;
  2649. dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
  2650. if (!dev)
  2651. return ERR_PTR(-ENOMEM);
  2652. INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
  2653. INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
  2654. mutex_init(&dev->shutdown_lock);
  2655. dev->nr_write_queues = write_queues;
  2656. dev->nr_poll_queues = poll_queues;
  2657. dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
  2658. dev->queues = kcalloc_node(dev->nr_allocated_queues,
  2659. sizeof(struct nvme_queue), GFP_KERNEL, node);
  2660. if (!dev->queues)
  2661. goto out_free_dev;
  2662. dev->dev = get_device(&pdev->dev);
  2663. quirks |= check_vendor_combination_bug(pdev);
  2664. if (!noacpi &&
  2665. !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
  2666. acpi_storage_d3(&pdev->dev)) {
  2667. /*
  2668. * Some systems use a bios work around to ask for D3 on
  2669. * platforms that support kernel managed suspend.
  2670. */
  2671. dev_info(&pdev->dev,
  2672. "platform quirk: setting simple suspend\n");
  2673. quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
  2674. }
  2675. ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
  2676. quirks);
  2677. if (ret)
  2678. goto out_put_device;
  2679. return dev;
  2680. out_put_device:
  2681. put_device(dev->dev);
  2682. kfree(dev->queues);
  2683. out_free_dev:
  2684. kfree(dev);
  2685. return ERR_PTR(ret);
  2686. }
  2687. static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  2688. {
  2689. struct nvme_dev *dev;
  2690. int result = -ENOMEM;
  2691. dev = nvme_pci_alloc_dev(pdev, id);
  2692. if (IS_ERR(dev))
  2693. return PTR_ERR(dev);
  2694. result = nvme_dev_map(dev);
  2695. if (result)
  2696. goto out_uninit_ctrl;
  2697. result = nvme_setup_prp_pools(dev);
  2698. if (result)
  2699. goto out_dev_unmap;
  2700. result = nvme_pci_alloc_iod_mempool(dev);
  2701. if (result)
  2702. goto out_release_prp_pools;
  2703. dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
  2704. pci_set_drvdata(pdev, dev);
  2705. nvme_reset_ctrl(&dev->ctrl);
  2706. async_schedule(nvme_async_probe, dev);
  2707. return 0;
  2708. out_release_prp_pools:
  2709. nvme_release_prp_pools(dev);
  2710. out_dev_unmap:
  2711. nvme_dev_unmap(dev);
  2712. out_uninit_ctrl:
  2713. nvme_uninit_ctrl(&dev->ctrl);
  2714. return result;
  2715. }
  2716. static void nvme_reset_prepare(struct pci_dev *pdev)
  2717. {
  2718. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2719. /*
  2720. * We don't need to check the return value from waiting for the reset
  2721. * state as pci_dev device lock is held, making it impossible to race
  2722. * with ->remove().
  2723. */
  2724. nvme_disable_prepare_reset(dev, false);
  2725. nvme_sync_queues(&dev->ctrl);
  2726. }
  2727. static void nvme_reset_done(struct pci_dev *pdev)
  2728. {
  2729. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2730. if (!nvme_try_sched_reset(&dev->ctrl))
  2731. flush_work(&dev->ctrl.reset_work);
  2732. }
  2733. static void nvme_shutdown(struct pci_dev *pdev)
  2734. {
  2735. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2736. nvme_disable_prepare_reset(dev, true);
  2737. }
  2738. /*
  2739. * The driver's remove may be called on a device in a partially initialized
  2740. * state. This function must not have any dependencies on the device state in
  2741. * order to proceed.
  2742. */
  2743. static void nvme_remove(struct pci_dev *pdev)
  2744. {
  2745. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2746. nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
  2747. pci_set_drvdata(pdev, NULL);
  2748. if (!pci_device_is_present(pdev)) {
  2749. nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
  2750. nvme_dev_disable(dev, true);
  2751. }
  2752. flush_work(&dev->ctrl.reset_work);
  2753. nvme_stop_ctrl(&dev->ctrl);
  2754. nvme_remove_namespaces(&dev->ctrl);
  2755. nvme_dev_disable(dev, true);
  2756. nvme_free_host_mem(dev);
  2757. nvme_dev_remove_admin(dev);
  2758. nvme_free_queues(dev, 0);
  2759. nvme_release_prp_pools(dev);
  2760. nvme_dev_unmap(dev);
  2761. nvme_uninit_ctrl(&dev->ctrl);
  2762. }
  2763. #ifdef CONFIG_PM_SLEEP
  2764. static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
  2765. {
  2766. return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
  2767. }
  2768. static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
  2769. {
  2770. return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
  2771. }
  2772. static int nvme_resume(struct device *dev)
  2773. {
  2774. struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
  2775. struct nvme_ctrl *ctrl = &ndev->ctrl;
  2776. if (ndev->last_ps == U32_MAX ||
  2777. nvme_set_power_state(ctrl, ndev->last_ps) != 0)
  2778. goto reset;
  2779. if (ctrl->hmpre && nvme_setup_host_mem(ndev))
  2780. goto reset;
  2781. return 0;
  2782. reset:
  2783. return nvme_try_sched_reset(ctrl);
  2784. }
  2785. static int nvme_suspend(struct device *dev)
  2786. {
  2787. struct pci_dev *pdev = to_pci_dev(dev);
  2788. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2789. struct nvme_ctrl *ctrl = &ndev->ctrl;
  2790. int ret = -EBUSY;
  2791. ndev->last_ps = U32_MAX;
  2792. /*
  2793. * The platform does not remove power for a kernel managed suspend so
  2794. * use host managed nvme power settings for lowest idle power if
  2795. * possible. This should have quicker resume latency than a full device
  2796. * shutdown. But if the firmware is involved after the suspend or the
  2797. * device does not support any non-default power states, shut down the
  2798. * device fully.
  2799. *
  2800. * If ASPM is not enabled for the device, shut down the device and allow
  2801. * the PCI bus layer to put it into D3 in order to take the PCIe link
  2802. * down, so as to allow the platform to achieve its minimum low-power
  2803. * state (which may not be possible if the link is up).
  2804. */
  2805. if (pm_suspend_via_firmware() || !ctrl->npss ||
  2806. !pcie_aspm_enabled(pdev) ||
  2807. (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
  2808. return nvme_disable_prepare_reset(ndev, true);
  2809. nvme_start_freeze(ctrl);
  2810. nvme_wait_freeze(ctrl);
  2811. nvme_sync_queues(ctrl);
  2812. if (ctrl->state != NVME_CTRL_LIVE)
  2813. goto unfreeze;
  2814. /*
  2815. * Host memory access may not be successful in a system suspend state,
  2816. * but the specification allows the controller to access memory in a
  2817. * non-operational power state.
  2818. */
  2819. if (ndev->hmb) {
  2820. ret = nvme_set_host_mem(ndev, 0);
  2821. if (ret < 0)
  2822. goto unfreeze;
  2823. }
  2824. ret = nvme_get_power_state(ctrl, &ndev->last_ps);
  2825. if (ret < 0)
  2826. goto unfreeze;
  2827. /*
  2828. * A saved state prevents pci pm from generically controlling the
  2829. * device's power. If we're using protocol specific settings, we don't
  2830. * want pci interfering.
  2831. */
  2832. pci_save_state(pdev);
  2833. ret = nvme_set_power_state(ctrl, ctrl->npss);
  2834. if (ret < 0)
  2835. goto unfreeze;
  2836. if (ret) {
  2837. /* discard the saved state */
  2838. pci_load_saved_state(pdev, NULL);
  2839. /*
  2840. * Clearing npss forces a controller reset on resume. The
  2841. * correct value will be rediscovered then.
  2842. */
  2843. ret = nvme_disable_prepare_reset(ndev, true);
  2844. ctrl->npss = 0;
  2845. }
  2846. unfreeze:
  2847. nvme_unfreeze(ctrl);
  2848. return ret;
  2849. }
  2850. static int nvme_simple_suspend(struct device *dev)
  2851. {
  2852. struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
  2853. return nvme_disable_prepare_reset(ndev, true);
  2854. }
  2855. static int nvme_simple_resume(struct device *dev)
  2856. {
  2857. struct pci_dev *pdev = to_pci_dev(dev);
  2858. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2859. return nvme_try_sched_reset(&ndev->ctrl);
  2860. }
  2861. static const struct dev_pm_ops nvme_dev_pm_ops = {
  2862. .suspend = nvme_suspend,
  2863. .resume = nvme_resume,
  2864. .freeze = nvme_simple_suspend,
  2865. .thaw = nvme_simple_resume,
  2866. .poweroff = nvme_simple_suspend,
  2867. .restore = nvme_simple_resume,
  2868. };
  2869. #endif /* CONFIG_PM_SLEEP */
  2870. static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
  2871. pci_channel_state_t state)
  2872. {
  2873. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2874. /*
  2875. * A frozen channel requires a reset. When detected, this method will
  2876. * shutdown the controller to quiesce. The controller will be restarted
  2877. * after the slot reset through driver's slot_reset callback.
  2878. */
  2879. switch (state) {
  2880. case pci_channel_io_normal:
  2881. return PCI_ERS_RESULT_CAN_RECOVER;
  2882. case pci_channel_io_frozen:
  2883. dev_warn(dev->ctrl.device,
  2884. "frozen state error detected, reset controller\n");
  2885. nvme_dev_disable(dev, false);
  2886. return PCI_ERS_RESULT_NEED_RESET;
  2887. case pci_channel_io_perm_failure:
  2888. dev_warn(dev->ctrl.device,
  2889. "failure state error detected, request disconnect\n");
  2890. return PCI_ERS_RESULT_DISCONNECT;
  2891. }
  2892. return PCI_ERS_RESULT_NEED_RESET;
  2893. }
  2894. static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
  2895. {
  2896. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2897. dev_info(dev->ctrl.device, "restart after slot reset\n");
  2898. pci_restore_state(pdev);
  2899. nvme_reset_ctrl(&dev->ctrl);
  2900. return PCI_ERS_RESULT_RECOVERED;
  2901. }
  2902. static void nvme_error_resume(struct pci_dev *pdev)
  2903. {
  2904. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2905. flush_work(&dev->ctrl.reset_work);
  2906. }
  2907. static const struct pci_error_handlers nvme_err_handler = {
  2908. .error_detected = nvme_error_detected,
  2909. .slot_reset = nvme_slot_reset,
  2910. .resume = nvme_error_resume,
  2911. .reset_prepare = nvme_reset_prepare,
  2912. .reset_done = nvme_reset_done,
  2913. };
  2914. static const struct pci_device_id nvme_id_table[] = {
  2915. { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
  2916. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2917. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2918. { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
  2919. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2920. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2921. { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
  2922. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2923. NVME_QUIRK_DEALLOCATE_ZEROES |
  2924. NVME_QUIRK_IGNORE_DEV_SUBNQN |
  2925. NVME_QUIRK_BOGUS_NID, },
  2926. { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
  2927. .driver_data = NVME_QUIRK_STRIPE_SIZE |
  2928. NVME_QUIRK_DEALLOCATE_ZEROES, },
  2929. { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
  2930. .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
  2931. NVME_QUIRK_MEDIUM_PRIO_SQ |
  2932. NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
  2933. NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2934. { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
  2935. .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
  2936. { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
  2937. .driver_data = NVME_QUIRK_IDENTIFY_CNS |
  2938. NVME_QUIRK_DISABLE_WRITE_ZEROES |
  2939. NVME_QUIRK_BOGUS_NID, },
  2940. { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
  2941. .driver_data = NVME_QUIRK_BOGUS_NID, },
  2942. { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
  2943. .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
  2944. NVME_QUIRK_BOGUS_NID, },
  2945. { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
  2946. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
  2947. NVME_QUIRK_NO_NS_DESC_LIST, },
  2948. { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
  2949. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2950. { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
  2951. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2952. { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
  2953. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2954. { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
  2955. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
  2956. { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
  2957. .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
  2958. NVME_QUIRK_DISABLE_WRITE_ZEROES|
  2959. NVME_QUIRK_IGNORE_DEV_SUBNQN, },
  2960. { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
  2961. .driver_data = NVME_QUIRK_BOGUS_NID, },
  2962. { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
  2963. .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
  2964. NVME_QUIRK_BOGUS_NID, },
  2965. { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
  2966. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2967. { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
  2968. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2969. { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
  2970. .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
  2971. NVME_QUIRK_IGNORE_DEV_SUBNQN, },
  2972. { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
  2973. .driver_data = NVME_QUIRK_BOGUS_NID, },
  2974. { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
  2975. .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
  2976. NVME_QUIRK_BOGUS_NID, },
  2977. { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
  2978. .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
  2979. NVME_QUIRK_IGNORE_DEV_SUBNQN, },
  2980. { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
  2981. .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
  2982. { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
  2983. .driver_data = NVME_QUIRK_BOGUS_NID, },
  2984. { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
  2985. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2986. { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
  2987. .driver_data = NVME_QUIRK_BOGUS_NID, },
  2988. { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
  2989. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2990. { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
  2991. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2992. { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
  2993. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
  2994. NVME_QUIRK_BOGUS_NID, },
  2995. { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
  2996. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2997. { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
  2998. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  2999. { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
  3000. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  3001. { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
  3002. .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
  3003. { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
  3004. .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
  3005. { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
  3006. .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
  3007. { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
  3008. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  3009. { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
  3010. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  3011. { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
  3012. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  3013. { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
  3014. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  3015. { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
  3016. .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
  3017. { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
  3018. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3019. { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
  3020. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3021. { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
  3022. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3023. { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
  3024. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3025. { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
  3026. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3027. { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
  3028. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3029. { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
  3030. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3031. { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
  3032. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3033. { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
  3034. .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
  3035. { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
  3036. .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
  3037. { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
  3038. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3039. { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
  3040. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3041. { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
  3042. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3043. { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
  3044. .driver_data = NVME_QUIRK_BOGUS_NID |
  3045. NVME_QUIRK_IGNORE_DEV_SUBNQN, },
  3046. { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
  3047. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3048. { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
  3049. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3050. { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
  3051. .driver_data = NVME_QUIRK_BOGUS_NID, },
  3052. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
  3053. .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
  3054. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
  3055. .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
  3056. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
  3057. .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
  3058. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
  3059. .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
  3060. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
  3061. .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
  3062. { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
  3063. .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
  3064. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
  3065. .driver_data = NVME_QUIRK_SINGLE_VECTOR },
  3066. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
  3067. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
  3068. .driver_data = NVME_QUIRK_SINGLE_VECTOR |
  3069. NVME_QUIRK_128_BYTES_SQES |
  3070. NVME_QUIRK_SHARED_TAGS |
  3071. NVME_QUIRK_SKIP_CID_GEN },
  3072. { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
  3073. { 0, }
  3074. };
  3075. MODULE_DEVICE_TABLE(pci, nvme_id_table);
  3076. static struct pci_driver nvme_driver = {
  3077. .name = "nvme",
  3078. .id_table = nvme_id_table,
  3079. .probe = nvme_probe,
  3080. .remove = nvme_remove,
  3081. .shutdown = nvme_shutdown,
  3082. #ifdef CONFIG_PM_SLEEP
  3083. .driver = {
  3084. .pm = &nvme_dev_pm_ops,
  3085. },
  3086. #endif
  3087. .sriov_configure = pci_sriov_configure_simple,
  3088. .err_handler = &nvme_err_handler,
  3089. };
  3090. static int __init nvme_init(void)
  3091. {
  3092. BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
  3093. BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
  3094. BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
  3095. BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
  3096. BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
  3097. S8_MAX);
  3098. return pci_register_driver(&nvme_driver);
  3099. }
  3100. static void __exit nvme_exit(void)
  3101. {
  3102. pci_unregister_driver(&nvme_driver);
  3103. flush_workqueue(nvme_wq);
  3104. }
  3105. MODULE_AUTHOR("Matthew Wilcox <[email protected]>");
  3106. MODULE_LICENSE("GPL");
  3107. MODULE_VERSION("1.0");
  3108. module_init(nvme_init);
  3109. module_exit(nvme_exit);