acx.h 9.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * This file is part of wl18xx
  4. *
  5. * Copyright (C) 2011 Texas Instruments. All rights reserved.
  6. */
  7. #ifndef __WL18XX_ACX_H__
  8. #define __WL18XX_ACX_H__
  9. #include "../wlcore/wlcore.h"
  10. #include "../wlcore/acx.h"
  11. enum {
  12. ACX_NS_IPV6_FILTER = 0x0050,
  13. ACX_PEER_HT_OPERATION_MODE_CFG = 0x0051,
  14. ACX_CSUM_CONFIG = 0x0052,
  15. ACX_SIM_CONFIG = 0x0053,
  16. ACX_CLEAR_STATISTICS = 0x0054,
  17. ACX_AUTO_RX_STREAMING = 0x0055,
  18. ACX_PEER_CAP = 0x0056,
  19. ACX_INTERRUPT_NOTIFY = 0x0057,
  20. ACX_RX_BA_FILTER = 0x0058,
  21. ACX_AP_SLEEP_CFG = 0x0059,
  22. ACX_DYNAMIC_TRACES_CFG = 0x005A,
  23. ACX_TIME_SYNC_CFG = 0x005B,
  24. };
  25. /* numbers of bits the length field takes (add 1 for the actual number) */
  26. #define WL18XX_HOST_IF_LEN_SIZE_FIELD 15
  27. #define WL18XX_ACX_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
  28. WL1271_ACX_INTR_INIT_COMPLETE | \
  29. WL1271_ACX_INTR_EVENT_A | \
  30. WL1271_ACX_INTR_EVENT_B | \
  31. WL1271_ACX_INTR_CMD_COMPLETE | \
  32. WL1271_ACX_INTR_HW_AVAILABLE | \
  33. WL1271_ACX_INTR_DATA | \
  34. WL1271_ACX_SW_INTR_WATCHDOG)
  35. #define WL18XX_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \
  36. WL1271_ACX_INTR_EVENT_A | \
  37. WL1271_ACX_INTR_EVENT_B | \
  38. WL1271_ACX_INTR_HW_AVAILABLE | \
  39. WL1271_ACX_INTR_DATA | \
  40. WL1271_ACX_SW_INTR_WATCHDOG)
  41. struct wl18xx_acx_host_config_bitmap {
  42. struct acx_header header;
  43. __le32 host_cfg_bitmap;
  44. __le32 host_sdio_block_size;
  45. /* extra mem blocks per frame in TX. */
  46. __le32 extra_mem_blocks;
  47. /*
  48. * number of bits of the length field in the first TX word
  49. * (up to 15 - for using the entire 16 bits).
  50. */
  51. __le32 length_field_size;
  52. } __packed;
  53. enum {
  54. CHECKSUM_OFFLOAD_DISABLED = 0,
  55. CHECKSUM_OFFLOAD_ENABLED = 1,
  56. CHECKSUM_OFFLOAD_FAKE_RX = 2,
  57. CHECKSUM_OFFLOAD_INVALID = 0xFF
  58. };
  59. struct wl18xx_acx_checksum_state {
  60. struct acx_header header;
  61. /* enum acx_checksum_state */
  62. u8 checksum_state;
  63. u8 pad[3];
  64. } __packed;
  65. struct wl18xx_acx_error_stats {
  66. u32 error_frame_non_ctrl;
  67. u32 error_frame_ctrl;
  68. u32 error_frame_during_protection;
  69. u32 null_frame_tx_start;
  70. u32 null_frame_cts_start;
  71. u32 bar_retry;
  72. u32 num_frame_cts_nul_flid;
  73. u32 tx_abort_failure;
  74. u32 tx_resume_failure;
  75. u32 rx_cmplt_db_overflow_cnt;
  76. u32 elp_while_rx_exch;
  77. u32 elp_while_tx_exch;
  78. u32 elp_while_tx;
  79. u32 elp_while_nvic_pending;
  80. u32 rx_excessive_frame_len;
  81. u32 burst_mismatch;
  82. u32 tbc_exch_mismatch;
  83. } __packed;
  84. #define NUM_OF_RATES_INDEXES 30
  85. struct wl18xx_acx_tx_stats {
  86. u32 tx_prepared_descs;
  87. u32 tx_cmplt;
  88. u32 tx_template_prepared;
  89. u32 tx_data_prepared;
  90. u32 tx_template_programmed;
  91. u32 tx_data_programmed;
  92. u32 tx_burst_programmed;
  93. u32 tx_starts;
  94. u32 tx_stop;
  95. u32 tx_start_templates;
  96. u32 tx_start_int_templates;
  97. u32 tx_start_fw_gen;
  98. u32 tx_start_data;
  99. u32 tx_start_null_frame;
  100. u32 tx_exch;
  101. u32 tx_retry_template;
  102. u32 tx_retry_data;
  103. u32 tx_retry_per_rate[NUM_OF_RATES_INDEXES];
  104. u32 tx_exch_pending;
  105. u32 tx_exch_expiry;
  106. u32 tx_done_template;
  107. u32 tx_done_data;
  108. u32 tx_done_int_template;
  109. u32 tx_cfe1;
  110. u32 tx_cfe2;
  111. u32 frag_called;
  112. u32 frag_mpdu_alloc_failed;
  113. u32 frag_init_called;
  114. u32 frag_in_process_called;
  115. u32 frag_tkip_called;
  116. u32 frag_key_not_found;
  117. u32 frag_need_fragmentation;
  118. u32 frag_bad_mblk_num;
  119. u32 frag_failed;
  120. u32 frag_cache_hit;
  121. u32 frag_cache_miss;
  122. } __packed;
  123. struct wl18xx_acx_rx_stats {
  124. u32 rx_beacon_early_term;
  125. u32 rx_out_of_mpdu_nodes;
  126. u32 rx_hdr_overflow;
  127. u32 rx_dropped_frame;
  128. u32 rx_done_stage;
  129. u32 rx_done;
  130. u32 rx_defrag;
  131. u32 rx_defrag_end;
  132. u32 rx_cmplt;
  133. u32 rx_pre_complt;
  134. u32 rx_cmplt_task;
  135. u32 rx_phy_hdr;
  136. u32 rx_timeout;
  137. u32 rx_rts_timeout;
  138. u32 rx_timeout_wa;
  139. u32 defrag_called;
  140. u32 defrag_init_called;
  141. u32 defrag_in_process_called;
  142. u32 defrag_tkip_called;
  143. u32 defrag_need_defrag;
  144. u32 defrag_decrypt_failed;
  145. u32 decrypt_key_not_found;
  146. u32 defrag_need_decrypt;
  147. u32 rx_tkip_replays;
  148. u32 rx_xfr;
  149. } __packed;
  150. struct wl18xx_acx_isr_stats {
  151. u32 irqs;
  152. } __packed;
  153. #define PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD 10
  154. struct wl18xx_acx_pwr_stats {
  155. u32 missing_bcns_cnt;
  156. u32 rcvd_bcns_cnt;
  157. u32 connection_out_of_sync;
  158. u32 cont_miss_bcns_spread[PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD];
  159. u32 rcvd_awake_bcns_cnt;
  160. u32 sleep_time_count;
  161. u32 sleep_time_avg;
  162. u32 sleep_cycle_avg;
  163. u32 sleep_percent;
  164. u32 ap_sleep_active_conf;
  165. u32 ap_sleep_user_conf;
  166. u32 ap_sleep_counter;
  167. } __packed;
  168. struct wl18xx_acx_rx_filter_stats {
  169. u32 beacon_filter;
  170. u32 arp_filter;
  171. u32 mc_filter;
  172. u32 dup_filter;
  173. u32 data_filter;
  174. u32 ibss_filter;
  175. u32 protection_filter;
  176. u32 accum_arp_pend_requests;
  177. u32 max_arp_queue_dep;
  178. } __packed;
  179. struct wl18xx_acx_rx_rate_stats {
  180. u32 rx_frames_per_rates[50];
  181. } __packed;
  182. #define AGGR_STATS_TX_AGG 16
  183. #define AGGR_STATS_RX_SIZE_LEN 16
  184. struct wl18xx_acx_aggr_stats {
  185. u32 tx_agg_rate[AGGR_STATS_TX_AGG];
  186. u32 tx_agg_len[AGGR_STATS_TX_AGG];
  187. u32 rx_size[AGGR_STATS_RX_SIZE_LEN];
  188. } __packed;
  189. #define PIPE_STATS_HW_FIFO 11
  190. struct wl18xx_acx_pipeline_stats {
  191. u32 hs_tx_stat_fifo_int;
  192. u32 hs_rx_stat_fifo_int;
  193. u32 enc_tx_stat_fifo_int;
  194. u32 enc_rx_stat_fifo_int;
  195. u32 rx_complete_stat_fifo_int;
  196. u32 pre_proc_swi;
  197. u32 post_proc_swi;
  198. u32 sec_frag_swi;
  199. u32 pre_to_defrag_swi;
  200. u32 defrag_to_rx_xfer_swi;
  201. u32 dec_packet_in;
  202. u32 dec_packet_in_fifo_full;
  203. u32 dec_packet_out;
  204. u16 pipeline_fifo_full[PIPE_STATS_HW_FIFO];
  205. u16 padding;
  206. } __packed;
  207. #define DIVERSITY_STATS_NUM_OF_ANT 2
  208. struct wl18xx_acx_diversity_stats {
  209. u32 num_of_packets_per_ant[DIVERSITY_STATS_NUM_OF_ANT];
  210. u32 total_num_of_toggles;
  211. } __packed;
  212. struct wl18xx_acx_thermal_stats {
  213. u16 irq_thr_low;
  214. u16 irq_thr_high;
  215. u16 tx_stop;
  216. u16 tx_resume;
  217. u16 false_irq;
  218. u16 adc_source_unexpected;
  219. } __packed;
  220. #define WL18XX_NUM_OF_CALIBRATIONS_ERRORS 18
  221. struct wl18xx_acx_calib_failure_stats {
  222. u16 fail_count[WL18XX_NUM_OF_CALIBRATIONS_ERRORS];
  223. u32 calib_count;
  224. } __packed;
  225. struct wl18xx_roaming_stats {
  226. s32 rssi_level;
  227. } __packed;
  228. struct wl18xx_dfs_stats {
  229. u32 num_of_radar_detections;
  230. } __packed;
  231. struct wl18xx_acx_statistics {
  232. struct acx_header header;
  233. struct wl18xx_acx_error_stats error;
  234. struct wl18xx_acx_tx_stats tx;
  235. struct wl18xx_acx_rx_stats rx;
  236. struct wl18xx_acx_isr_stats isr;
  237. struct wl18xx_acx_pwr_stats pwr;
  238. struct wl18xx_acx_rx_filter_stats rx_filter;
  239. struct wl18xx_acx_rx_rate_stats rx_rate;
  240. struct wl18xx_acx_aggr_stats aggr_size;
  241. struct wl18xx_acx_pipeline_stats pipeline;
  242. struct wl18xx_acx_diversity_stats diversity;
  243. struct wl18xx_acx_thermal_stats thermal;
  244. struct wl18xx_acx_calib_failure_stats calib;
  245. struct wl18xx_roaming_stats roaming;
  246. struct wl18xx_dfs_stats dfs;
  247. } __packed;
  248. struct wl18xx_acx_clear_statistics {
  249. struct acx_header header;
  250. };
  251. enum wlcore_bandwidth {
  252. WLCORE_BANDWIDTH_20MHZ,
  253. WLCORE_BANDWIDTH_40MHZ,
  254. };
  255. struct wlcore_peer_ht_operation_mode {
  256. struct acx_header header;
  257. u8 hlid;
  258. u8 bandwidth; /* enum wlcore_bandwidth */
  259. u8 padding[2];
  260. };
  261. /*
  262. * ACX_PEER_CAP
  263. * this struct is very similar to wl1271_acx_ht_capabilities, with the
  264. * addition of supported rates
  265. */
  266. struct wlcore_acx_peer_cap {
  267. struct acx_header header;
  268. /* bitmask of capability bits supported by the peer */
  269. __le32 ht_capabilites;
  270. /* rates supported by the remote peer */
  271. __le32 supported_rates;
  272. /* Indicates to which link these capabilities apply. */
  273. u8 hlid;
  274. /*
  275. * This the maximum A-MPDU length supported by the AP. The FW may not
  276. * exceed this length when sending A-MPDUs
  277. */
  278. u8 ampdu_max_length;
  279. /* This is the minimal spacing required when sending A-MPDUs to the AP*/
  280. u8 ampdu_min_spacing;
  281. u8 padding;
  282. } __packed;
  283. /*
  284. * ACX_INTERRUPT_NOTIFY
  285. * enable/disable fast-link/PSM notification from FW
  286. */
  287. struct wl18xx_acx_interrupt_notify {
  288. struct acx_header header;
  289. u32 enable;
  290. };
  291. /*
  292. * ACX_RX_BA_FILTER
  293. * enable/disable RX BA filtering in FW
  294. */
  295. struct wl18xx_acx_rx_ba_filter {
  296. struct acx_header header;
  297. u32 enable;
  298. };
  299. struct acx_ap_sleep_cfg {
  300. struct acx_header header;
  301. /* Duty Cycle (20-80% of staying Awake) for IDLE AP
  302. * (0: disable)
  303. */
  304. u8 idle_duty_cycle;
  305. /* Duty Cycle (20-80% of staying Awake) for Connected AP
  306. * (0: disable)
  307. */
  308. u8 connected_duty_cycle;
  309. /* Maximum stations that are allowed to be connected to AP
  310. * (255: no limit)
  311. */
  312. u8 max_stations_thresh;
  313. /* Timeout till enabling the Sleep Mechanism after data stops
  314. * [unit: 100 msec]
  315. */
  316. u8 idle_conn_thresh;
  317. } __packed;
  318. /*
  319. * ACX_DYNAMIC_TRACES_CFG
  320. * configure the FW dynamic traces
  321. */
  322. struct acx_dynamic_fw_traces_cfg {
  323. struct acx_header header;
  324. __le32 dynamic_fw_traces;
  325. } __packed;
  326. /*
  327. * ACX_TIME_SYNC_CFG
  328. * configure the time sync parameters
  329. */
  330. struct acx_time_sync_cfg {
  331. struct acx_header header;
  332. u8 sync_mode;
  333. u8 zone_mac_addr[ETH_ALEN];
  334. u8 padding[1];
  335. } __packed;
  336. int wl18xx_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap,
  337. u32 sdio_blk_size, u32 extra_mem_blks,
  338. u32 len_field_size);
  339. int wl18xx_acx_set_checksum_state(struct wl1271 *wl);
  340. int wl18xx_acx_clear_statistics(struct wl1271 *wl);
  341. int wl18xx_acx_peer_ht_operation_mode(struct wl1271 *wl, u8 hlid, bool wide);
  342. int wl18xx_acx_set_peer_cap(struct wl1271 *wl,
  343. struct ieee80211_sta_ht_cap *ht_cap,
  344. bool allow_ht_operation,
  345. u32 rate_set, u8 hlid);
  346. int wl18xx_acx_interrupt_notify_config(struct wl1271 *wl, bool action);
  347. int wl18xx_acx_rx_ba_filter(struct wl1271 *wl, bool action);
  348. int wl18xx_acx_ap_sleep(struct wl1271 *wl);
  349. int wl18xx_acx_dynamic_fw_traces(struct wl1271 *wl);
  350. int wl18xx_acx_time_sync_cfg(struct wl1271 *wl);
  351. #endif /* __WL18XX_ACX_H__ */