wanxl.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * wanXL serial card driver for Linux
  4. * host part
  5. *
  6. * Copyright (C) 2003 Krzysztof Halasa <[email protected]>
  7. *
  8. * Status:
  9. * - Only DTE (external clock) support with NRZ and NRZI encodings
  10. * - wanXL100 will require minor driver modifications, no access to hw
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/slab.h>
  16. #include <linux/sched.h>
  17. #include <linux/types.h>
  18. #include <linux/fcntl.h>
  19. #include <linux/string.h>
  20. #include <linux/errno.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/ioport.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/hdlc.h>
  26. #include <linux/pci.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/delay.h>
  29. #include <asm/io.h>
  30. #include "wanxl.h"
  31. static const char *version = "wanXL serial card driver version: 0.48";
  32. #define PLX_CTL_RESET 0x40000000 /* adapter reset */
  33. #undef DEBUG_PKT
  34. #undef DEBUG_PCI
  35. /* MAILBOX #1 - PUTS COMMANDS */
  36. #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
  37. #ifdef __LITTLE_ENDIAN
  38. #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
  39. #else
  40. #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
  41. #endif
  42. /* MAILBOX #2 - DRAM SIZE */
  43. #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
  44. struct port {
  45. struct net_device *dev;
  46. struct card *card;
  47. spinlock_t lock; /* for wanxl_xmit */
  48. int node; /* physical port #0 - 3 */
  49. unsigned int clock_type;
  50. int tx_in, tx_out;
  51. struct sk_buff *tx_skbs[TX_BUFFERS];
  52. };
  53. struct card_status {
  54. desc_t rx_descs[RX_QUEUE_LENGTH];
  55. port_status_t port_status[4];
  56. };
  57. struct card {
  58. int n_ports; /* 1, 2 or 4 ports */
  59. u8 irq;
  60. u8 __iomem *plx; /* PLX PCI9060 virtual base address */
  61. struct pci_dev *pdev; /* for pci_name(pdev) */
  62. int rx_in;
  63. struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
  64. struct card_status *status; /* shared between host and card */
  65. dma_addr_t status_address;
  66. struct port ports[]; /* 1 - 4 port structures follow */
  67. };
  68. static inline struct port *dev_to_port(struct net_device *dev)
  69. {
  70. return (struct port *)dev_to_hdlc(dev)->priv;
  71. }
  72. static inline port_status_t *get_status(struct port *port)
  73. {
  74. return &port->card->status->port_status[port->node];
  75. }
  76. #ifdef DEBUG_PCI
  77. static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
  78. size_t size, int direction)
  79. {
  80. dma_addr_t addr = dma_map_single(&pdev->dev, ptr, size, direction);
  81. if (addr + size > 0x100000000LL)
  82. pr_crit("%s: pci_map_single() returned memory at 0x%llx!\n",
  83. pci_name(pdev), (unsigned long long)addr);
  84. return addr;
  85. }
  86. #undef pci_map_single
  87. #define pci_map_single pci_map_single_debug
  88. #endif
  89. /* Cable and/or personality module change interrupt service */
  90. static inline void wanxl_cable_intr(struct port *port)
  91. {
  92. u32 value = get_status(port)->cable;
  93. int valid = 1;
  94. const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
  95. switch (value & 0x7) {
  96. case STATUS_CABLE_V35:
  97. cable = "V.35";
  98. break;
  99. case STATUS_CABLE_X21:
  100. cable = "X.21";
  101. break;
  102. case STATUS_CABLE_V24:
  103. cable = "V.24";
  104. break;
  105. case STATUS_CABLE_EIA530:
  106. cable = "EIA530";
  107. break;
  108. case STATUS_CABLE_NONE:
  109. cable = "no";
  110. break;
  111. default:
  112. cable = "invalid";
  113. }
  114. switch ((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
  115. case STATUS_CABLE_V35:
  116. pm = "V.35";
  117. break;
  118. case STATUS_CABLE_X21:
  119. pm = "X.21";
  120. break;
  121. case STATUS_CABLE_V24:
  122. pm = "V.24";
  123. break;
  124. case STATUS_CABLE_EIA530:
  125. pm = "EIA530";
  126. break;
  127. case STATUS_CABLE_NONE:
  128. pm = "no personality";
  129. valid = 0;
  130. break;
  131. default:
  132. pm = "invalid personality";
  133. valid = 0;
  134. }
  135. if (valid) {
  136. if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
  137. dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
  138. ", DSR off";
  139. dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
  140. ", carrier off";
  141. }
  142. dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
  143. }
  144. netdev_info(port->dev, "%s%s module, %s cable%s%s\n",
  145. pm, dte, cable, dsr, dcd);
  146. if (value & STATUS_CABLE_DCD)
  147. netif_carrier_on(port->dev);
  148. else
  149. netif_carrier_off(port->dev);
  150. }
  151. /* Transmit complete interrupt service */
  152. static inline void wanxl_tx_intr(struct port *port)
  153. {
  154. struct net_device *dev = port->dev;
  155. while (1) {
  156. desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
  157. struct sk_buff *skb = port->tx_skbs[port->tx_in];
  158. switch (desc->stat) {
  159. case PACKET_FULL:
  160. case PACKET_EMPTY:
  161. netif_wake_queue(dev);
  162. return;
  163. case PACKET_UNDERRUN:
  164. dev->stats.tx_errors++;
  165. dev->stats.tx_fifo_errors++;
  166. break;
  167. default:
  168. dev->stats.tx_packets++;
  169. dev->stats.tx_bytes += skb->len;
  170. }
  171. desc->stat = PACKET_EMPTY; /* Free descriptor */
  172. dma_unmap_single(&port->card->pdev->dev, desc->address,
  173. skb->len, DMA_TO_DEVICE);
  174. dev_consume_skb_irq(skb);
  175. port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
  176. }
  177. }
  178. /* Receive complete interrupt service */
  179. static inline void wanxl_rx_intr(struct card *card)
  180. {
  181. desc_t *desc;
  182. while (desc = &card->status->rx_descs[card->rx_in],
  183. desc->stat != PACKET_EMPTY) {
  184. if ((desc->stat & PACKET_PORT_MASK) > card->n_ports) {
  185. pr_crit("%s: received packet for nonexistent port\n",
  186. pci_name(card->pdev));
  187. } else {
  188. struct sk_buff *skb = card->rx_skbs[card->rx_in];
  189. struct port *port = &card->ports[desc->stat &
  190. PACKET_PORT_MASK];
  191. struct net_device *dev = port->dev;
  192. if (!skb) {
  193. dev->stats.rx_dropped++;
  194. } else {
  195. dma_unmap_single(&card->pdev->dev,
  196. desc->address, BUFFER_LENGTH,
  197. DMA_FROM_DEVICE);
  198. skb_put(skb, desc->length);
  199. #ifdef DEBUG_PKT
  200. printk(KERN_DEBUG "%s RX(%i):", dev->name,
  201. skb->len);
  202. debug_frame(skb);
  203. #endif
  204. dev->stats.rx_packets++;
  205. dev->stats.rx_bytes += skb->len;
  206. skb->protocol = hdlc_type_trans(skb, dev);
  207. netif_rx(skb);
  208. skb = NULL;
  209. }
  210. if (!skb) {
  211. skb = dev_alloc_skb(BUFFER_LENGTH);
  212. desc->address = skb ?
  213. dma_map_single(&card->pdev->dev,
  214. skb->data,
  215. BUFFER_LENGTH,
  216. DMA_FROM_DEVICE) : 0;
  217. card->rx_skbs[card->rx_in] = skb;
  218. }
  219. }
  220. desc->stat = PACKET_EMPTY; /* Free descriptor */
  221. card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
  222. }
  223. }
  224. static irqreturn_t wanxl_intr(int irq, void *dev_id)
  225. {
  226. struct card *card = dev_id;
  227. int i;
  228. u32 stat;
  229. int handled = 0;
  230. while ((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
  231. handled = 1;
  232. writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
  233. for (i = 0; i < card->n_ports; i++) {
  234. if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
  235. wanxl_tx_intr(&card->ports[i]);
  236. if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
  237. wanxl_cable_intr(&card->ports[i]);
  238. }
  239. if (stat & (1 << DOORBELL_FROM_CARD_RX))
  240. wanxl_rx_intr(card);
  241. }
  242. return IRQ_RETVAL(handled);
  243. }
  244. static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
  245. {
  246. struct port *port = dev_to_port(dev);
  247. desc_t *desc;
  248. spin_lock(&port->lock);
  249. desc = &get_status(port)->tx_descs[port->tx_out];
  250. if (desc->stat != PACKET_EMPTY) {
  251. /* should never happen - previous xmit should stop queue */
  252. #ifdef DEBUG_PKT
  253. printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
  254. #endif
  255. netif_stop_queue(dev);
  256. spin_unlock(&port->lock);
  257. return NETDEV_TX_BUSY; /* request packet to be queued */
  258. }
  259. #ifdef DEBUG_PKT
  260. printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
  261. debug_frame(skb);
  262. #endif
  263. port->tx_skbs[port->tx_out] = skb;
  264. desc->address = dma_map_single(&port->card->pdev->dev, skb->data,
  265. skb->len, DMA_TO_DEVICE);
  266. desc->length = skb->len;
  267. desc->stat = PACKET_FULL;
  268. writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
  269. port->card->plx + PLX_DOORBELL_TO_CARD);
  270. port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
  271. if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
  272. netif_stop_queue(dev);
  273. #ifdef DEBUG_PKT
  274. printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
  275. #endif
  276. }
  277. spin_unlock(&port->lock);
  278. return NETDEV_TX_OK;
  279. }
  280. static int wanxl_attach(struct net_device *dev, unsigned short encoding,
  281. unsigned short parity)
  282. {
  283. struct port *port = dev_to_port(dev);
  284. if (encoding != ENCODING_NRZ &&
  285. encoding != ENCODING_NRZI)
  286. return -EINVAL;
  287. if (parity != PARITY_NONE &&
  288. parity != PARITY_CRC32_PR1_CCITT &&
  289. parity != PARITY_CRC16_PR1_CCITT &&
  290. parity != PARITY_CRC32_PR0_CCITT &&
  291. parity != PARITY_CRC16_PR0_CCITT)
  292. return -EINVAL;
  293. get_status(port)->encoding = encoding;
  294. get_status(port)->parity = parity;
  295. return 0;
  296. }
  297. static int wanxl_ioctl(struct net_device *dev, struct if_settings *ifs)
  298. {
  299. const size_t size = sizeof(sync_serial_settings);
  300. sync_serial_settings line;
  301. struct port *port = dev_to_port(dev);
  302. switch (ifs->type) {
  303. case IF_GET_IFACE:
  304. ifs->type = IF_IFACE_SYNC_SERIAL;
  305. if (ifs->size < size) {
  306. ifs->size = size; /* data size wanted */
  307. return -ENOBUFS;
  308. }
  309. memset(&line, 0, sizeof(line));
  310. line.clock_type = get_status(port)->clocking;
  311. line.clock_rate = 0;
  312. line.loopback = 0;
  313. if (copy_to_user(ifs->ifs_ifsu.sync, &line, size))
  314. return -EFAULT;
  315. return 0;
  316. case IF_IFACE_SYNC_SERIAL:
  317. if (!capable(CAP_NET_ADMIN))
  318. return -EPERM;
  319. if (dev->flags & IFF_UP)
  320. return -EBUSY;
  321. if (copy_from_user(&line, ifs->ifs_ifsu.sync,
  322. size))
  323. return -EFAULT;
  324. if (line.clock_type != CLOCK_EXT &&
  325. line.clock_type != CLOCK_TXFROMRX)
  326. return -EINVAL; /* No such clock setting */
  327. if (line.loopback != 0)
  328. return -EINVAL;
  329. get_status(port)->clocking = line.clock_type;
  330. return 0;
  331. default:
  332. return hdlc_ioctl(dev, ifs);
  333. }
  334. }
  335. static int wanxl_open(struct net_device *dev)
  336. {
  337. struct port *port = dev_to_port(dev);
  338. u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
  339. unsigned long timeout;
  340. int i;
  341. if (get_status(port)->open) {
  342. netdev_err(dev, "port already open\n");
  343. return -EIO;
  344. }
  345. i = hdlc_open(dev);
  346. if (i)
  347. return i;
  348. port->tx_in = port->tx_out = 0;
  349. for (i = 0; i < TX_BUFFERS; i++)
  350. get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
  351. /* signal the card */
  352. writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
  353. timeout = jiffies + HZ;
  354. do {
  355. if (get_status(port)->open) {
  356. netif_start_queue(dev);
  357. return 0;
  358. }
  359. } while (time_after(timeout, jiffies));
  360. netdev_err(dev, "unable to open port\n");
  361. /* ask the card to close the port, should it be still alive */
  362. writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
  363. return -EFAULT;
  364. }
  365. static int wanxl_close(struct net_device *dev)
  366. {
  367. struct port *port = dev_to_port(dev);
  368. unsigned long timeout;
  369. int i;
  370. hdlc_close(dev);
  371. /* signal the card */
  372. writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
  373. port->card->plx + PLX_DOORBELL_TO_CARD);
  374. timeout = jiffies + HZ;
  375. do {
  376. if (!get_status(port)->open)
  377. break;
  378. } while (time_after(timeout, jiffies));
  379. if (get_status(port)->open)
  380. netdev_err(dev, "unable to close port\n");
  381. netif_stop_queue(dev);
  382. for (i = 0; i < TX_BUFFERS; i++) {
  383. desc_t *desc = &get_status(port)->tx_descs[i];
  384. if (desc->stat != PACKET_EMPTY) {
  385. desc->stat = PACKET_EMPTY;
  386. dma_unmap_single(&port->card->pdev->dev,
  387. desc->address, port->tx_skbs[i]->len,
  388. DMA_TO_DEVICE);
  389. dev_kfree_skb(port->tx_skbs[i]);
  390. }
  391. }
  392. return 0;
  393. }
  394. static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
  395. {
  396. struct port *port = dev_to_port(dev);
  397. dev->stats.rx_over_errors = get_status(port)->rx_overruns;
  398. dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors;
  399. dev->stats.rx_errors = dev->stats.rx_over_errors +
  400. dev->stats.rx_frame_errors;
  401. return &dev->stats;
  402. }
  403. static int wanxl_puts_command(struct card *card, u32 cmd)
  404. {
  405. unsigned long timeout = jiffies + 5 * HZ;
  406. writel(cmd, card->plx + PLX_MAILBOX_1);
  407. do {
  408. if (readl(card->plx + PLX_MAILBOX_1) == 0)
  409. return 0;
  410. schedule();
  411. } while (time_after(timeout, jiffies));
  412. return -1;
  413. }
  414. static void wanxl_reset(struct card *card)
  415. {
  416. u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
  417. writel(0x80, card->plx + PLX_MAILBOX_0);
  418. writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
  419. readl(card->plx + PLX_CONTROL); /* wait for posted write */
  420. udelay(1);
  421. writel(old_value, card->plx + PLX_CONTROL);
  422. readl(card->plx + PLX_CONTROL); /* wait for posted write */
  423. }
  424. static void wanxl_pci_remove_one(struct pci_dev *pdev)
  425. {
  426. struct card *card = pci_get_drvdata(pdev);
  427. int i;
  428. for (i = 0; i < card->n_ports; i++) {
  429. unregister_hdlc_device(card->ports[i].dev);
  430. free_netdev(card->ports[i].dev);
  431. }
  432. /* unregister and free all host resources */
  433. if (card->irq)
  434. free_irq(card->irq, card);
  435. wanxl_reset(card);
  436. for (i = 0; i < RX_QUEUE_LENGTH; i++)
  437. if (card->rx_skbs[i]) {
  438. dma_unmap_single(&card->pdev->dev,
  439. card->status->rx_descs[i].address,
  440. BUFFER_LENGTH, DMA_FROM_DEVICE);
  441. dev_kfree_skb(card->rx_skbs[i]);
  442. }
  443. if (card->plx)
  444. iounmap(card->plx);
  445. if (card->status)
  446. dma_free_coherent(&pdev->dev, sizeof(struct card_status),
  447. card->status, card->status_address);
  448. pci_release_regions(pdev);
  449. pci_disable_device(pdev);
  450. kfree(card);
  451. }
  452. #include "wanxlfw.inc"
  453. static const struct net_device_ops wanxl_ops = {
  454. .ndo_open = wanxl_open,
  455. .ndo_stop = wanxl_close,
  456. .ndo_start_xmit = hdlc_start_xmit,
  457. .ndo_siocwandev = wanxl_ioctl,
  458. .ndo_get_stats = wanxl_get_stats,
  459. };
  460. static int wanxl_pci_init_one(struct pci_dev *pdev,
  461. const struct pci_device_id *ent)
  462. {
  463. struct card *card;
  464. u32 ramsize, stat;
  465. unsigned long timeout;
  466. u32 plx_phy; /* PLX PCI base address */
  467. u32 mem_phy; /* memory PCI base addr */
  468. u8 __iomem *mem; /* memory virtual base addr */
  469. int i, ports;
  470. #ifndef MODULE
  471. pr_info_once("%s\n", version);
  472. #endif
  473. i = pci_enable_device(pdev);
  474. if (i)
  475. return i;
  476. /* QUICC can only access first 256 MB of host RAM directly,
  477. * but PLX9060 DMA does 32-bits for actual packet data transfers
  478. */
  479. /* FIXME when PCI/DMA subsystems are fixed.
  480. * We set both dma_mask and consistent_dma_mask to 28 bits
  481. * and pray pci_alloc_consistent() will use this info. It should
  482. * work on most platforms
  483. */
  484. if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(28)) ||
  485. dma_set_mask(&pdev->dev, DMA_BIT_MASK(28))) {
  486. pr_err("No usable DMA configuration\n");
  487. pci_disable_device(pdev);
  488. return -EIO;
  489. }
  490. i = pci_request_regions(pdev, "wanXL");
  491. if (i) {
  492. pci_disable_device(pdev);
  493. return i;
  494. }
  495. switch (pdev->device) {
  496. case PCI_DEVICE_ID_SBE_WANXL100:
  497. ports = 1;
  498. break;
  499. case PCI_DEVICE_ID_SBE_WANXL200:
  500. ports = 2;
  501. break;
  502. default:
  503. ports = 4;
  504. }
  505. card = kzalloc(struct_size(card, ports, ports), GFP_KERNEL);
  506. if (!card) {
  507. pci_release_regions(pdev);
  508. pci_disable_device(pdev);
  509. return -ENOBUFS;
  510. }
  511. pci_set_drvdata(pdev, card);
  512. card->pdev = pdev;
  513. card->status = dma_alloc_coherent(&pdev->dev,
  514. sizeof(struct card_status),
  515. &card->status_address, GFP_KERNEL);
  516. if (!card->status) {
  517. wanxl_pci_remove_one(pdev);
  518. return -ENOBUFS;
  519. }
  520. #ifdef DEBUG_PCI
  521. printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
  522. " at 0x%LX\n", pci_name(pdev),
  523. (unsigned long long)card->status_address);
  524. #endif
  525. /* FIXME when PCI/DMA subsystems are fixed.
  526. * We set both dma_mask and consistent_dma_mask back to 32 bits
  527. * to indicate the card can do 32-bit DMA addressing
  528. */
  529. if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)) ||
  530. dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
  531. pr_err("No usable DMA configuration\n");
  532. wanxl_pci_remove_one(pdev);
  533. return -EIO;
  534. }
  535. /* set up PLX mapping */
  536. plx_phy = pci_resource_start(pdev, 0);
  537. card->plx = ioremap(plx_phy, 0x70);
  538. if (!card->plx) {
  539. pr_err("ioremap() failed\n");
  540. wanxl_pci_remove_one(pdev);
  541. return -EFAULT;
  542. }
  543. #if RESET_WHILE_LOADING
  544. wanxl_reset(card);
  545. #endif
  546. timeout = jiffies + 20 * HZ;
  547. while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
  548. if (time_before(timeout, jiffies)) {
  549. pr_warn("%s: timeout waiting for PUTS to complete\n",
  550. pci_name(pdev));
  551. wanxl_pci_remove_one(pdev);
  552. return -ENODEV;
  553. }
  554. switch (stat & 0xC0) {
  555. case 0x00: /* hmm - PUTS completed with non-zero code? */
  556. case 0x80: /* PUTS still testing the hardware */
  557. break;
  558. default:
  559. pr_warn("%s: PUTS test 0x%X failed\n",
  560. pci_name(pdev), stat & 0x30);
  561. wanxl_pci_remove_one(pdev);
  562. return -ENODEV;
  563. }
  564. schedule();
  565. }
  566. /* get on-board memory size (PUTS detects no more than 4 MB) */
  567. ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
  568. /* set up on-board RAM mapping */
  569. mem_phy = pci_resource_start(pdev, 2);
  570. /* sanity check the board's reported memory size */
  571. if (ramsize < BUFFERS_ADDR +
  572. (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
  573. pr_warn("%s: no enough on-board RAM (%u bytes detected, %u bytes required)\n",
  574. pci_name(pdev), ramsize,
  575. BUFFERS_ADDR +
  576. (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
  577. wanxl_pci_remove_one(pdev);
  578. return -ENODEV;
  579. }
  580. if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
  581. pr_warn("%s: unable to Set Byte Swap Mode\n", pci_name(pdev));
  582. wanxl_pci_remove_one(pdev);
  583. return -ENODEV;
  584. }
  585. for (i = 0; i < RX_QUEUE_LENGTH; i++) {
  586. struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
  587. card->rx_skbs[i] = skb;
  588. if (skb)
  589. card->status->rx_descs[i].address =
  590. dma_map_single(&card->pdev->dev, skb->data,
  591. BUFFER_LENGTH, DMA_FROM_DEVICE);
  592. }
  593. mem = ioremap(mem_phy, PDM_OFFSET + sizeof(firmware));
  594. if (!mem) {
  595. pr_err("ioremap() failed\n");
  596. wanxl_pci_remove_one(pdev);
  597. return -EFAULT;
  598. }
  599. for (i = 0; i < sizeof(firmware); i += 4)
  600. writel(ntohl(*(__be32 *)(firmware + i)), mem + PDM_OFFSET + i);
  601. for (i = 0; i < ports; i++)
  602. writel(card->status_address +
  603. (void *)&card->status->port_status[i] -
  604. (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
  605. writel(card->status_address, mem + PDM_OFFSET + 20);
  606. writel(PDM_OFFSET, mem);
  607. iounmap(mem);
  608. writel(0, card->plx + PLX_MAILBOX_5);
  609. if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
  610. pr_warn("%s: unable to Abort and Jump\n", pci_name(pdev));
  611. wanxl_pci_remove_one(pdev);
  612. return -ENODEV;
  613. }
  614. timeout = jiffies + 5 * HZ;
  615. do {
  616. stat = readl(card->plx + PLX_MAILBOX_5);
  617. if (stat)
  618. break;
  619. schedule();
  620. } while (time_after(timeout, jiffies));
  621. if (!stat) {
  622. pr_warn("%s: timeout while initializing card firmware\n",
  623. pci_name(pdev));
  624. wanxl_pci_remove_one(pdev);
  625. return -ENODEV;
  626. }
  627. #if DETECT_RAM
  628. ramsize = stat;
  629. #endif
  630. pr_info("%s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
  631. pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
  632. /* Allocate IRQ */
  633. if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) {
  634. pr_warn("%s: could not allocate IRQ%i\n",
  635. pci_name(pdev), pdev->irq);
  636. wanxl_pci_remove_one(pdev);
  637. return -EBUSY;
  638. }
  639. card->irq = pdev->irq;
  640. for (i = 0; i < ports; i++) {
  641. hdlc_device *hdlc;
  642. struct port *port = &card->ports[i];
  643. struct net_device *dev = alloc_hdlcdev(port);
  644. if (!dev) {
  645. pr_err("%s: unable to allocate memory\n",
  646. pci_name(pdev));
  647. wanxl_pci_remove_one(pdev);
  648. return -ENOMEM;
  649. }
  650. port->dev = dev;
  651. hdlc = dev_to_hdlc(dev);
  652. spin_lock_init(&port->lock);
  653. dev->tx_queue_len = 50;
  654. dev->netdev_ops = &wanxl_ops;
  655. hdlc->attach = wanxl_attach;
  656. hdlc->xmit = wanxl_xmit;
  657. port->card = card;
  658. port->node = i;
  659. get_status(port)->clocking = CLOCK_EXT;
  660. if (register_hdlc_device(dev)) {
  661. pr_err("%s: unable to register hdlc device\n",
  662. pci_name(pdev));
  663. free_netdev(dev);
  664. wanxl_pci_remove_one(pdev);
  665. return -ENOBUFS;
  666. }
  667. card->n_ports++;
  668. }
  669. pr_info("%s: port", pci_name(pdev));
  670. for (i = 0; i < ports; i++)
  671. pr_cont("%s #%i: %s",
  672. i ? "," : "", i, card->ports[i].dev->name);
  673. pr_cont("\n");
  674. for (i = 0; i < ports; i++)
  675. wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
  676. return 0;
  677. }
  678. static const struct pci_device_id wanxl_pci_tbl[] = {
  679. { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
  680. PCI_ANY_ID, 0, 0, 0 },
  681. { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
  682. PCI_ANY_ID, 0, 0, 0 },
  683. { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
  684. PCI_ANY_ID, 0, 0, 0 },
  685. { 0, }
  686. };
  687. static struct pci_driver wanxl_pci_driver = {
  688. .name = "wanXL",
  689. .id_table = wanxl_pci_tbl,
  690. .probe = wanxl_pci_init_one,
  691. .remove = wanxl_pci_remove_one,
  692. };
  693. static int __init wanxl_init_module(void)
  694. {
  695. #ifdef MODULE
  696. pr_info("%s\n", version);
  697. #endif
  698. return pci_register_driver(&wanxl_pci_driver);
  699. }
  700. static void __exit wanxl_cleanup_module(void)
  701. {
  702. pci_unregister_driver(&wanxl_pci_driver);
  703. }
  704. MODULE_AUTHOR("Krzysztof Halasa <[email protected]>");
  705. MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
  706. MODULE_LICENSE("GPL v2");
  707. MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
  708. module_init(wanxl_init_module);
  709. module_exit(wanxl_cleanup_module);