r8152.c 237 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  4. */
  5. #include <linux/signal.h>
  6. #include <linux/slab.h>
  7. #include <linux/module.h>
  8. #include <linux/netdevice.h>
  9. #include <linux/etherdevice.h>
  10. #include <linux/mii.h>
  11. #include <linux/ethtool.h>
  12. #include <linux/usb.h>
  13. #include <linux/crc32.h>
  14. #include <linux/if_vlan.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/list.h>
  17. #include <linux/ip.h>
  18. #include <linux/ipv6.h>
  19. #include <net/ip6_checksum.h>
  20. #include <uapi/linux/mdio.h>
  21. #include <linux/mdio.h>
  22. #include <linux/usb/cdc.h>
  23. #include <linux/suspend.h>
  24. #include <linux/atomic.h>
  25. #include <linux/acpi.h>
  26. #include <linux/firmware.h>
  27. #include <crypto/hash.h>
  28. #include <linux/usb/r8152.h>
  29. /* Information for net-next */
  30. #define NETNEXT_VERSION "12"
  31. /* Information for net */
  32. #define NET_VERSION "13"
  33. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  34. #define DRIVER_AUTHOR "Realtek linux nic maintainers <[email protected]>"
  35. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  36. #define MODULENAME "r8152"
  37. #define R8152_PHY_ID 32
  38. #define PLA_IDR 0xc000
  39. #define PLA_RCR 0xc010
  40. #define PLA_RCR1 0xc012
  41. #define PLA_RMS 0xc016
  42. #define PLA_RXFIFO_CTRL0 0xc0a0
  43. #define PLA_RXFIFO_FULL 0xc0a2
  44. #define PLA_RXFIFO_CTRL1 0xc0a4
  45. #define PLA_RX_FIFO_FULL 0xc0a6
  46. #define PLA_RXFIFO_CTRL2 0xc0a8
  47. #define PLA_RX_FIFO_EMPTY 0xc0aa
  48. #define PLA_DMY_REG0 0xc0b0
  49. #define PLA_FMC 0xc0b4
  50. #define PLA_CFG_WOL 0xc0b6
  51. #define PLA_TEREDO_CFG 0xc0bc
  52. #define PLA_TEREDO_WAKE_BASE 0xc0c4
  53. #define PLA_MAR 0xcd00
  54. #define PLA_BACKUP 0xd000
  55. #define PLA_BDC_CR 0xd1a0
  56. #define PLA_TEREDO_TIMER 0xd2cc
  57. #define PLA_REALWOW_TIMER 0xd2e8
  58. #define PLA_UPHY_TIMER 0xd388
  59. #define PLA_SUSPEND_FLAG 0xd38a
  60. #define PLA_INDICATE_FALG 0xd38c
  61. #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
  62. #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
  63. #define PLA_EXTRA_STATUS 0xd398
  64. #define PLA_GPHY_CTRL 0xd3ae
  65. #define PLA_POL_GPIO_CTRL 0xdc6a
  66. #define PLA_EFUSE_DATA 0xdd00
  67. #define PLA_EFUSE_CMD 0xdd02
  68. #define PLA_LEDSEL 0xdd90
  69. #define PLA_LED_FEATURE 0xdd92
  70. #define PLA_PHYAR 0xde00
  71. #define PLA_BOOT_CTRL 0xe004
  72. #define PLA_LWAKE_CTRL_REG 0xe007
  73. #define PLA_GPHY_INTR_IMR 0xe022
  74. #define PLA_EEE_CR 0xe040
  75. #define PLA_EEE_TXTWSYS 0xe04c
  76. #define PLA_EEE_TXTWSYS_2P5G 0xe058
  77. #define PLA_EEEP_CR 0xe080
  78. #define PLA_MAC_PWR_CTRL 0xe0c0
  79. #define PLA_MAC_PWR_CTRL2 0xe0ca
  80. #define PLA_MAC_PWR_CTRL3 0xe0cc
  81. #define PLA_MAC_PWR_CTRL4 0xe0ce
  82. #define PLA_WDT6_CTRL 0xe428
  83. #define PLA_TCR0 0xe610
  84. #define PLA_TCR1 0xe612
  85. #define PLA_MTPS 0xe615
  86. #define PLA_TXFIFO_CTRL 0xe618
  87. #define PLA_TXFIFO_FULL 0xe61a
  88. #define PLA_RSTTALLY 0xe800
  89. #define PLA_CR 0xe813
  90. #define PLA_CRWECR 0xe81c
  91. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  92. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  93. #define PLA_CONFIG5 0xe822
  94. #define PLA_PHY_PWR 0xe84c
  95. #define PLA_OOB_CTRL 0xe84f
  96. #define PLA_CPCR 0xe854
  97. #define PLA_MISC_0 0xe858
  98. #define PLA_MISC_1 0xe85a
  99. #define PLA_OCP_GPHY_BASE 0xe86c
  100. #define PLA_TALLYCNT 0xe890
  101. #define PLA_SFF_STS_7 0xe8de
  102. #define PLA_PHYSTATUS 0xe908
  103. #define PLA_CONFIG6 0xe90a /* CONFIG6 */
  104. #define PLA_USB_CFG 0xe952
  105. #define PLA_BP_BA 0xfc26
  106. #define PLA_BP_0 0xfc28
  107. #define PLA_BP_1 0xfc2a
  108. #define PLA_BP_2 0xfc2c
  109. #define PLA_BP_3 0xfc2e
  110. #define PLA_BP_4 0xfc30
  111. #define PLA_BP_5 0xfc32
  112. #define PLA_BP_6 0xfc34
  113. #define PLA_BP_7 0xfc36
  114. #define PLA_BP_EN 0xfc38
  115. #define USB_USB2PHY 0xb41e
  116. #define USB_SSPHYLINK1 0xb426
  117. #define USB_SSPHYLINK2 0xb428
  118. #define USB_L1_CTRL 0xb45e
  119. #define USB_U2P3_CTRL 0xb460
  120. #define USB_CSR_DUMMY1 0xb464
  121. #define USB_CSR_DUMMY2 0xb466
  122. #define USB_DEV_STAT 0xb808
  123. #define USB_CONNECT_TIMER 0xcbf8
  124. #define USB_MSC_TIMER 0xcbfc
  125. #define USB_BURST_SIZE 0xcfc0
  126. #define USB_FW_FIX_EN0 0xcfca
  127. #define USB_FW_FIX_EN1 0xcfcc
  128. #define USB_LPM_CONFIG 0xcfd8
  129. #define USB_ECM_OPTION 0xcfee
  130. #define USB_CSTMR 0xcfef /* RTL8153A */
  131. #define USB_MISC_2 0xcfff
  132. #define USB_ECM_OP 0xd26b
  133. #define USB_GPHY_CTRL 0xd284
  134. #define USB_SPEED_OPTION 0xd32a
  135. #define USB_FW_CTRL 0xd334 /* RTL8153B */
  136. #define USB_FC_TIMER 0xd340
  137. #define USB_USB_CTRL 0xd406
  138. #define USB_PHY_CTRL 0xd408
  139. #define USB_TX_AGG 0xd40a
  140. #define USB_RX_BUF_TH 0xd40c
  141. #define USB_USB_TIMER 0xd428
  142. #define USB_RX_EARLY_TIMEOUT 0xd42c
  143. #define USB_RX_EARLY_SIZE 0xd42e
  144. #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
  145. #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
  146. #define USB_TX_DMA 0xd434
  147. #define USB_UPT_RXDMA_OWN 0xd437
  148. #define USB_UPHY3_MDCMDIO 0xd480
  149. #define USB_TOLERANCE 0xd490
  150. #define USB_LPM_CTRL 0xd41a
  151. #define USB_BMU_RESET 0xd4b0
  152. #define USB_BMU_CONFIG 0xd4b4
  153. #define USB_U1U2_TIMER 0xd4da
  154. #define USB_FW_TASK 0xd4e8 /* RTL8153B */
  155. #define USB_RX_AGGR_NUM 0xd4ee
  156. #define USB_UPS_CTRL 0xd800
  157. #define USB_POWER_CUT 0xd80a
  158. #define USB_MISC_0 0xd81a
  159. #define USB_MISC_1 0xd81f
  160. #define USB_AFE_CTRL2 0xd824
  161. #define USB_UPHY_XTAL 0xd826
  162. #define USB_UPS_CFG 0xd842
  163. #define USB_UPS_FLAGS 0xd848
  164. #define USB_WDT1_CTRL 0xe404
  165. #define USB_WDT11_CTRL 0xe43c
  166. #define USB_BP_BA PLA_BP_BA
  167. #define USB_BP_0 PLA_BP_0
  168. #define USB_BP_1 PLA_BP_1
  169. #define USB_BP_2 PLA_BP_2
  170. #define USB_BP_3 PLA_BP_3
  171. #define USB_BP_4 PLA_BP_4
  172. #define USB_BP_5 PLA_BP_5
  173. #define USB_BP_6 PLA_BP_6
  174. #define USB_BP_7 PLA_BP_7
  175. #define USB_BP_EN PLA_BP_EN /* RTL8153A */
  176. #define USB_BP_8 0xfc38 /* RTL8153B */
  177. #define USB_BP_9 0xfc3a
  178. #define USB_BP_10 0xfc3c
  179. #define USB_BP_11 0xfc3e
  180. #define USB_BP_12 0xfc40
  181. #define USB_BP_13 0xfc42
  182. #define USB_BP_14 0xfc44
  183. #define USB_BP_15 0xfc46
  184. #define USB_BP2_EN 0xfc48
  185. /* OCP Registers */
  186. #define OCP_ALDPS_CONFIG 0x2010
  187. #define OCP_EEE_CONFIG1 0x2080
  188. #define OCP_EEE_CONFIG2 0x2092
  189. #define OCP_EEE_CONFIG3 0x2094
  190. #define OCP_BASE_MII 0xa400
  191. #define OCP_EEE_AR 0xa41a
  192. #define OCP_EEE_DATA 0xa41c
  193. #define OCP_PHY_STATUS 0xa420
  194. #define OCP_INTR_EN 0xa424
  195. #define OCP_NCTL_CFG 0xa42c
  196. #define OCP_POWER_CFG 0xa430
  197. #define OCP_EEE_CFG 0xa432
  198. #define OCP_SRAM_ADDR 0xa436
  199. #define OCP_SRAM_DATA 0xa438
  200. #define OCP_DOWN_SPEED 0xa442
  201. #define OCP_EEE_ABLE 0xa5c4
  202. #define OCP_EEE_ADV 0xa5d0
  203. #define OCP_EEE_LPABLE 0xa5d2
  204. #define OCP_10GBT_CTRL 0xa5d4
  205. #define OCP_10GBT_STAT 0xa5d6
  206. #define OCP_EEE_ADV2 0xa6d4
  207. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  208. #define OCP_PHY_PATCH_STAT 0xb800
  209. #define OCP_PHY_PATCH_CMD 0xb820
  210. #define OCP_PHY_LOCK 0xb82e
  211. #define OCP_ADC_IOFFSET 0xbcfc
  212. #define OCP_ADC_CFG 0xbc06
  213. #define OCP_SYSCLK_CFG 0xc416
  214. /* SRAM Register */
  215. #define SRAM_GREEN_CFG 0x8011
  216. #define SRAM_LPF_CFG 0x8012
  217. #define SRAM_GPHY_FW_VER 0x801e
  218. #define SRAM_10M_AMP1 0x8080
  219. #define SRAM_10M_AMP2 0x8082
  220. #define SRAM_IMPEDANCE 0x8084
  221. #define SRAM_PHY_LOCK 0xb82e
  222. /* PLA_RCR */
  223. #define RCR_AAP 0x00000001
  224. #define RCR_APM 0x00000002
  225. #define RCR_AM 0x00000004
  226. #define RCR_AB 0x00000008
  227. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  228. #define SLOT_EN BIT(11)
  229. /* PLA_RCR1 */
  230. #define OUTER_VLAN BIT(7)
  231. #define INNER_VLAN BIT(6)
  232. /* PLA_RXFIFO_CTRL0 */
  233. #define RXFIFO_THR1_NORMAL 0x00080002
  234. #define RXFIFO_THR1_OOB 0x01800003
  235. /* PLA_RXFIFO_FULL */
  236. #define RXFIFO_FULL_MASK 0xfff
  237. /* PLA_RXFIFO_CTRL1 */
  238. #define RXFIFO_THR2_FULL 0x00000060
  239. #define RXFIFO_THR2_HIGH 0x00000038
  240. #define RXFIFO_THR2_OOB 0x0000004a
  241. #define RXFIFO_THR2_NORMAL 0x00a0
  242. /* PLA_RXFIFO_CTRL2 */
  243. #define RXFIFO_THR3_FULL 0x00000078
  244. #define RXFIFO_THR3_HIGH 0x00000048
  245. #define RXFIFO_THR3_OOB 0x0000005a
  246. #define RXFIFO_THR3_NORMAL 0x0110
  247. /* PLA_TXFIFO_CTRL */
  248. #define TXFIFO_THR_NORMAL 0x00400008
  249. #define TXFIFO_THR_NORMAL2 0x01000008
  250. /* PLA_DMY_REG0 */
  251. #define ECM_ALDPS 0x0002
  252. /* PLA_FMC */
  253. #define FMC_FCR_MCU_EN 0x0001
  254. /* PLA_EEEP_CR */
  255. #define EEEP_CR_EEEP_TX 0x0002
  256. /* PLA_WDT6_CTRL */
  257. #define WDT6_SET_MODE 0x0010
  258. /* PLA_TCR0 */
  259. #define TCR0_TX_EMPTY 0x0800
  260. #define TCR0_AUTO_FIFO 0x0080
  261. /* PLA_TCR1 */
  262. #define VERSION_MASK 0x7cf0
  263. #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
  264. #define IFG_144NS BIT(9)
  265. #define IFG_96NS (BIT(9) | BIT(8))
  266. /* PLA_MTPS */
  267. #define MTPS_JUMBO (12 * 1024 / 64)
  268. #define MTPS_DEFAULT (6 * 1024 / 64)
  269. /* PLA_RSTTALLY */
  270. #define TALLY_RESET 0x0001
  271. /* PLA_CR */
  272. #define CR_RST 0x10
  273. #define CR_RE 0x08
  274. #define CR_TE 0x04
  275. /* PLA_CRWECR */
  276. #define CRWECR_NORAML 0x00
  277. #define CRWECR_CONFIG 0xc0
  278. /* PLA_OOB_CTRL */
  279. #define NOW_IS_OOB 0x80
  280. #define TXFIFO_EMPTY 0x20
  281. #define RXFIFO_EMPTY 0x10
  282. #define LINK_LIST_READY 0x02
  283. #define DIS_MCU_CLROOB 0x01
  284. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  285. /* PLA_MISC_1 */
  286. #define RXDY_GATED_EN 0x0008
  287. /* PLA_SFF_STS_7 */
  288. #define RE_INIT_LL 0x8000
  289. #define MCU_BORW_EN 0x4000
  290. /* PLA_CPCR */
  291. #define FLOW_CTRL_EN BIT(0)
  292. #define CPCR_RX_VLAN 0x0040
  293. /* PLA_CFG_WOL */
  294. #define MAGIC_EN 0x0001
  295. /* PLA_TEREDO_CFG */
  296. #define TEREDO_SEL 0x8000
  297. #define TEREDO_WAKE_MASK 0x7f00
  298. #define TEREDO_RS_EVENT_MASK 0x00fe
  299. #define OOB_TEREDO_EN 0x0001
  300. /* PLA_BDC_CR */
  301. #define ALDPS_PROXY_MODE 0x0001
  302. /* PLA_EFUSE_CMD */
  303. #define EFUSE_READ_CMD BIT(15)
  304. #define EFUSE_DATA_BIT16 BIT(7)
  305. /* PLA_CONFIG34 */
  306. #define LINK_ON_WAKE_EN 0x0010
  307. #define LINK_OFF_WAKE_EN 0x0008
  308. /* PLA_CONFIG6 */
  309. #define LANWAKE_CLR_EN BIT(0)
  310. /* PLA_USB_CFG */
  311. #define EN_XG_LIP BIT(1)
  312. #define EN_G_LIP BIT(2)
  313. /* PLA_CONFIG5 */
  314. #define BWF_EN 0x0040
  315. #define MWF_EN 0x0020
  316. #define UWF_EN 0x0010
  317. #define LAN_WAKE_EN 0x0002
  318. /* PLA_LED_FEATURE */
  319. #define LED_MODE_MASK 0x0700
  320. /* PLA_PHY_PWR */
  321. #define TX_10M_IDLE_EN 0x0080
  322. #define PFM_PWM_SWITCH 0x0040
  323. #define TEST_IO_OFF BIT(4)
  324. /* PLA_MAC_PWR_CTRL */
  325. #define D3_CLK_GATED_EN 0x00004000
  326. #define MCU_CLK_RATIO 0x07010f07
  327. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  328. #define ALDPS_SPDWN_RATIO 0x0f87
  329. /* PLA_MAC_PWR_CTRL2 */
  330. #define EEE_SPDWN_RATIO 0x8007
  331. #define MAC_CLK_SPDWN_EN BIT(15)
  332. #define EEE_SPDWN_RATIO_MASK 0xff
  333. /* PLA_MAC_PWR_CTRL3 */
  334. #define PLA_MCU_SPDWN_EN BIT(14)
  335. #define PKT_AVAIL_SPDWN_EN 0x0100
  336. #define SUSPEND_SPDWN_EN 0x0004
  337. #define U1U2_SPDWN_EN 0x0002
  338. #define L1_SPDWN_EN 0x0001
  339. /* PLA_MAC_PWR_CTRL4 */
  340. #define PWRSAVE_SPDWN_EN 0x1000
  341. #define RXDV_SPDWN_EN 0x0800
  342. #define TX10MIDLE_EN 0x0100
  343. #define IDLE_SPDWN_EN BIT(6)
  344. #define TP100_SPDWN_EN 0x0020
  345. #define TP500_SPDWN_EN 0x0010
  346. #define TP1000_SPDWN_EN 0x0008
  347. #define EEE_SPDWN_EN 0x0001
  348. /* PLA_GPHY_INTR_IMR */
  349. #define GPHY_STS_MSK 0x0001
  350. #define SPEED_DOWN_MSK 0x0002
  351. #define SPDWN_RXDV_MSK 0x0004
  352. #define SPDWN_LINKCHG_MSK 0x0008
  353. /* PLA_PHYAR */
  354. #define PHYAR_FLAG 0x80000000
  355. /* PLA_EEE_CR */
  356. #define EEE_RX_EN 0x0001
  357. #define EEE_TX_EN 0x0002
  358. /* PLA_BOOT_CTRL */
  359. #define AUTOLOAD_DONE 0x0002
  360. /* PLA_LWAKE_CTRL_REG */
  361. #define LANWAKE_PIN BIT(7)
  362. /* PLA_SUSPEND_FLAG */
  363. #define LINK_CHG_EVENT BIT(0)
  364. /* PLA_INDICATE_FALG */
  365. #define UPCOMING_RUNTIME_D3 BIT(0)
  366. /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
  367. #define DEBUG_OE BIT(0)
  368. #define DEBUG_LTSSM 0x0082
  369. /* PLA_EXTRA_STATUS */
  370. #define CUR_LINK_OK BIT(15)
  371. #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
  372. #define LINK_CHANGE_FLAG BIT(8)
  373. #define POLL_LINK_CHG BIT(0)
  374. /* PLA_GPHY_CTRL */
  375. #define GPHY_FLASH BIT(1)
  376. /* PLA_POL_GPIO_CTRL */
  377. #define DACK_DET_EN BIT(15)
  378. #define POL_GPHY_PATCH BIT(4)
  379. /* USB_USB2PHY */
  380. #define USB2PHY_SUSPEND 0x0001
  381. #define USB2PHY_L1 0x0002
  382. /* USB_SSPHYLINK1 */
  383. #define DELAY_PHY_PWR_CHG BIT(1)
  384. /* USB_SSPHYLINK2 */
  385. #define pwd_dn_scale_mask 0x3ffe
  386. #define pwd_dn_scale(x) ((x) << 1)
  387. /* USB_CSR_DUMMY1 */
  388. #define DYNAMIC_BURST 0x0001
  389. /* USB_CSR_DUMMY2 */
  390. #define EP4_FULL_FC 0x0001
  391. /* USB_DEV_STAT */
  392. #define STAT_SPEED_MASK 0x0006
  393. #define STAT_SPEED_HIGH 0x0000
  394. #define STAT_SPEED_FULL 0x0002
  395. /* USB_FW_FIX_EN0 */
  396. #define FW_FIX_SUSPEND BIT(14)
  397. /* USB_FW_FIX_EN1 */
  398. #define FW_IP_RESET_EN BIT(9)
  399. /* USB_LPM_CONFIG */
  400. #define LPM_U1U2_EN BIT(0)
  401. /* USB_TX_AGG */
  402. #define TX_AGG_MAX_THRESHOLD 0x03
  403. /* USB_RX_BUF_TH */
  404. #define RX_THR_SUPPER 0x0c350180
  405. #define RX_THR_HIGH 0x7a120180
  406. #define RX_THR_SLOW 0xffff0180
  407. #define RX_THR_B 0x00010001
  408. /* USB_TX_DMA */
  409. #define TEST_MODE_DISABLE 0x00000001
  410. #define TX_SIZE_ADJUST1 0x00000100
  411. /* USB_BMU_RESET */
  412. #define BMU_RESET_EP_IN 0x01
  413. #define BMU_RESET_EP_OUT 0x02
  414. /* USB_BMU_CONFIG */
  415. #define ACT_ODMA BIT(1)
  416. /* USB_UPT_RXDMA_OWN */
  417. #define OWN_UPDATE BIT(0)
  418. #define OWN_CLEAR BIT(1)
  419. /* USB_FW_TASK */
  420. #define FC_PATCH_TASK BIT(1)
  421. /* USB_RX_AGGR_NUM */
  422. #define RX_AGGR_NUM_MASK 0x1ff
  423. /* USB_UPS_CTRL */
  424. #define POWER_CUT 0x0100
  425. /* USB_PM_CTRL_STATUS */
  426. #define RESUME_INDICATE 0x0001
  427. /* USB_ECM_OPTION */
  428. #define BYPASS_MAC_RESET BIT(5)
  429. /* USB_CSTMR */
  430. #define FORCE_SUPER BIT(0)
  431. /* USB_MISC_2 */
  432. #define UPS_FORCE_PWR_DOWN BIT(0)
  433. /* USB_ECM_OP */
  434. #define EN_ALL_SPEED BIT(0)
  435. /* USB_GPHY_CTRL */
  436. #define GPHY_PATCH_DONE BIT(2)
  437. #define BYPASS_FLASH BIT(5)
  438. #define BACKUP_RESTRORE BIT(6)
  439. /* USB_SPEED_OPTION */
  440. #define RG_PWRDN_EN BIT(8)
  441. #define ALL_SPEED_OFF BIT(9)
  442. /* USB_FW_CTRL */
  443. #define FLOW_CTRL_PATCH_OPT BIT(1)
  444. #define AUTO_SPEEDUP BIT(3)
  445. #define FLOW_CTRL_PATCH_2 BIT(8)
  446. /* USB_FC_TIMER */
  447. #define CTRL_TIMER_EN BIT(15)
  448. /* USB_USB_CTRL */
  449. #define CDC_ECM_EN BIT(3)
  450. #define RX_AGG_DISABLE 0x0010
  451. #define RX_ZERO_EN 0x0080
  452. /* USB_U2P3_CTRL */
  453. #define U2P3_ENABLE 0x0001
  454. #define RX_DETECT8 BIT(3)
  455. /* USB_POWER_CUT */
  456. #define PWR_EN 0x0001
  457. #define PHASE2_EN 0x0008
  458. #define UPS_EN BIT(4)
  459. #define USP_PREWAKE BIT(5)
  460. /* USB_MISC_0 */
  461. #define PCUT_STATUS 0x0001
  462. /* USB_RX_EARLY_TIMEOUT */
  463. #define COALESCE_SUPER 85000U
  464. #define COALESCE_HIGH 250000U
  465. #define COALESCE_SLOW 524280U
  466. /* USB_WDT1_CTRL */
  467. #define WTD1_EN BIT(0)
  468. /* USB_WDT11_CTRL */
  469. #define TIMER11_EN 0x0001
  470. /* USB_LPM_CTRL */
  471. /* bit 4 ~ 5: fifo empty boundary */
  472. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  473. /* bit 2 ~ 3: LMP timer */
  474. #define LPM_TIMER_MASK 0x0c
  475. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  476. #define LPM_TIMER_500US 0x0c /* 500 us */
  477. #define ROK_EXIT_LPM 0x02
  478. /* USB_AFE_CTRL2 */
  479. #define SEN_VAL_MASK 0xf800
  480. #define SEN_VAL_NORMAL 0xa000
  481. #define SEL_RXIDLE 0x0100
  482. /* USB_UPHY_XTAL */
  483. #define OOBS_POLLING BIT(8)
  484. /* USB_UPS_CFG */
  485. #define SAW_CNT_1MS_MASK 0x0fff
  486. #define MID_REVERSE BIT(5) /* RTL8156A */
  487. /* USB_UPS_FLAGS */
  488. #define UPS_FLAGS_R_TUNE BIT(0)
  489. #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
  490. #define UPS_FLAGS_250M_CKDIV BIT(2)
  491. #define UPS_FLAGS_EN_ALDPS BIT(3)
  492. #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
  493. #define UPS_FLAGS_SPEED_MASK (0xf << 16)
  494. #define ups_flags_speed(x) ((x) << 16)
  495. #define UPS_FLAGS_EN_EEE BIT(20)
  496. #define UPS_FLAGS_EN_500M_EEE BIT(21)
  497. #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
  498. #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
  499. #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
  500. #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
  501. #define UPS_FLAGS_EN_GREEN BIT(26)
  502. #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
  503. enum spd_duplex {
  504. NWAY_10M_HALF,
  505. NWAY_10M_FULL,
  506. NWAY_100M_HALF,
  507. NWAY_100M_FULL,
  508. NWAY_1000M_FULL,
  509. FORCE_10M_HALF,
  510. FORCE_10M_FULL,
  511. FORCE_100M_HALF,
  512. FORCE_100M_FULL,
  513. FORCE_1000M_FULL,
  514. NWAY_2500M_FULL,
  515. };
  516. /* OCP_ALDPS_CONFIG */
  517. #define ENPWRSAVE 0x8000
  518. #define ENPDNPS 0x0200
  519. #define LINKENA 0x0100
  520. #define DIS_SDSAVE 0x0010
  521. /* OCP_PHY_STATUS */
  522. #define PHY_STAT_MASK 0x0007
  523. #define PHY_STAT_EXT_INIT 2
  524. #define PHY_STAT_LAN_ON 3
  525. #define PHY_STAT_PWRDN 5
  526. /* OCP_INTR_EN */
  527. #define INTR_SPEED_FORCE BIT(3)
  528. /* OCP_NCTL_CFG */
  529. #define PGA_RETURN_EN BIT(1)
  530. /* OCP_POWER_CFG */
  531. #define EEE_CLKDIV_EN 0x8000
  532. #define EN_ALDPS 0x0004
  533. #define EN_10M_PLLOFF 0x0001
  534. /* OCP_EEE_CONFIG1 */
  535. #define RG_TXLPI_MSK_HFDUP 0x8000
  536. #define RG_MATCLR_EN 0x4000
  537. #define EEE_10_CAP 0x2000
  538. #define EEE_NWAY_EN 0x1000
  539. #define TX_QUIET_EN 0x0200
  540. #define RX_QUIET_EN 0x0100
  541. #define sd_rise_time_mask 0x0070
  542. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  543. #define RG_RXLPI_MSK_HFDUP 0x0008
  544. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  545. /* OCP_EEE_CONFIG2 */
  546. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  547. #define RG_DACQUIET_EN 0x0400
  548. #define RG_LDVQUIET_EN 0x0200
  549. #define RG_CKRSEL 0x0020
  550. #define RG_EEEPRG_EN 0x0010
  551. /* OCP_EEE_CONFIG3 */
  552. #define fast_snr_mask 0xff80
  553. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  554. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  555. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  556. /* OCP_EEE_AR */
  557. /* bit[15:14] function */
  558. #define FUN_ADDR 0x0000
  559. #define FUN_DATA 0x4000
  560. /* bit[4:0] device addr */
  561. /* OCP_EEE_CFG */
  562. #define CTAP_SHORT_EN 0x0040
  563. #define EEE10_EN 0x0010
  564. /* OCP_DOWN_SPEED */
  565. #define EN_EEE_CMODE BIT(14)
  566. #define EN_EEE_1000 BIT(13)
  567. #define EN_EEE_100 BIT(12)
  568. #define EN_10M_CLKDIV BIT(11)
  569. #define EN_10M_BGOFF 0x0080
  570. /* OCP_10GBT_CTRL */
  571. #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
  572. /* OCP_PHY_STATE */
  573. #define TXDIS_STATE 0x01
  574. #define ABD_STATE 0x02
  575. /* OCP_PHY_PATCH_STAT */
  576. #define PATCH_READY BIT(6)
  577. /* OCP_PHY_PATCH_CMD */
  578. #define PATCH_REQUEST BIT(4)
  579. /* OCP_PHY_LOCK */
  580. #define PATCH_LOCK BIT(0)
  581. /* OCP_ADC_CFG */
  582. #define CKADSEL_L 0x0100
  583. #define ADC_EN 0x0080
  584. #define EN_EMI_L 0x0040
  585. /* OCP_SYSCLK_CFG */
  586. #define sysclk_div_expo(x) (min(x, 5) << 8)
  587. #define clk_div_expo(x) (min(x, 5) << 4)
  588. /* SRAM_GREEN_CFG */
  589. #define GREEN_ETH_EN BIT(15)
  590. #define R_TUNE_EN BIT(11)
  591. /* SRAM_LPF_CFG */
  592. #define LPF_AUTO_TUNE 0x8000
  593. /* SRAM_10M_AMP1 */
  594. #define GDAC_IB_UPALL 0x0008
  595. /* SRAM_10M_AMP2 */
  596. #define AMP_DN 0x0200
  597. /* SRAM_IMPEDANCE */
  598. #define RX_DRIVING_MASK 0x6000
  599. /* SRAM_PHY_LOCK */
  600. #define PHY_PATCH_LOCK 0x0001
  601. /* MAC PASSTHRU */
  602. #define AD_MASK 0xfee0
  603. #define BND_MASK 0x0004
  604. #define BD_MASK 0x0001
  605. #define EFUSE 0xcfdb
  606. #define PASS_THRU_MASK 0x1
  607. #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
  608. enum rtl_register_content {
  609. _2500bps = BIT(10),
  610. _1250bps = BIT(9),
  611. _500bps = BIT(8),
  612. _tx_flow = BIT(6),
  613. _rx_flow = BIT(5),
  614. _1000bps = 0x10,
  615. _100bps = 0x08,
  616. _10bps = 0x04,
  617. LINK_STATUS = 0x02,
  618. FULL_DUP = 0x01,
  619. };
  620. #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
  621. #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
  622. #define RTL8152_MAX_TX 4
  623. #define RTL8152_MAX_RX 10
  624. #define INTBUFSIZE 2
  625. #define TX_ALIGN 4
  626. #define RX_ALIGN 8
  627. #define RTL8152_RX_MAX_PENDING 4096
  628. #define RTL8152_RXFG_HEADSZ 256
  629. #define INTR_LINK 0x0004
  630. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
  631. #define RTL8153_RMS RTL8153_MAX_PACKET
  632. #define RTL8152_TX_TIMEOUT (5 * HZ)
  633. #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
  634. #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
  635. #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
  636. /* rtl8152 flags */
  637. enum rtl8152_flags {
  638. RTL8152_INACCESSIBLE = 0,
  639. RTL8152_SET_RX_MODE,
  640. WORK_ENABLE,
  641. RTL8152_LINK_CHG,
  642. SELECTIVE_SUSPEND,
  643. PHY_RESET,
  644. SCHEDULE_TASKLET,
  645. GREEN_ETHERNET,
  646. RX_EPROTO,
  647. };
  648. #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
  649. #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
  650. #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
  651. #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
  652. #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
  653. #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
  654. struct tally_counter {
  655. __le64 tx_packets;
  656. __le64 rx_packets;
  657. __le64 tx_errors;
  658. __le32 rx_errors;
  659. __le16 rx_missed;
  660. __le16 align_errors;
  661. __le32 tx_one_collision;
  662. __le32 tx_multi_collision;
  663. __le64 rx_unicast;
  664. __le64 rx_broadcast;
  665. __le32 rx_multicast;
  666. __le16 tx_aborted;
  667. __le16 tx_underrun;
  668. };
  669. struct rx_desc {
  670. __le32 opts1;
  671. #define RX_LEN_MASK 0x7fff
  672. __le32 opts2;
  673. #define RD_UDP_CS BIT(23)
  674. #define RD_TCP_CS BIT(22)
  675. #define RD_IPV6_CS BIT(20)
  676. #define RD_IPV4_CS BIT(19)
  677. __le32 opts3;
  678. #define IPF BIT(23) /* IP checksum fail */
  679. #define UDPF BIT(22) /* UDP checksum fail */
  680. #define TCPF BIT(21) /* TCP checksum fail */
  681. #define RX_VLAN_TAG BIT(16)
  682. __le32 opts4;
  683. __le32 opts5;
  684. __le32 opts6;
  685. };
  686. struct tx_desc {
  687. __le32 opts1;
  688. #define TX_FS BIT(31) /* First segment of a packet */
  689. #define TX_LS BIT(30) /* Final segment of a packet */
  690. #define GTSENDV4 BIT(28)
  691. #define GTSENDV6 BIT(27)
  692. #define GTTCPHO_SHIFT 18
  693. #define GTTCPHO_MAX 0x7fU
  694. #define TX_LEN_MAX 0x3ffffU
  695. __le32 opts2;
  696. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  697. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  698. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  699. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  700. #define MSS_SHIFT 17
  701. #define MSS_MAX 0x7ffU
  702. #define TCPHO_SHIFT 17
  703. #define TCPHO_MAX 0x7ffU
  704. #define TX_VLAN_TAG BIT(16)
  705. };
  706. struct r8152;
  707. struct rx_agg {
  708. struct list_head list, info_list;
  709. struct urb *urb;
  710. struct r8152 *context;
  711. struct page *page;
  712. void *buffer;
  713. };
  714. struct tx_agg {
  715. struct list_head list;
  716. struct urb *urb;
  717. struct r8152 *context;
  718. void *buffer;
  719. void *head;
  720. u32 skb_num;
  721. u32 skb_len;
  722. };
  723. struct r8152 {
  724. unsigned long flags;
  725. struct usb_device *udev;
  726. struct napi_struct napi;
  727. struct usb_interface *intf;
  728. struct net_device *netdev;
  729. struct urb *intr_urb;
  730. struct tx_agg tx_info[RTL8152_MAX_TX];
  731. struct list_head rx_info, rx_used;
  732. struct list_head rx_done, tx_free;
  733. struct sk_buff_head tx_queue, rx_queue;
  734. spinlock_t rx_lock, tx_lock;
  735. struct delayed_work schedule, hw_phy_work;
  736. struct mii_if_info mii;
  737. struct mutex control; /* use for hw setting */
  738. #ifdef CONFIG_PM_SLEEP
  739. struct notifier_block pm_notifier;
  740. #endif
  741. struct tasklet_struct tx_tl;
  742. struct rtl_ops {
  743. void (*init)(struct r8152 *tp);
  744. int (*enable)(struct r8152 *tp);
  745. void (*disable)(struct r8152 *tp);
  746. void (*up)(struct r8152 *tp);
  747. void (*down)(struct r8152 *tp);
  748. void (*unload)(struct r8152 *tp);
  749. int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
  750. int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
  751. bool (*in_nway)(struct r8152 *tp);
  752. void (*hw_phy_cfg)(struct r8152 *tp);
  753. void (*autosuspend_en)(struct r8152 *tp, bool enable);
  754. void (*change_mtu)(struct r8152 *tp);
  755. } rtl_ops;
  756. struct ups_info {
  757. u32 r_tune:1;
  758. u32 _10m_ckdiv:1;
  759. u32 _250m_ckdiv:1;
  760. u32 aldps:1;
  761. u32 lite_mode:2;
  762. u32 speed_duplex:4;
  763. u32 eee:1;
  764. u32 eee_lite:1;
  765. u32 eee_ckdiv:1;
  766. u32 eee_plloff_100:1;
  767. u32 eee_plloff_giga:1;
  768. u32 eee_cmod_lv:1;
  769. u32 green:1;
  770. u32 flow_control:1;
  771. u32 ctap_short_off:1;
  772. } ups_info;
  773. #define RTL_VER_SIZE 32
  774. struct rtl_fw {
  775. const char *fw_name;
  776. const struct firmware *fw;
  777. char version[RTL_VER_SIZE];
  778. int (*pre_fw)(struct r8152 *tp);
  779. int (*post_fw)(struct r8152 *tp);
  780. bool retry;
  781. } rtl_fw;
  782. atomic_t rx_count;
  783. bool eee_en;
  784. int intr_interval;
  785. u32 saved_wolopts;
  786. u32 msg_enable;
  787. u32 tx_qlen;
  788. u32 coalesce;
  789. u32 advertising;
  790. u32 rx_buf_sz;
  791. u32 rx_copybreak;
  792. u32 rx_pending;
  793. u32 fc_pause_on, fc_pause_off;
  794. unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
  795. u32 support_2500full:1;
  796. u32 lenovo_macpassthru:1;
  797. u32 dell_tb_rx_agg_bug:1;
  798. u16 ocp_base;
  799. u16 speed;
  800. u16 eee_adv;
  801. u8 *intr_buff;
  802. u8 version;
  803. u8 duplex;
  804. u8 autoneg;
  805. };
  806. /**
  807. * struct fw_block - block type and total length
  808. * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
  809. * RTL_FW_USB and so on.
  810. * @length: total length of the current block.
  811. */
  812. struct fw_block {
  813. __le32 type;
  814. __le32 length;
  815. } __packed;
  816. /**
  817. * struct fw_header - header of the firmware file
  818. * @checksum: checksum of sha256 which is calculated from the whole file
  819. * except the checksum field of the file. That is, calculate sha256
  820. * from the version field to the end of the file.
  821. * @version: version of this firmware.
  822. * @blocks: the first firmware block of the file
  823. */
  824. struct fw_header {
  825. u8 checksum[32];
  826. char version[RTL_VER_SIZE];
  827. struct fw_block blocks[];
  828. } __packed;
  829. enum rtl8152_fw_flags {
  830. FW_FLAGS_USB = 0,
  831. FW_FLAGS_PLA,
  832. FW_FLAGS_START,
  833. FW_FLAGS_STOP,
  834. FW_FLAGS_NC,
  835. FW_FLAGS_NC1,
  836. FW_FLAGS_NC2,
  837. FW_FLAGS_UC2,
  838. FW_FLAGS_UC,
  839. FW_FLAGS_SPEED_UP,
  840. FW_FLAGS_VER,
  841. };
  842. enum rtl8152_fw_fixup_cmd {
  843. FW_FIXUP_AND = 0,
  844. FW_FIXUP_OR,
  845. FW_FIXUP_NOT,
  846. FW_FIXUP_XOR,
  847. };
  848. struct fw_phy_set {
  849. __le16 addr;
  850. __le16 data;
  851. } __packed;
  852. struct fw_phy_speed_up {
  853. struct fw_block blk_hdr;
  854. __le16 fw_offset;
  855. __le16 version;
  856. __le16 fw_reg;
  857. __le16 reserved;
  858. char info[];
  859. } __packed;
  860. struct fw_phy_ver {
  861. struct fw_block blk_hdr;
  862. struct fw_phy_set ver;
  863. __le32 reserved;
  864. } __packed;
  865. struct fw_phy_fixup {
  866. struct fw_block blk_hdr;
  867. struct fw_phy_set setting;
  868. __le16 bit_cmd;
  869. __le16 reserved;
  870. } __packed;
  871. struct fw_phy_union {
  872. struct fw_block blk_hdr;
  873. __le16 fw_offset;
  874. __le16 fw_reg;
  875. struct fw_phy_set pre_set[2];
  876. struct fw_phy_set bp[8];
  877. struct fw_phy_set bp_en;
  878. u8 pre_num;
  879. u8 bp_num;
  880. char info[];
  881. } __packed;
  882. /**
  883. * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
  884. * The layout of the firmware block is:
  885. * <struct fw_mac> + <info> + <firmware data>.
  886. * @blk_hdr: firmware descriptor (type, length)
  887. * @fw_offset: offset of the firmware binary data. The start address of
  888. * the data would be the address of struct fw_mac + @fw_offset.
  889. * @fw_reg: the register to load the firmware. Depends on chip.
  890. * @bp_ba_addr: the register to write break point base address. Depends on
  891. * chip.
  892. * @bp_ba_value: break point base address. Depends on chip.
  893. * @bp_en_addr: the register to write break point enabled mask. Depends
  894. * on chip.
  895. * @bp_en_value: break point enabled mask. Depends on the firmware.
  896. * @bp_start: the start register of break points. Depends on chip.
  897. * @bp_num: the break point number which needs to be set for this firmware.
  898. * Depends on the firmware.
  899. * @bp: break points. Depends on firmware.
  900. * @reserved: reserved space (unused)
  901. * @fw_ver_reg: the register to store the fw version.
  902. * @fw_ver_data: the firmware version of the current type.
  903. * @info: additional information for debugging, and is followed by the
  904. * binary data of firmware.
  905. */
  906. struct fw_mac {
  907. struct fw_block blk_hdr;
  908. __le16 fw_offset;
  909. __le16 fw_reg;
  910. __le16 bp_ba_addr;
  911. __le16 bp_ba_value;
  912. __le16 bp_en_addr;
  913. __le16 bp_en_value;
  914. __le16 bp_start;
  915. __le16 bp_num;
  916. __le16 bp[16]; /* any value determined by firmware */
  917. __le32 reserved;
  918. __le16 fw_ver_reg;
  919. u8 fw_ver_data;
  920. char info[];
  921. } __packed;
  922. /**
  923. * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
  924. * This is used to set patch key when loading the firmware of PHY.
  925. * @blk_hdr: firmware descriptor (type, length)
  926. * @key_reg: the register to write the patch key.
  927. * @key_data: patch key.
  928. * @reserved: reserved space (unused)
  929. */
  930. struct fw_phy_patch_key {
  931. struct fw_block blk_hdr;
  932. __le16 key_reg;
  933. __le16 key_data;
  934. __le32 reserved;
  935. } __packed;
  936. /**
  937. * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
  938. * The layout of the firmware block is:
  939. * <struct fw_phy_nc> + <info> + <firmware data>.
  940. * @blk_hdr: firmware descriptor (type, length)
  941. * @fw_offset: offset of the firmware binary data. The start address of
  942. * the data would be the address of struct fw_phy_nc + @fw_offset.
  943. * @fw_reg: the register to load the firmware. Depends on chip.
  944. * @ba_reg: the register to write the base address. Depends on chip.
  945. * @ba_data: base address. Depends on chip.
  946. * @patch_en_addr: the register of enabling patch mode. Depends on chip.
  947. * @patch_en_value: patch mode enabled mask. Depends on the firmware.
  948. * @mode_reg: the regitster of switching the mode.
  949. * @mode_pre: the mode needing to be set before loading the firmware.
  950. * @mode_post: the mode to be set when finishing to load the firmware.
  951. * @reserved: reserved space (unused)
  952. * @bp_start: the start register of break points. Depends on chip.
  953. * @bp_num: the break point number which needs to be set for this firmware.
  954. * Depends on the firmware.
  955. * @bp: break points. Depends on firmware.
  956. * @info: additional information for debugging, and is followed by the
  957. * binary data of firmware.
  958. */
  959. struct fw_phy_nc {
  960. struct fw_block blk_hdr;
  961. __le16 fw_offset;
  962. __le16 fw_reg;
  963. __le16 ba_reg;
  964. __le16 ba_data;
  965. __le16 patch_en_addr;
  966. __le16 patch_en_value;
  967. __le16 mode_reg;
  968. __le16 mode_pre;
  969. __le16 mode_post;
  970. __le16 reserved;
  971. __le16 bp_start;
  972. __le16 bp_num;
  973. __le16 bp[4];
  974. char info[];
  975. } __packed;
  976. enum rtl_fw_type {
  977. RTL_FW_END = 0,
  978. RTL_FW_PLA,
  979. RTL_FW_USB,
  980. RTL_FW_PHY_START,
  981. RTL_FW_PHY_STOP,
  982. RTL_FW_PHY_NC,
  983. RTL_FW_PHY_FIXUP,
  984. RTL_FW_PHY_UNION_NC,
  985. RTL_FW_PHY_UNION_NC1,
  986. RTL_FW_PHY_UNION_NC2,
  987. RTL_FW_PHY_UNION_UC2,
  988. RTL_FW_PHY_UNION_UC,
  989. RTL_FW_PHY_UNION_MISC,
  990. RTL_FW_PHY_SPEED_UP,
  991. RTL_FW_PHY_VER,
  992. };
  993. enum rtl_version {
  994. RTL_VER_UNKNOWN = 0,
  995. RTL_VER_01,
  996. RTL_VER_02,
  997. RTL_VER_03,
  998. RTL_VER_04,
  999. RTL_VER_05,
  1000. RTL_VER_06,
  1001. RTL_VER_07,
  1002. RTL_VER_08,
  1003. RTL_VER_09,
  1004. RTL_TEST_01,
  1005. RTL_VER_10,
  1006. RTL_VER_11,
  1007. RTL_VER_12,
  1008. RTL_VER_13,
  1009. RTL_VER_14,
  1010. RTL_VER_15,
  1011. RTL_VER_MAX
  1012. };
  1013. enum tx_csum_stat {
  1014. TX_CSUM_SUCCESS = 0,
  1015. TX_CSUM_TSO,
  1016. TX_CSUM_NONE
  1017. };
  1018. #define RTL_ADVERTISED_10_HALF BIT(0)
  1019. #define RTL_ADVERTISED_10_FULL BIT(1)
  1020. #define RTL_ADVERTISED_100_HALF BIT(2)
  1021. #define RTL_ADVERTISED_100_FULL BIT(3)
  1022. #define RTL_ADVERTISED_1000_HALF BIT(4)
  1023. #define RTL_ADVERTISED_1000_FULL BIT(5)
  1024. #define RTL_ADVERTISED_2500_FULL BIT(6)
  1025. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  1026. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  1027. */
  1028. static const int multicast_filter_limit = 32;
  1029. static unsigned int agg_buf_sz = 16384;
  1030. #define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
  1031. static
  1032. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  1033. {
  1034. int ret;
  1035. void *tmp;
  1036. tmp = kmalloc(size, GFP_KERNEL);
  1037. if (!tmp)
  1038. return -ENOMEM;
  1039. ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
  1040. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  1041. value, index, tmp, size, USB_CTRL_GET_TIMEOUT);
  1042. if (ret < 0)
  1043. memset(data, 0xff, size);
  1044. else
  1045. memcpy(data, tmp, size);
  1046. kfree(tmp);
  1047. return ret;
  1048. }
  1049. static
  1050. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  1051. {
  1052. int ret;
  1053. void *tmp;
  1054. tmp = kmemdup(data, size, GFP_KERNEL);
  1055. if (!tmp)
  1056. return -ENOMEM;
  1057. ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
  1058. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  1059. value, index, tmp, size, USB_CTRL_SET_TIMEOUT);
  1060. kfree(tmp);
  1061. return ret;
  1062. }
  1063. static void rtl_set_unplug(struct r8152 *tp)
  1064. {
  1065. if (tp->udev->state == USB_STATE_NOTATTACHED) {
  1066. set_bit(RTL8152_INACCESSIBLE, &tp->flags);
  1067. smp_mb__after_atomic();
  1068. }
  1069. }
  1070. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  1071. void *data, u16 type)
  1072. {
  1073. u16 limit = 64;
  1074. int ret = 0;
  1075. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1076. return -ENODEV;
  1077. /* both size and indix must be 4 bytes align */
  1078. if ((size & 3) || !size || (index & 3) || !data)
  1079. return -EPERM;
  1080. if ((u32)index + (u32)size > 0xffff)
  1081. return -EPERM;
  1082. while (size) {
  1083. if (size > limit) {
  1084. ret = get_registers(tp, index, type, limit, data);
  1085. if (ret < 0)
  1086. break;
  1087. index += limit;
  1088. data += limit;
  1089. size -= limit;
  1090. } else {
  1091. ret = get_registers(tp, index, type, size, data);
  1092. if (ret < 0)
  1093. break;
  1094. index += size;
  1095. data += size;
  1096. size = 0;
  1097. break;
  1098. }
  1099. }
  1100. if (ret == -ENODEV)
  1101. rtl_set_unplug(tp);
  1102. return ret;
  1103. }
  1104. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  1105. u16 size, void *data, u16 type)
  1106. {
  1107. int ret;
  1108. u16 byteen_start, byteen_end, byen;
  1109. u16 limit = 512;
  1110. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1111. return -ENODEV;
  1112. /* both size and indix must be 4 bytes align */
  1113. if ((size & 3) || !size || (index & 3) || !data)
  1114. return -EPERM;
  1115. if ((u32)index + (u32)size > 0xffff)
  1116. return -EPERM;
  1117. byteen_start = byteen & BYTE_EN_START_MASK;
  1118. byteen_end = byteen & BYTE_EN_END_MASK;
  1119. byen = byteen_start | (byteen_start << 4);
  1120. ret = set_registers(tp, index, type | byen, 4, data);
  1121. if (ret < 0)
  1122. goto error1;
  1123. index += 4;
  1124. data += 4;
  1125. size -= 4;
  1126. if (size) {
  1127. size -= 4;
  1128. while (size) {
  1129. if (size > limit) {
  1130. ret = set_registers(tp, index,
  1131. type | BYTE_EN_DWORD,
  1132. limit, data);
  1133. if (ret < 0)
  1134. goto error1;
  1135. index += limit;
  1136. data += limit;
  1137. size -= limit;
  1138. } else {
  1139. ret = set_registers(tp, index,
  1140. type | BYTE_EN_DWORD,
  1141. size, data);
  1142. if (ret < 0)
  1143. goto error1;
  1144. index += size;
  1145. data += size;
  1146. size = 0;
  1147. break;
  1148. }
  1149. }
  1150. byen = byteen_end | (byteen_end >> 4);
  1151. ret = set_registers(tp, index, type | byen, 4, data);
  1152. if (ret < 0)
  1153. goto error1;
  1154. }
  1155. error1:
  1156. if (ret == -ENODEV)
  1157. rtl_set_unplug(tp);
  1158. return ret;
  1159. }
  1160. static inline
  1161. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  1162. {
  1163. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  1164. }
  1165. static inline
  1166. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  1167. {
  1168. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  1169. }
  1170. static inline
  1171. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  1172. {
  1173. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  1174. }
  1175. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  1176. {
  1177. __le32 data;
  1178. generic_ocp_read(tp, index, sizeof(data), &data, type);
  1179. return __le32_to_cpu(data);
  1180. }
  1181. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  1182. {
  1183. __le32 tmp = __cpu_to_le32(data);
  1184. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  1185. }
  1186. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  1187. {
  1188. u32 data;
  1189. __le32 tmp;
  1190. u16 byen = BYTE_EN_WORD;
  1191. u8 shift = index & 2;
  1192. index &= ~3;
  1193. byen <<= shift;
  1194. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
  1195. data = __le32_to_cpu(tmp);
  1196. data >>= (shift * 8);
  1197. data &= 0xffff;
  1198. return (u16)data;
  1199. }
  1200. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  1201. {
  1202. u32 mask = 0xffff;
  1203. __le32 tmp;
  1204. u16 byen = BYTE_EN_WORD;
  1205. u8 shift = index & 2;
  1206. data &= mask;
  1207. if (index & 2) {
  1208. byen <<= shift;
  1209. mask <<= (shift * 8);
  1210. data <<= (shift * 8);
  1211. index &= ~3;
  1212. }
  1213. tmp = __cpu_to_le32(data);
  1214. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  1215. }
  1216. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  1217. {
  1218. u32 data;
  1219. __le32 tmp;
  1220. u8 shift = index & 3;
  1221. index &= ~3;
  1222. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  1223. data = __le32_to_cpu(tmp);
  1224. data >>= (shift * 8);
  1225. data &= 0xff;
  1226. return (u8)data;
  1227. }
  1228. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  1229. {
  1230. u32 mask = 0xff;
  1231. __le32 tmp;
  1232. u16 byen = BYTE_EN_BYTE;
  1233. u8 shift = index & 3;
  1234. data &= mask;
  1235. if (index & 3) {
  1236. byen <<= shift;
  1237. mask <<= (shift * 8);
  1238. data <<= (shift * 8);
  1239. index &= ~3;
  1240. }
  1241. tmp = __cpu_to_le32(data);
  1242. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  1243. }
  1244. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  1245. {
  1246. u16 ocp_base, ocp_index;
  1247. ocp_base = addr & 0xf000;
  1248. if (ocp_base != tp->ocp_base) {
  1249. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  1250. tp->ocp_base = ocp_base;
  1251. }
  1252. ocp_index = (addr & 0x0fff) | 0xb000;
  1253. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  1254. }
  1255. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  1256. {
  1257. u16 ocp_base, ocp_index;
  1258. ocp_base = addr & 0xf000;
  1259. if (ocp_base != tp->ocp_base) {
  1260. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  1261. tp->ocp_base = ocp_base;
  1262. }
  1263. ocp_index = (addr & 0x0fff) | 0xb000;
  1264. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  1265. }
  1266. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  1267. {
  1268. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  1269. }
  1270. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  1271. {
  1272. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  1273. }
  1274. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  1275. {
  1276. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  1277. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  1278. }
  1279. static u16 sram_read(struct r8152 *tp, u16 addr)
  1280. {
  1281. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  1282. return ocp_reg_read(tp, OCP_SRAM_DATA);
  1283. }
  1284. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  1285. {
  1286. struct r8152 *tp = netdev_priv(netdev);
  1287. int ret;
  1288. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1289. return -ENODEV;
  1290. if (phy_id != R8152_PHY_ID)
  1291. return -EINVAL;
  1292. ret = r8152_mdio_read(tp, reg);
  1293. return ret;
  1294. }
  1295. static
  1296. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  1297. {
  1298. struct r8152 *tp = netdev_priv(netdev);
  1299. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1300. return;
  1301. if (phy_id != R8152_PHY_ID)
  1302. return;
  1303. r8152_mdio_write(tp, reg, val);
  1304. }
  1305. static int
  1306. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  1307. static int
  1308. rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
  1309. u32 advertising);
  1310. static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
  1311. bool in_resume)
  1312. {
  1313. struct r8152 *tp = netdev_priv(netdev);
  1314. struct sockaddr *addr = p;
  1315. int ret = -EADDRNOTAVAIL;
  1316. if (!is_valid_ether_addr(addr->sa_data))
  1317. goto out1;
  1318. if (!in_resume) {
  1319. ret = usb_autopm_get_interface(tp->intf);
  1320. if (ret < 0)
  1321. goto out1;
  1322. }
  1323. mutex_lock(&tp->control);
  1324. eth_hw_addr_set(netdev, addr->sa_data);
  1325. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1326. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  1327. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1328. mutex_unlock(&tp->control);
  1329. if (!in_resume)
  1330. usb_autopm_put_interface(tp->intf);
  1331. out1:
  1332. return ret;
  1333. }
  1334. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  1335. {
  1336. return __rtl8152_set_mac_address(netdev, p, false);
  1337. }
  1338. /* Devices containing proper chips can support a persistent
  1339. * host system provided MAC address.
  1340. * Examples of this are Dell TB15 and Dell WD15 docks
  1341. */
  1342. static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
  1343. {
  1344. acpi_status status;
  1345. struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
  1346. union acpi_object *obj;
  1347. int ret = -EINVAL;
  1348. u32 ocp_data;
  1349. unsigned char buf[6];
  1350. char *mac_obj_name;
  1351. acpi_object_type mac_obj_type;
  1352. int mac_strlen;
  1353. if (tp->lenovo_macpassthru) {
  1354. mac_obj_name = "\\MACA";
  1355. mac_obj_type = ACPI_TYPE_STRING;
  1356. mac_strlen = 0x16;
  1357. } else {
  1358. /* test for -AD variant of RTL8153 */
  1359. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1360. if ((ocp_data & AD_MASK) == 0x1000) {
  1361. /* test for MAC address pass-through bit */
  1362. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
  1363. if ((ocp_data & PASS_THRU_MASK) != 1) {
  1364. netif_dbg(tp, probe, tp->netdev,
  1365. "No efuse for RTL8153-AD MAC pass through\n");
  1366. return -ENODEV;
  1367. }
  1368. } else {
  1369. /* test for RTL8153-BND and RTL8153-BD */
  1370. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
  1371. if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
  1372. netif_dbg(tp, probe, tp->netdev,
  1373. "Invalid variant for MAC pass through\n");
  1374. return -ENODEV;
  1375. }
  1376. }
  1377. mac_obj_name = "\\_SB.AMAC";
  1378. mac_obj_type = ACPI_TYPE_BUFFER;
  1379. mac_strlen = 0x17;
  1380. }
  1381. /* returns _AUXMAC_#AABBCCDDEEFF# */
  1382. status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
  1383. obj = (union acpi_object *)buffer.pointer;
  1384. if (!ACPI_SUCCESS(status))
  1385. return -ENODEV;
  1386. if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
  1387. netif_warn(tp, probe, tp->netdev,
  1388. "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
  1389. obj->type, obj->string.length);
  1390. goto amacout;
  1391. }
  1392. if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
  1393. strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
  1394. netif_warn(tp, probe, tp->netdev,
  1395. "Invalid header when reading pass-thru MAC addr\n");
  1396. goto amacout;
  1397. }
  1398. ret = hex2bin(buf, obj->string.pointer + 9, 6);
  1399. if (!(ret == 0 && is_valid_ether_addr(buf))) {
  1400. netif_warn(tp, probe, tp->netdev,
  1401. "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
  1402. ret, buf);
  1403. ret = -EINVAL;
  1404. goto amacout;
  1405. }
  1406. memcpy(sa->sa_data, buf, 6);
  1407. netif_info(tp, probe, tp->netdev,
  1408. "Using pass-thru MAC addr %pM\n", sa->sa_data);
  1409. amacout:
  1410. kfree(obj);
  1411. return ret;
  1412. }
  1413. static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
  1414. {
  1415. struct net_device *dev = tp->netdev;
  1416. int ret;
  1417. sa->sa_family = dev->type;
  1418. ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
  1419. if (ret < 0) {
  1420. if (tp->version == RTL_VER_01) {
  1421. ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
  1422. } else {
  1423. /* if device doesn't support MAC pass through this will
  1424. * be expected to be non-zero
  1425. */
  1426. ret = vendor_mac_passthru_addr_read(tp, sa);
  1427. if (ret < 0)
  1428. ret = pla_ocp_read(tp, PLA_BACKUP, 8,
  1429. sa->sa_data);
  1430. }
  1431. }
  1432. if (ret < 0) {
  1433. netif_err(tp, probe, dev, "Get ether addr fail\n");
  1434. } else if (!is_valid_ether_addr(sa->sa_data)) {
  1435. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  1436. sa->sa_data);
  1437. eth_hw_addr_random(dev);
  1438. ether_addr_copy(sa->sa_data, dev->dev_addr);
  1439. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  1440. sa->sa_data);
  1441. return 0;
  1442. }
  1443. return ret;
  1444. }
  1445. static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
  1446. {
  1447. struct net_device *dev = tp->netdev;
  1448. struct sockaddr sa;
  1449. int ret;
  1450. ret = determine_ethernet_addr(tp, &sa);
  1451. if (ret < 0)
  1452. return ret;
  1453. if (tp->version == RTL_VER_01)
  1454. eth_hw_addr_set(dev, sa.sa_data);
  1455. else
  1456. ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
  1457. return ret;
  1458. }
  1459. static void read_bulk_callback(struct urb *urb)
  1460. {
  1461. struct net_device *netdev;
  1462. int status = urb->status;
  1463. struct rx_agg *agg;
  1464. struct r8152 *tp;
  1465. unsigned long flags;
  1466. agg = urb->context;
  1467. if (!agg)
  1468. return;
  1469. tp = agg->context;
  1470. if (!tp)
  1471. return;
  1472. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1473. return;
  1474. if (!test_bit(WORK_ENABLE, &tp->flags))
  1475. return;
  1476. netdev = tp->netdev;
  1477. /* When link down, the driver would cancel all bulks. */
  1478. /* This avoid the re-submitting bulk */
  1479. if (!netif_carrier_ok(netdev))
  1480. return;
  1481. usb_mark_last_busy(tp->udev);
  1482. switch (status) {
  1483. case 0:
  1484. if (urb->actual_length < ETH_ZLEN)
  1485. break;
  1486. spin_lock_irqsave(&tp->rx_lock, flags);
  1487. list_add_tail(&agg->list, &tp->rx_done);
  1488. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1489. napi_schedule(&tp->napi);
  1490. return;
  1491. case -ESHUTDOWN:
  1492. rtl_set_unplug(tp);
  1493. netif_device_detach(tp->netdev);
  1494. return;
  1495. case -EPROTO:
  1496. urb->actual_length = 0;
  1497. spin_lock_irqsave(&tp->rx_lock, flags);
  1498. list_add_tail(&agg->list, &tp->rx_done);
  1499. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1500. set_bit(RX_EPROTO, &tp->flags);
  1501. schedule_delayed_work(&tp->schedule, 1);
  1502. return;
  1503. case -ENOENT:
  1504. return; /* the urb is in unlink state */
  1505. case -ETIME:
  1506. if (net_ratelimit())
  1507. netdev_warn(netdev, "maybe reset is needed?\n");
  1508. break;
  1509. default:
  1510. if (net_ratelimit())
  1511. netdev_warn(netdev, "Rx status %d\n", status);
  1512. break;
  1513. }
  1514. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1515. }
  1516. static void write_bulk_callback(struct urb *urb)
  1517. {
  1518. struct net_device_stats *stats;
  1519. struct net_device *netdev;
  1520. struct tx_agg *agg;
  1521. struct r8152 *tp;
  1522. unsigned long flags;
  1523. int status = urb->status;
  1524. agg = urb->context;
  1525. if (!agg)
  1526. return;
  1527. tp = agg->context;
  1528. if (!tp)
  1529. return;
  1530. netdev = tp->netdev;
  1531. stats = &netdev->stats;
  1532. if (status) {
  1533. if (net_ratelimit())
  1534. netdev_warn(netdev, "Tx status %d\n", status);
  1535. stats->tx_errors += agg->skb_num;
  1536. } else {
  1537. stats->tx_packets += agg->skb_num;
  1538. stats->tx_bytes += agg->skb_len;
  1539. }
  1540. spin_lock_irqsave(&tp->tx_lock, flags);
  1541. list_add_tail(&agg->list, &tp->tx_free);
  1542. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1543. usb_autopm_put_interface_async(tp->intf);
  1544. if (!netif_carrier_ok(netdev))
  1545. return;
  1546. if (!test_bit(WORK_ENABLE, &tp->flags))
  1547. return;
  1548. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1549. return;
  1550. if (!skb_queue_empty(&tp->tx_queue))
  1551. tasklet_schedule(&tp->tx_tl);
  1552. }
  1553. static void intr_callback(struct urb *urb)
  1554. {
  1555. struct r8152 *tp;
  1556. __le16 *d;
  1557. int status = urb->status;
  1558. int res;
  1559. tp = urb->context;
  1560. if (!tp)
  1561. return;
  1562. if (!test_bit(WORK_ENABLE, &tp->flags))
  1563. return;
  1564. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  1565. return;
  1566. switch (status) {
  1567. case 0: /* success */
  1568. break;
  1569. case -ECONNRESET: /* unlink */
  1570. case -ESHUTDOWN:
  1571. netif_device_detach(tp->netdev);
  1572. fallthrough;
  1573. case -ENOENT:
  1574. case -EPROTO:
  1575. netif_info(tp, intr, tp->netdev,
  1576. "Stop submitting intr, status %d\n", status);
  1577. return;
  1578. case -EOVERFLOW:
  1579. if (net_ratelimit())
  1580. netif_info(tp, intr, tp->netdev,
  1581. "intr status -EOVERFLOW\n");
  1582. goto resubmit;
  1583. /* -EPIPE: should clear the halt */
  1584. default:
  1585. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  1586. goto resubmit;
  1587. }
  1588. d = urb->transfer_buffer;
  1589. if (INTR_LINK & __le16_to_cpu(d[0])) {
  1590. if (!netif_carrier_ok(tp->netdev)) {
  1591. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1592. schedule_delayed_work(&tp->schedule, 0);
  1593. }
  1594. } else {
  1595. if (netif_carrier_ok(tp->netdev)) {
  1596. netif_stop_queue(tp->netdev);
  1597. set_bit(RTL8152_LINK_CHG, &tp->flags);
  1598. schedule_delayed_work(&tp->schedule, 0);
  1599. }
  1600. }
  1601. resubmit:
  1602. res = usb_submit_urb(urb, GFP_ATOMIC);
  1603. if (res == -ENODEV) {
  1604. rtl_set_unplug(tp);
  1605. netif_device_detach(tp->netdev);
  1606. } else if (res) {
  1607. netif_err(tp, intr, tp->netdev,
  1608. "can't resubmit intr, status %d\n", res);
  1609. }
  1610. }
  1611. static inline void *rx_agg_align(void *data)
  1612. {
  1613. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1614. }
  1615. static inline void *tx_agg_align(void *data)
  1616. {
  1617. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1618. }
  1619. static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
  1620. {
  1621. list_del(&agg->info_list);
  1622. usb_free_urb(agg->urb);
  1623. put_page(agg->page);
  1624. kfree(agg);
  1625. atomic_dec(&tp->rx_count);
  1626. }
  1627. static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
  1628. {
  1629. struct net_device *netdev = tp->netdev;
  1630. int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1631. unsigned int order = get_order(tp->rx_buf_sz);
  1632. struct rx_agg *rx_agg;
  1633. unsigned long flags;
  1634. rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
  1635. if (!rx_agg)
  1636. return NULL;
  1637. rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
  1638. if (!rx_agg->page)
  1639. goto free_rx;
  1640. rx_agg->buffer = page_address(rx_agg->page);
  1641. rx_agg->urb = usb_alloc_urb(0, mflags);
  1642. if (!rx_agg->urb)
  1643. goto free_buf;
  1644. rx_agg->context = tp;
  1645. INIT_LIST_HEAD(&rx_agg->list);
  1646. INIT_LIST_HEAD(&rx_agg->info_list);
  1647. spin_lock_irqsave(&tp->rx_lock, flags);
  1648. list_add_tail(&rx_agg->info_list, &tp->rx_info);
  1649. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1650. atomic_inc(&tp->rx_count);
  1651. return rx_agg;
  1652. free_buf:
  1653. __free_pages(rx_agg->page, order);
  1654. free_rx:
  1655. kfree(rx_agg);
  1656. return NULL;
  1657. }
  1658. static void free_all_mem(struct r8152 *tp)
  1659. {
  1660. struct rx_agg *agg, *agg_next;
  1661. unsigned long flags;
  1662. int i;
  1663. spin_lock_irqsave(&tp->rx_lock, flags);
  1664. list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
  1665. free_rx_agg(tp, agg);
  1666. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1667. WARN_ON(atomic_read(&tp->rx_count));
  1668. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1669. usb_free_urb(tp->tx_info[i].urb);
  1670. tp->tx_info[i].urb = NULL;
  1671. kfree(tp->tx_info[i].buffer);
  1672. tp->tx_info[i].buffer = NULL;
  1673. tp->tx_info[i].head = NULL;
  1674. }
  1675. usb_free_urb(tp->intr_urb);
  1676. tp->intr_urb = NULL;
  1677. kfree(tp->intr_buff);
  1678. tp->intr_buff = NULL;
  1679. }
  1680. static int alloc_all_mem(struct r8152 *tp)
  1681. {
  1682. struct net_device *netdev = tp->netdev;
  1683. struct usb_interface *intf = tp->intf;
  1684. struct usb_host_interface *alt = intf->cur_altsetting;
  1685. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1686. int node, i;
  1687. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1688. spin_lock_init(&tp->rx_lock);
  1689. spin_lock_init(&tp->tx_lock);
  1690. INIT_LIST_HEAD(&tp->rx_info);
  1691. INIT_LIST_HEAD(&tp->tx_free);
  1692. INIT_LIST_HEAD(&tp->rx_done);
  1693. skb_queue_head_init(&tp->tx_queue);
  1694. skb_queue_head_init(&tp->rx_queue);
  1695. atomic_set(&tp->rx_count, 0);
  1696. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1697. if (!alloc_rx_agg(tp, GFP_KERNEL))
  1698. goto err1;
  1699. }
  1700. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1701. struct urb *urb;
  1702. u8 *buf;
  1703. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1704. if (!buf)
  1705. goto err1;
  1706. if (buf != tx_agg_align(buf)) {
  1707. kfree(buf);
  1708. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1709. node);
  1710. if (!buf)
  1711. goto err1;
  1712. }
  1713. urb = usb_alloc_urb(0, GFP_KERNEL);
  1714. if (!urb) {
  1715. kfree(buf);
  1716. goto err1;
  1717. }
  1718. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1719. tp->tx_info[i].context = tp;
  1720. tp->tx_info[i].urb = urb;
  1721. tp->tx_info[i].buffer = buf;
  1722. tp->tx_info[i].head = tx_agg_align(buf);
  1723. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1724. }
  1725. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1726. if (!tp->intr_urb)
  1727. goto err1;
  1728. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1729. if (!tp->intr_buff)
  1730. goto err1;
  1731. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1732. usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
  1733. tp->intr_buff, INTBUFSIZE, intr_callback,
  1734. tp, tp->intr_interval);
  1735. return 0;
  1736. err1:
  1737. free_all_mem(tp);
  1738. return -ENOMEM;
  1739. }
  1740. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1741. {
  1742. struct tx_agg *agg = NULL;
  1743. unsigned long flags;
  1744. if (list_empty(&tp->tx_free))
  1745. return NULL;
  1746. spin_lock_irqsave(&tp->tx_lock, flags);
  1747. if (!list_empty(&tp->tx_free)) {
  1748. struct list_head *cursor;
  1749. cursor = tp->tx_free.next;
  1750. list_del_init(cursor);
  1751. agg = list_entry(cursor, struct tx_agg, list);
  1752. }
  1753. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1754. return agg;
  1755. }
  1756. /* r8152_csum_workaround()
  1757. * The hw limits the value of the transport offset. When the offset is out of
  1758. * range, calculate the checksum by sw.
  1759. */
  1760. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1761. struct sk_buff_head *list)
  1762. {
  1763. if (skb_shinfo(skb)->gso_size) {
  1764. netdev_features_t features = tp->netdev->features;
  1765. struct sk_buff *segs, *seg, *next;
  1766. struct sk_buff_head seg_list;
  1767. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1768. segs = skb_gso_segment(skb, features);
  1769. if (IS_ERR(segs) || !segs)
  1770. goto drop;
  1771. __skb_queue_head_init(&seg_list);
  1772. skb_list_walk_safe(segs, seg, next) {
  1773. skb_mark_not_on_list(seg);
  1774. __skb_queue_tail(&seg_list, seg);
  1775. }
  1776. skb_queue_splice(&seg_list, list);
  1777. dev_kfree_skb(skb);
  1778. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1779. if (skb_checksum_help(skb) < 0)
  1780. goto drop;
  1781. __skb_queue_head(list, skb);
  1782. } else {
  1783. struct net_device_stats *stats;
  1784. drop:
  1785. stats = &tp->netdev->stats;
  1786. stats->tx_dropped++;
  1787. dev_kfree_skb(skb);
  1788. }
  1789. }
  1790. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1791. {
  1792. if (skb_vlan_tag_present(skb)) {
  1793. u32 opts2;
  1794. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1795. desc->opts2 |= cpu_to_le32(opts2);
  1796. }
  1797. }
  1798. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1799. {
  1800. u32 opts2 = le32_to_cpu(desc->opts2);
  1801. if (opts2 & RX_VLAN_TAG)
  1802. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1803. swab16(opts2 & 0xffff));
  1804. }
  1805. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1806. struct sk_buff *skb, u32 len)
  1807. {
  1808. u32 mss = skb_shinfo(skb)->gso_size;
  1809. u32 opts1, opts2 = 0;
  1810. int ret = TX_CSUM_SUCCESS;
  1811. WARN_ON_ONCE(len > TX_LEN_MAX);
  1812. opts1 = len | TX_FS | TX_LS;
  1813. if (mss) {
  1814. u32 transport_offset = (u32)skb_transport_offset(skb);
  1815. if (transport_offset > GTTCPHO_MAX) {
  1816. netif_warn(tp, tx_err, tp->netdev,
  1817. "Invalid transport offset 0x%x for TSO\n",
  1818. transport_offset);
  1819. ret = TX_CSUM_TSO;
  1820. goto unavailable;
  1821. }
  1822. switch (vlan_get_protocol(skb)) {
  1823. case htons(ETH_P_IP):
  1824. opts1 |= GTSENDV4;
  1825. break;
  1826. case htons(ETH_P_IPV6):
  1827. if (skb_cow_head(skb, 0)) {
  1828. ret = TX_CSUM_TSO;
  1829. goto unavailable;
  1830. }
  1831. tcp_v6_gso_csum_prep(skb);
  1832. opts1 |= GTSENDV6;
  1833. break;
  1834. default:
  1835. WARN_ON_ONCE(1);
  1836. break;
  1837. }
  1838. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1839. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1840. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1841. u32 transport_offset = (u32)skb_transport_offset(skb);
  1842. u8 ip_protocol;
  1843. if (transport_offset > TCPHO_MAX) {
  1844. netif_warn(tp, tx_err, tp->netdev,
  1845. "Invalid transport offset 0x%x\n",
  1846. transport_offset);
  1847. ret = TX_CSUM_NONE;
  1848. goto unavailable;
  1849. }
  1850. switch (vlan_get_protocol(skb)) {
  1851. case htons(ETH_P_IP):
  1852. opts2 |= IPV4_CS;
  1853. ip_protocol = ip_hdr(skb)->protocol;
  1854. break;
  1855. case htons(ETH_P_IPV6):
  1856. opts2 |= IPV6_CS;
  1857. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1858. break;
  1859. default:
  1860. ip_protocol = IPPROTO_RAW;
  1861. break;
  1862. }
  1863. if (ip_protocol == IPPROTO_TCP)
  1864. opts2 |= TCP_CS;
  1865. else if (ip_protocol == IPPROTO_UDP)
  1866. opts2 |= UDP_CS;
  1867. else
  1868. WARN_ON_ONCE(1);
  1869. opts2 |= transport_offset << TCPHO_SHIFT;
  1870. }
  1871. desc->opts2 = cpu_to_le32(opts2);
  1872. desc->opts1 = cpu_to_le32(opts1);
  1873. unavailable:
  1874. return ret;
  1875. }
  1876. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1877. {
  1878. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1879. int remain, ret;
  1880. u8 *tx_data;
  1881. __skb_queue_head_init(&skb_head);
  1882. spin_lock(&tx_queue->lock);
  1883. skb_queue_splice_init(tx_queue, &skb_head);
  1884. spin_unlock(&tx_queue->lock);
  1885. tx_data = agg->head;
  1886. agg->skb_num = 0;
  1887. agg->skb_len = 0;
  1888. remain = agg_buf_sz;
  1889. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1890. struct tx_desc *tx_desc;
  1891. struct sk_buff *skb;
  1892. unsigned int len;
  1893. skb = __skb_dequeue(&skb_head);
  1894. if (!skb)
  1895. break;
  1896. len = skb->len + sizeof(*tx_desc);
  1897. if (len > remain) {
  1898. __skb_queue_head(&skb_head, skb);
  1899. break;
  1900. }
  1901. tx_data = tx_agg_align(tx_data);
  1902. tx_desc = (struct tx_desc *)tx_data;
  1903. if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
  1904. r8152_csum_workaround(tp, skb, &skb_head);
  1905. continue;
  1906. }
  1907. rtl_tx_vlan_tag(tx_desc, skb);
  1908. tx_data += sizeof(*tx_desc);
  1909. len = skb->len;
  1910. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1911. struct net_device_stats *stats = &tp->netdev->stats;
  1912. stats->tx_dropped++;
  1913. dev_kfree_skb_any(skb);
  1914. tx_data -= sizeof(*tx_desc);
  1915. continue;
  1916. }
  1917. tx_data += len;
  1918. agg->skb_len += len;
  1919. agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
  1920. dev_kfree_skb_any(skb);
  1921. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1922. if (tp->dell_tb_rx_agg_bug)
  1923. break;
  1924. }
  1925. if (!skb_queue_empty(&skb_head)) {
  1926. spin_lock(&tx_queue->lock);
  1927. skb_queue_splice(&skb_head, tx_queue);
  1928. spin_unlock(&tx_queue->lock);
  1929. }
  1930. netif_tx_lock(tp->netdev);
  1931. if (netif_queue_stopped(tp->netdev) &&
  1932. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1933. netif_wake_queue(tp->netdev);
  1934. netif_tx_unlock(tp->netdev);
  1935. ret = usb_autopm_get_interface_async(tp->intf);
  1936. if (ret < 0)
  1937. goto out_tx_fill;
  1938. usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
  1939. agg->head, (int)(tx_data - (u8 *)agg->head),
  1940. (usb_complete_t)write_bulk_callback, agg);
  1941. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1942. if (ret < 0)
  1943. usb_autopm_put_interface_async(tp->intf);
  1944. out_tx_fill:
  1945. return ret;
  1946. }
  1947. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1948. {
  1949. u8 checksum = CHECKSUM_NONE;
  1950. u32 opts2, opts3;
  1951. if (!(tp->netdev->features & NETIF_F_RXCSUM))
  1952. goto return_result;
  1953. opts2 = le32_to_cpu(rx_desc->opts2);
  1954. opts3 = le32_to_cpu(rx_desc->opts3);
  1955. if (opts2 & RD_IPV4_CS) {
  1956. if (opts3 & IPF)
  1957. checksum = CHECKSUM_NONE;
  1958. else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1959. checksum = CHECKSUM_UNNECESSARY;
  1960. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1961. checksum = CHECKSUM_UNNECESSARY;
  1962. } else if (opts2 & RD_IPV6_CS) {
  1963. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1964. checksum = CHECKSUM_UNNECESSARY;
  1965. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1966. checksum = CHECKSUM_UNNECESSARY;
  1967. }
  1968. return_result:
  1969. return checksum;
  1970. }
  1971. static inline bool rx_count_exceed(struct r8152 *tp)
  1972. {
  1973. return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
  1974. }
  1975. static inline int agg_offset(struct rx_agg *agg, void *addr)
  1976. {
  1977. return (int)(addr - agg->buffer);
  1978. }
  1979. static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
  1980. {
  1981. struct rx_agg *agg, *agg_next, *agg_free = NULL;
  1982. unsigned long flags;
  1983. spin_lock_irqsave(&tp->rx_lock, flags);
  1984. list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
  1985. if (page_count(agg->page) == 1) {
  1986. if (!agg_free) {
  1987. list_del_init(&agg->list);
  1988. agg_free = agg;
  1989. continue;
  1990. }
  1991. if (rx_count_exceed(tp)) {
  1992. list_del_init(&agg->list);
  1993. free_rx_agg(tp, agg);
  1994. }
  1995. break;
  1996. }
  1997. }
  1998. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1999. if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
  2000. agg_free = alloc_rx_agg(tp, mflags);
  2001. return agg_free;
  2002. }
  2003. static int rx_bottom(struct r8152 *tp, int budget)
  2004. {
  2005. unsigned long flags;
  2006. struct list_head *cursor, *next, rx_queue;
  2007. int ret = 0, work_done = 0;
  2008. struct napi_struct *napi = &tp->napi;
  2009. if (!skb_queue_empty(&tp->rx_queue)) {
  2010. while (work_done < budget) {
  2011. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  2012. struct net_device *netdev = tp->netdev;
  2013. struct net_device_stats *stats = &netdev->stats;
  2014. unsigned int pkt_len;
  2015. if (!skb)
  2016. break;
  2017. pkt_len = skb->len;
  2018. napi_gro_receive(napi, skb);
  2019. work_done++;
  2020. stats->rx_packets++;
  2021. stats->rx_bytes += pkt_len;
  2022. }
  2023. }
  2024. if (list_empty(&tp->rx_done))
  2025. goto out1;
  2026. clear_bit(RX_EPROTO, &tp->flags);
  2027. INIT_LIST_HEAD(&rx_queue);
  2028. spin_lock_irqsave(&tp->rx_lock, flags);
  2029. list_splice_init(&tp->rx_done, &rx_queue);
  2030. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2031. list_for_each_safe(cursor, next, &rx_queue) {
  2032. struct rx_desc *rx_desc;
  2033. struct rx_agg *agg, *agg_free;
  2034. int len_used = 0;
  2035. struct urb *urb;
  2036. u8 *rx_data;
  2037. list_del_init(cursor);
  2038. agg = list_entry(cursor, struct rx_agg, list);
  2039. urb = agg->urb;
  2040. if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
  2041. goto submit;
  2042. agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
  2043. rx_desc = agg->buffer;
  2044. rx_data = agg->buffer;
  2045. len_used += sizeof(struct rx_desc);
  2046. while (urb->actual_length > len_used) {
  2047. struct net_device *netdev = tp->netdev;
  2048. struct net_device_stats *stats = &netdev->stats;
  2049. unsigned int pkt_len, rx_frag_head_sz;
  2050. struct sk_buff *skb;
  2051. /* limit the skb numbers for rx_queue */
  2052. if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
  2053. break;
  2054. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  2055. if (pkt_len < ETH_ZLEN)
  2056. break;
  2057. len_used += pkt_len;
  2058. if (urb->actual_length < len_used)
  2059. break;
  2060. pkt_len -= ETH_FCS_LEN;
  2061. rx_data += sizeof(struct rx_desc);
  2062. if (!agg_free || tp->rx_copybreak > pkt_len)
  2063. rx_frag_head_sz = pkt_len;
  2064. else
  2065. rx_frag_head_sz = tp->rx_copybreak;
  2066. skb = napi_alloc_skb(napi, rx_frag_head_sz);
  2067. if (!skb) {
  2068. stats->rx_dropped++;
  2069. goto find_next_rx;
  2070. }
  2071. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  2072. memcpy(skb->data, rx_data, rx_frag_head_sz);
  2073. skb_put(skb, rx_frag_head_sz);
  2074. pkt_len -= rx_frag_head_sz;
  2075. rx_data += rx_frag_head_sz;
  2076. if (pkt_len) {
  2077. skb_add_rx_frag(skb, 0, agg->page,
  2078. agg_offset(agg, rx_data),
  2079. pkt_len,
  2080. SKB_DATA_ALIGN(pkt_len));
  2081. get_page(agg->page);
  2082. }
  2083. skb->protocol = eth_type_trans(skb, netdev);
  2084. rtl_rx_vlan_tag(rx_desc, skb);
  2085. if (work_done < budget) {
  2086. work_done++;
  2087. stats->rx_packets++;
  2088. stats->rx_bytes += skb->len;
  2089. napi_gro_receive(napi, skb);
  2090. } else {
  2091. __skb_queue_tail(&tp->rx_queue, skb);
  2092. }
  2093. find_next_rx:
  2094. rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
  2095. rx_desc = (struct rx_desc *)rx_data;
  2096. len_used = agg_offset(agg, rx_data);
  2097. len_used += sizeof(struct rx_desc);
  2098. }
  2099. WARN_ON(!agg_free && page_count(agg->page) > 1);
  2100. if (agg_free) {
  2101. spin_lock_irqsave(&tp->rx_lock, flags);
  2102. if (page_count(agg->page) == 1) {
  2103. list_add(&agg_free->list, &tp->rx_used);
  2104. } else {
  2105. list_add_tail(&agg->list, &tp->rx_used);
  2106. agg = agg_free;
  2107. urb = agg->urb;
  2108. }
  2109. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2110. }
  2111. submit:
  2112. if (!ret) {
  2113. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  2114. } else {
  2115. urb->actual_length = 0;
  2116. list_add_tail(&agg->list, next);
  2117. }
  2118. }
  2119. if (!list_empty(&rx_queue)) {
  2120. spin_lock_irqsave(&tp->rx_lock, flags);
  2121. list_splice_tail(&rx_queue, &tp->rx_done);
  2122. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2123. }
  2124. out1:
  2125. return work_done;
  2126. }
  2127. static void tx_bottom(struct r8152 *tp)
  2128. {
  2129. int res;
  2130. do {
  2131. struct net_device *netdev = tp->netdev;
  2132. struct tx_agg *agg;
  2133. if (skb_queue_empty(&tp->tx_queue))
  2134. break;
  2135. agg = r8152_get_tx_agg(tp);
  2136. if (!agg)
  2137. break;
  2138. res = r8152_tx_agg_fill(tp, agg);
  2139. if (!res)
  2140. continue;
  2141. if (res == -ENODEV) {
  2142. rtl_set_unplug(tp);
  2143. netif_device_detach(netdev);
  2144. } else {
  2145. struct net_device_stats *stats = &netdev->stats;
  2146. unsigned long flags;
  2147. netif_warn(tp, tx_err, netdev,
  2148. "failed tx_urb %d\n", res);
  2149. stats->tx_dropped += agg->skb_num;
  2150. spin_lock_irqsave(&tp->tx_lock, flags);
  2151. list_add_tail(&agg->list, &tp->tx_free);
  2152. spin_unlock_irqrestore(&tp->tx_lock, flags);
  2153. }
  2154. } while (res == 0);
  2155. }
  2156. static void bottom_half(struct tasklet_struct *t)
  2157. {
  2158. struct r8152 *tp = from_tasklet(tp, t, tx_tl);
  2159. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2160. return;
  2161. if (!test_bit(WORK_ENABLE, &tp->flags))
  2162. return;
  2163. /* When link down, the driver would cancel all bulks. */
  2164. /* This avoid the re-submitting bulk */
  2165. if (!netif_carrier_ok(tp->netdev))
  2166. return;
  2167. clear_bit(SCHEDULE_TASKLET, &tp->flags);
  2168. tx_bottom(tp);
  2169. }
  2170. static int r8152_poll(struct napi_struct *napi, int budget)
  2171. {
  2172. struct r8152 *tp = container_of(napi, struct r8152, napi);
  2173. int work_done;
  2174. if (!budget)
  2175. return 0;
  2176. work_done = rx_bottom(tp, budget);
  2177. if (work_done < budget) {
  2178. if (!napi_complete_done(napi, work_done))
  2179. goto out;
  2180. if (!list_empty(&tp->rx_done))
  2181. napi_schedule(napi);
  2182. }
  2183. out:
  2184. return work_done;
  2185. }
  2186. static
  2187. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  2188. {
  2189. int ret;
  2190. /* The rx would be stopped, so skip submitting */
  2191. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
  2192. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  2193. return 0;
  2194. usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
  2195. agg->buffer, tp->rx_buf_sz,
  2196. (usb_complete_t)read_bulk_callback, agg);
  2197. ret = usb_submit_urb(agg->urb, mem_flags);
  2198. if (ret == -ENODEV) {
  2199. rtl_set_unplug(tp);
  2200. netif_device_detach(tp->netdev);
  2201. } else if (ret) {
  2202. struct urb *urb = agg->urb;
  2203. unsigned long flags;
  2204. urb->actual_length = 0;
  2205. spin_lock_irqsave(&tp->rx_lock, flags);
  2206. list_add_tail(&agg->list, &tp->rx_done);
  2207. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2208. netif_err(tp, rx_err, tp->netdev,
  2209. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  2210. napi_schedule(&tp->napi);
  2211. }
  2212. return ret;
  2213. }
  2214. static void rtl_drop_queued_tx(struct r8152 *tp)
  2215. {
  2216. struct net_device_stats *stats = &tp->netdev->stats;
  2217. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  2218. struct sk_buff *skb;
  2219. if (skb_queue_empty(tx_queue))
  2220. return;
  2221. __skb_queue_head_init(&skb_head);
  2222. spin_lock_bh(&tx_queue->lock);
  2223. skb_queue_splice_init(tx_queue, &skb_head);
  2224. spin_unlock_bh(&tx_queue->lock);
  2225. while ((skb = __skb_dequeue(&skb_head))) {
  2226. dev_kfree_skb(skb);
  2227. stats->tx_dropped++;
  2228. }
  2229. }
  2230. static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
  2231. {
  2232. struct r8152 *tp = netdev_priv(netdev);
  2233. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  2234. usb_queue_reset_device(tp->intf);
  2235. }
  2236. static void rtl8152_set_rx_mode(struct net_device *netdev)
  2237. {
  2238. struct r8152 *tp = netdev_priv(netdev);
  2239. if (netif_carrier_ok(netdev)) {
  2240. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2241. schedule_delayed_work(&tp->schedule, 0);
  2242. }
  2243. }
  2244. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  2245. {
  2246. struct r8152 *tp = netdev_priv(netdev);
  2247. u32 mc_filter[2]; /* Multicast hash filter */
  2248. __le32 tmp[2];
  2249. u32 ocp_data;
  2250. netif_stop_queue(netdev);
  2251. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2252. ocp_data &= ~RCR_ACPT_ALL;
  2253. ocp_data |= RCR_AB | RCR_APM;
  2254. if (netdev->flags & IFF_PROMISC) {
  2255. /* Unconditionally log net taps. */
  2256. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  2257. ocp_data |= RCR_AM | RCR_AAP;
  2258. mc_filter[1] = 0xffffffff;
  2259. mc_filter[0] = 0xffffffff;
  2260. } else if ((netdev->flags & IFF_MULTICAST &&
  2261. netdev_mc_count(netdev) > multicast_filter_limit) ||
  2262. (netdev->flags & IFF_ALLMULTI)) {
  2263. /* Too many to filter perfectly -- accept all multicasts. */
  2264. ocp_data |= RCR_AM;
  2265. mc_filter[1] = 0xffffffff;
  2266. mc_filter[0] = 0xffffffff;
  2267. } else {
  2268. mc_filter[1] = 0;
  2269. mc_filter[0] = 0;
  2270. if (netdev->flags & IFF_MULTICAST) {
  2271. struct netdev_hw_addr *ha;
  2272. netdev_for_each_mc_addr(ha, netdev) {
  2273. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  2274. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2275. ocp_data |= RCR_AM;
  2276. }
  2277. }
  2278. }
  2279. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  2280. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  2281. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  2282. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2283. netif_wake_queue(netdev);
  2284. }
  2285. static netdev_features_t
  2286. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  2287. netdev_features_t features)
  2288. {
  2289. u32 mss = skb_shinfo(skb)->gso_size;
  2290. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  2291. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
  2292. skb_transport_offset(skb) > max_offset)
  2293. features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
  2294. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  2295. features &= ~NETIF_F_GSO_MASK;
  2296. return features;
  2297. }
  2298. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  2299. struct net_device *netdev)
  2300. {
  2301. struct r8152 *tp = netdev_priv(netdev);
  2302. skb_tx_timestamp(skb);
  2303. skb_queue_tail(&tp->tx_queue, skb);
  2304. if (!list_empty(&tp->tx_free)) {
  2305. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2306. set_bit(SCHEDULE_TASKLET, &tp->flags);
  2307. schedule_delayed_work(&tp->schedule, 0);
  2308. } else {
  2309. usb_mark_last_busy(tp->udev);
  2310. tasklet_schedule(&tp->tx_tl);
  2311. }
  2312. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  2313. netif_stop_queue(netdev);
  2314. }
  2315. return NETDEV_TX_OK;
  2316. }
  2317. static void r8152b_reset_packet_filter(struct r8152 *tp)
  2318. {
  2319. u32 ocp_data;
  2320. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  2321. ocp_data &= ~FMC_FCR_MCU_EN;
  2322. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  2323. ocp_data |= FMC_FCR_MCU_EN;
  2324. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  2325. }
  2326. static void rtl8152_nic_reset(struct r8152 *tp)
  2327. {
  2328. u32 ocp_data;
  2329. int i;
  2330. switch (tp->version) {
  2331. case RTL_TEST_01:
  2332. case RTL_VER_10:
  2333. case RTL_VER_11:
  2334. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  2335. ocp_data &= ~CR_TE;
  2336. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  2337. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
  2338. ocp_data &= ~BMU_RESET_EP_IN;
  2339. ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2340. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2341. ocp_data |= CDC_ECM_EN;
  2342. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2343. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  2344. ocp_data &= ~CR_RE;
  2345. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  2346. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
  2347. ocp_data |= BMU_RESET_EP_IN;
  2348. ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  2349. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2350. ocp_data &= ~CDC_ECM_EN;
  2351. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2352. break;
  2353. default:
  2354. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  2355. for (i = 0; i < 1000; i++) {
  2356. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2357. break;
  2358. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  2359. break;
  2360. usleep_range(100, 400);
  2361. }
  2362. break;
  2363. }
  2364. }
  2365. static void set_tx_qlen(struct r8152 *tp)
  2366. {
  2367. tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
  2368. }
  2369. static inline u16 rtl8152_get_speed(struct r8152 *tp)
  2370. {
  2371. return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  2372. }
  2373. static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
  2374. {
  2375. u32 ocp_data;
  2376. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  2377. if (enable)
  2378. ocp_data |= EEEP_CR_EEEP_TX;
  2379. else
  2380. ocp_data &= ~EEEP_CR_EEEP_TX;
  2381. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  2382. }
  2383. static void rtl_set_eee_plus(struct r8152 *tp)
  2384. {
  2385. if (rtl8152_get_speed(tp) & _10bps)
  2386. rtl_eee_plus_en(tp, true);
  2387. else
  2388. rtl_eee_plus_en(tp, false);
  2389. }
  2390. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  2391. {
  2392. u32 ocp_data;
  2393. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  2394. if (enable)
  2395. ocp_data |= RXDY_GATED_EN;
  2396. else
  2397. ocp_data &= ~RXDY_GATED_EN;
  2398. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  2399. }
  2400. static int rtl_start_rx(struct r8152 *tp)
  2401. {
  2402. struct rx_agg *agg, *agg_next;
  2403. struct list_head tmp_list;
  2404. unsigned long flags;
  2405. int ret = 0, i = 0;
  2406. INIT_LIST_HEAD(&tmp_list);
  2407. spin_lock_irqsave(&tp->rx_lock, flags);
  2408. INIT_LIST_HEAD(&tp->rx_done);
  2409. INIT_LIST_HEAD(&tp->rx_used);
  2410. list_splice_init(&tp->rx_info, &tmp_list);
  2411. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2412. list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
  2413. INIT_LIST_HEAD(&agg->list);
  2414. /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
  2415. if (++i > RTL8152_MAX_RX) {
  2416. spin_lock_irqsave(&tp->rx_lock, flags);
  2417. list_add_tail(&agg->list, &tp->rx_used);
  2418. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2419. } else if (unlikely(ret < 0)) {
  2420. spin_lock_irqsave(&tp->rx_lock, flags);
  2421. list_add_tail(&agg->list, &tp->rx_done);
  2422. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2423. } else {
  2424. ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
  2425. }
  2426. }
  2427. spin_lock_irqsave(&tp->rx_lock, flags);
  2428. WARN_ON(!list_empty(&tp->rx_info));
  2429. list_splice(&tmp_list, &tp->rx_info);
  2430. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2431. return ret;
  2432. }
  2433. static int rtl_stop_rx(struct r8152 *tp)
  2434. {
  2435. struct rx_agg *agg, *agg_next;
  2436. struct list_head tmp_list;
  2437. unsigned long flags;
  2438. INIT_LIST_HEAD(&tmp_list);
  2439. /* The usb_kill_urb() couldn't be used in atomic.
  2440. * Therefore, move the list of rx_info to a tmp one.
  2441. * Then, list_for_each_entry_safe could be used without
  2442. * spin lock.
  2443. */
  2444. spin_lock_irqsave(&tp->rx_lock, flags);
  2445. list_splice_init(&tp->rx_info, &tmp_list);
  2446. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2447. list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
  2448. /* At least RTL8152_MAX_RX rx_agg have the page_count being
  2449. * equal to 1, so the other ones could be freed safely.
  2450. */
  2451. if (page_count(agg->page) > 1)
  2452. free_rx_agg(tp, agg);
  2453. else
  2454. usb_kill_urb(agg->urb);
  2455. }
  2456. /* Move back the list of temp to the rx_info */
  2457. spin_lock_irqsave(&tp->rx_lock, flags);
  2458. WARN_ON(!list_empty(&tp->rx_info));
  2459. list_splice(&tmp_list, &tp->rx_info);
  2460. spin_unlock_irqrestore(&tp->rx_lock, flags);
  2461. while (!skb_queue_empty(&tp->rx_queue))
  2462. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  2463. return 0;
  2464. }
  2465. static void rtl_set_ifg(struct r8152 *tp, u16 speed)
  2466. {
  2467. u32 ocp_data;
  2468. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  2469. ocp_data &= ~IFG_MASK;
  2470. if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
  2471. ocp_data |= IFG_144NS;
  2472. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
  2473. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
  2474. ocp_data &= ~TX10MIDLE_EN;
  2475. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
  2476. } else {
  2477. ocp_data |= IFG_96NS;
  2478. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
  2479. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
  2480. ocp_data |= TX10MIDLE_EN;
  2481. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
  2482. }
  2483. }
  2484. static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
  2485. {
  2486. ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
  2487. OWN_UPDATE | OWN_CLEAR);
  2488. }
  2489. static int rtl_enable(struct r8152 *tp)
  2490. {
  2491. u32 ocp_data;
  2492. r8152b_reset_packet_filter(tp);
  2493. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  2494. ocp_data |= CR_RE | CR_TE;
  2495. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  2496. switch (tp->version) {
  2497. case RTL_VER_01:
  2498. case RTL_VER_02:
  2499. case RTL_VER_03:
  2500. case RTL_VER_04:
  2501. case RTL_VER_05:
  2502. case RTL_VER_06:
  2503. case RTL_VER_07:
  2504. break;
  2505. default:
  2506. r8153b_rx_agg_chg_indicate(tp);
  2507. break;
  2508. }
  2509. rxdy_gated_en(tp, false);
  2510. return 0;
  2511. }
  2512. static int rtl8152_enable(struct r8152 *tp)
  2513. {
  2514. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2515. return -ENODEV;
  2516. set_tx_qlen(tp);
  2517. rtl_set_eee_plus(tp);
  2518. return rtl_enable(tp);
  2519. }
  2520. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  2521. {
  2522. u32 ocp_data = tp->coalesce / 8;
  2523. switch (tp->version) {
  2524. case RTL_VER_03:
  2525. case RTL_VER_04:
  2526. case RTL_VER_05:
  2527. case RTL_VER_06:
  2528. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  2529. ocp_data);
  2530. break;
  2531. case RTL_VER_08:
  2532. case RTL_VER_09:
  2533. case RTL_VER_14:
  2534. /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
  2535. * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
  2536. */
  2537. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  2538. 128 / 8);
  2539. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
  2540. ocp_data);
  2541. break;
  2542. case RTL_VER_10:
  2543. case RTL_VER_11:
  2544. case RTL_VER_12:
  2545. case RTL_VER_13:
  2546. case RTL_VER_15:
  2547. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  2548. 640 / 8);
  2549. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
  2550. ocp_data);
  2551. break;
  2552. default:
  2553. break;
  2554. }
  2555. }
  2556. static void r8153_set_rx_early_size(struct r8152 *tp)
  2557. {
  2558. u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
  2559. switch (tp->version) {
  2560. case RTL_VER_03:
  2561. case RTL_VER_04:
  2562. case RTL_VER_05:
  2563. case RTL_VER_06:
  2564. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  2565. ocp_data / 4);
  2566. break;
  2567. case RTL_VER_08:
  2568. case RTL_VER_09:
  2569. case RTL_VER_14:
  2570. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  2571. ocp_data / 8);
  2572. break;
  2573. case RTL_TEST_01:
  2574. case RTL_VER_10:
  2575. case RTL_VER_11:
  2576. case RTL_VER_12:
  2577. case RTL_VER_13:
  2578. case RTL_VER_15:
  2579. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  2580. ocp_data / 8);
  2581. break;
  2582. default:
  2583. WARN_ON_ONCE(1);
  2584. break;
  2585. }
  2586. }
  2587. static int rtl8153_enable(struct r8152 *tp)
  2588. {
  2589. u32 ocp_data;
  2590. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2591. return -ENODEV;
  2592. set_tx_qlen(tp);
  2593. rtl_set_eee_plus(tp);
  2594. r8153_set_rx_early_timeout(tp);
  2595. r8153_set_rx_early_size(tp);
  2596. rtl_set_ifg(tp, rtl8152_get_speed(tp));
  2597. switch (tp->version) {
  2598. case RTL_VER_09:
  2599. case RTL_VER_14:
  2600. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
  2601. ocp_data &= ~FC_PATCH_TASK;
  2602. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  2603. usleep_range(1000, 2000);
  2604. ocp_data |= FC_PATCH_TASK;
  2605. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  2606. break;
  2607. default:
  2608. break;
  2609. }
  2610. return rtl_enable(tp);
  2611. }
  2612. static void rtl_disable(struct r8152 *tp)
  2613. {
  2614. u32 ocp_data;
  2615. int i;
  2616. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
  2617. rtl_drop_queued_tx(tp);
  2618. return;
  2619. }
  2620. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2621. ocp_data &= ~RCR_ACPT_ALL;
  2622. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2623. rtl_drop_queued_tx(tp);
  2624. for (i = 0; i < RTL8152_MAX_TX; i++)
  2625. usb_kill_urb(tp->tx_info[i].urb);
  2626. rxdy_gated_en(tp, true);
  2627. for (i = 0; i < 1000; i++) {
  2628. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2629. break;
  2630. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2631. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  2632. break;
  2633. usleep_range(1000, 2000);
  2634. }
  2635. for (i = 0; i < 1000; i++) {
  2636. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2637. break;
  2638. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  2639. break;
  2640. usleep_range(1000, 2000);
  2641. }
  2642. rtl_stop_rx(tp);
  2643. rtl8152_nic_reset(tp);
  2644. }
  2645. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  2646. {
  2647. u32 ocp_data;
  2648. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  2649. if (enable)
  2650. ocp_data |= POWER_CUT;
  2651. else
  2652. ocp_data &= ~POWER_CUT;
  2653. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  2654. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  2655. ocp_data &= ~RESUME_INDICATE;
  2656. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  2657. }
  2658. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  2659. {
  2660. u32 ocp_data;
  2661. switch (tp->version) {
  2662. case RTL_VER_01:
  2663. case RTL_VER_02:
  2664. case RTL_VER_03:
  2665. case RTL_VER_04:
  2666. case RTL_VER_05:
  2667. case RTL_VER_06:
  2668. case RTL_VER_07:
  2669. case RTL_VER_08:
  2670. case RTL_VER_09:
  2671. case RTL_VER_14:
  2672. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  2673. if (enable)
  2674. ocp_data |= CPCR_RX_VLAN;
  2675. else
  2676. ocp_data &= ~CPCR_RX_VLAN;
  2677. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  2678. break;
  2679. case RTL_TEST_01:
  2680. case RTL_VER_10:
  2681. case RTL_VER_11:
  2682. case RTL_VER_12:
  2683. case RTL_VER_13:
  2684. case RTL_VER_15:
  2685. default:
  2686. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
  2687. if (enable)
  2688. ocp_data |= OUTER_VLAN | INNER_VLAN;
  2689. else
  2690. ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
  2691. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
  2692. break;
  2693. }
  2694. }
  2695. static int rtl8152_set_features(struct net_device *dev,
  2696. netdev_features_t features)
  2697. {
  2698. netdev_features_t changed = features ^ dev->features;
  2699. struct r8152 *tp = netdev_priv(dev);
  2700. int ret;
  2701. ret = usb_autopm_get_interface(tp->intf);
  2702. if (ret < 0)
  2703. goto out;
  2704. mutex_lock(&tp->control);
  2705. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  2706. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  2707. rtl_rx_vlan_en(tp, true);
  2708. else
  2709. rtl_rx_vlan_en(tp, false);
  2710. }
  2711. mutex_unlock(&tp->control);
  2712. usb_autopm_put_interface(tp->intf);
  2713. out:
  2714. return ret;
  2715. }
  2716. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  2717. static u32 __rtl_get_wol(struct r8152 *tp)
  2718. {
  2719. u32 ocp_data;
  2720. u32 wolopts = 0;
  2721. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2722. if (ocp_data & LINK_ON_WAKE_EN)
  2723. wolopts |= WAKE_PHY;
  2724. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  2725. if (ocp_data & UWF_EN)
  2726. wolopts |= WAKE_UCAST;
  2727. if (ocp_data & BWF_EN)
  2728. wolopts |= WAKE_BCAST;
  2729. if (ocp_data & MWF_EN)
  2730. wolopts |= WAKE_MCAST;
  2731. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  2732. if (ocp_data & MAGIC_EN)
  2733. wolopts |= WAKE_MAGIC;
  2734. return wolopts;
  2735. }
  2736. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  2737. {
  2738. u32 ocp_data;
  2739. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  2740. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  2741. ocp_data &= ~LINK_ON_WAKE_EN;
  2742. if (wolopts & WAKE_PHY)
  2743. ocp_data |= LINK_ON_WAKE_EN;
  2744. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  2745. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  2746. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
  2747. if (wolopts & WAKE_UCAST)
  2748. ocp_data |= UWF_EN;
  2749. if (wolopts & WAKE_BCAST)
  2750. ocp_data |= BWF_EN;
  2751. if (wolopts & WAKE_MCAST)
  2752. ocp_data |= MWF_EN;
  2753. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  2754. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2755. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  2756. ocp_data &= ~MAGIC_EN;
  2757. if (wolopts & WAKE_MAGIC)
  2758. ocp_data |= MAGIC_EN;
  2759. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  2760. if (wolopts & WAKE_ANY)
  2761. device_set_wakeup_enable(&tp->udev->dev, true);
  2762. else
  2763. device_set_wakeup_enable(&tp->udev->dev, false);
  2764. }
  2765. static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
  2766. {
  2767. u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
  2768. /* MAC clock speed down */
  2769. if (enable)
  2770. ocp_data |= MAC_CLK_SPDWN_EN;
  2771. else
  2772. ocp_data &= ~MAC_CLK_SPDWN_EN;
  2773. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
  2774. }
  2775. static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
  2776. {
  2777. u32 ocp_data;
  2778. /* MAC clock speed down */
  2779. if (enable) {
  2780. /* aldps_spdwn_ratio, tp10_spdwn_ratio */
  2781. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
  2782. 0x0403);
  2783. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
  2784. ocp_data &= ~EEE_SPDWN_RATIO_MASK;
  2785. ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
  2786. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
  2787. } else {
  2788. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
  2789. ocp_data &= ~MAC_CLK_SPDWN_EN;
  2790. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
  2791. }
  2792. }
  2793. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2794. {
  2795. u8 u1u2[8];
  2796. if (enable)
  2797. memset(u1u2, 0xff, sizeof(u1u2));
  2798. else
  2799. memset(u1u2, 0x00, sizeof(u1u2));
  2800. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2801. }
  2802. static void r8153b_u1u2en(struct r8152 *tp, bool enable)
  2803. {
  2804. u32 ocp_data;
  2805. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
  2806. if (enable)
  2807. ocp_data |= LPM_U1U2_EN;
  2808. else
  2809. ocp_data &= ~LPM_U1U2_EN;
  2810. ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
  2811. }
  2812. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2813. {
  2814. u32 ocp_data;
  2815. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2816. if (enable)
  2817. ocp_data |= U2P3_ENABLE;
  2818. else
  2819. ocp_data &= ~U2P3_ENABLE;
  2820. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2821. }
  2822. static void r8153b_ups_flags(struct r8152 *tp)
  2823. {
  2824. u32 ups_flags = 0;
  2825. if (tp->ups_info.green)
  2826. ups_flags |= UPS_FLAGS_EN_GREEN;
  2827. if (tp->ups_info.aldps)
  2828. ups_flags |= UPS_FLAGS_EN_ALDPS;
  2829. if (tp->ups_info.eee)
  2830. ups_flags |= UPS_FLAGS_EN_EEE;
  2831. if (tp->ups_info.flow_control)
  2832. ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
  2833. if (tp->ups_info.eee_ckdiv)
  2834. ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
  2835. if (tp->ups_info.eee_cmod_lv)
  2836. ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
  2837. if (tp->ups_info.r_tune)
  2838. ups_flags |= UPS_FLAGS_R_TUNE;
  2839. if (tp->ups_info._10m_ckdiv)
  2840. ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
  2841. if (tp->ups_info.eee_plloff_100)
  2842. ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
  2843. if (tp->ups_info.eee_plloff_giga)
  2844. ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
  2845. if (tp->ups_info._250m_ckdiv)
  2846. ups_flags |= UPS_FLAGS_250M_CKDIV;
  2847. if (tp->ups_info.ctap_short_off)
  2848. ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
  2849. switch (tp->ups_info.speed_duplex) {
  2850. case NWAY_10M_HALF:
  2851. ups_flags |= ups_flags_speed(1);
  2852. break;
  2853. case NWAY_10M_FULL:
  2854. ups_flags |= ups_flags_speed(2);
  2855. break;
  2856. case NWAY_100M_HALF:
  2857. ups_flags |= ups_flags_speed(3);
  2858. break;
  2859. case NWAY_100M_FULL:
  2860. ups_flags |= ups_flags_speed(4);
  2861. break;
  2862. case NWAY_1000M_FULL:
  2863. ups_flags |= ups_flags_speed(5);
  2864. break;
  2865. case FORCE_10M_HALF:
  2866. ups_flags |= ups_flags_speed(6);
  2867. break;
  2868. case FORCE_10M_FULL:
  2869. ups_flags |= ups_flags_speed(7);
  2870. break;
  2871. case FORCE_100M_HALF:
  2872. ups_flags |= ups_flags_speed(8);
  2873. break;
  2874. case FORCE_100M_FULL:
  2875. ups_flags |= ups_flags_speed(9);
  2876. break;
  2877. default:
  2878. break;
  2879. }
  2880. ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
  2881. }
  2882. static void r8156_ups_flags(struct r8152 *tp)
  2883. {
  2884. u32 ups_flags = 0;
  2885. if (tp->ups_info.green)
  2886. ups_flags |= UPS_FLAGS_EN_GREEN;
  2887. if (tp->ups_info.aldps)
  2888. ups_flags |= UPS_FLAGS_EN_ALDPS;
  2889. if (tp->ups_info.eee)
  2890. ups_flags |= UPS_FLAGS_EN_EEE;
  2891. if (tp->ups_info.flow_control)
  2892. ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
  2893. if (tp->ups_info.eee_ckdiv)
  2894. ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
  2895. if (tp->ups_info._10m_ckdiv)
  2896. ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
  2897. if (tp->ups_info.eee_plloff_100)
  2898. ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
  2899. if (tp->ups_info.eee_plloff_giga)
  2900. ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
  2901. if (tp->ups_info._250m_ckdiv)
  2902. ups_flags |= UPS_FLAGS_250M_CKDIV;
  2903. switch (tp->ups_info.speed_duplex) {
  2904. case FORCE_10M_HALF:
  2905. ups_flags |= ups_flags_speed(0);
  2906. break;
  2907. case FORCE_10M_FULL:
  2908. ups_flags |= ups_flags_speed(1);
  2909. break;
  2910. case FORCE_100M_HALF:
  2911. ups_flags |= ups_flags_speed(2);
  2912. break;
  2913. case FORCE_100M_FULL:
  2914. ups_flags |= ups_flags_speed(3);
  2915. break;
  2916. case NWAY_10M_HALF:
  2917. ups_flags |= ups_flags_speed(4);
  2918. break;
  2919. case NWAY_10M_FULL:
  2920. ups_flags |= ups_flags_speed(5);
  2921. break;
  2922. case NWAY_100M_HALF:
  2923. ups_flags |= ups_flags_speed(6);
  2924. break;
  2925. case NWAY_100M_FULL:
  2926. ups_flags |= ups_flags_speed(7);
  2927. break;
  2928. case NWAY_1000M_FULL:
  2929. ups_flags |= ups_flags_speed(8);
  2930. break;
  2931. case NWAY_2500M_FULL:
  2932. ups_flags |= ups_flags_speed(9);
  2933. break;
  2934. default:
  2935. break;
  2936. }
  2937. switch (tp->ups_info.lite_mode) {
  2938. case 1:
  2939. ups_flags |= 0 << 5;
  2940. break;
  2941. case 2:
  2942. ups_flags |= 2 << 5;
  2943. break;
  2944. case 0:
  2945. default:
  2946. ups_flags |= 1 << 5;
  2947. break;
  2948. }
  2949. ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
  2950. }
  2951. static void rtl_green_en(struct r8152 *tp, bool enable)
  2952. {
  2953. u16 data;
  2954. data = sram_read(tp, SRAM_GREEN_CFG);
  2955. if (enable)
  2956. data |= GREEN_ETH_EN;
  2957. else
  2958. data &= ~GREEN_ETH_EN;
  2959. sram_write(tp, SRAM_GREEN_CFG, data);
  2960. tp->ups_info.green = enable;
  2961. }
  2962. static void r8153b_green_en(struct r8152 *tp, bool enable)
  2963. {
  2964. if (enable) {
  2965. sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
  2966. sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
  2967. sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
  2968. } else {
  2969. sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
  2970. sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
  2971. sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
  2972. }
  2973. rtl_green_en(tp, true);
  2974. }
  2975. static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
  2976. {
  2977. u16 data;
  2978. int i;
  2979. for (i = 0; i < 500; i++) {
  2980. data = ocp_reg_read(tp, OCP_PHY_STATUS);
  2981. data &= PHY_STAT_MASK;
  2982. if (desired) {
  2983. if (data == desired)
  2984. break;
  2985. } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
  2986. data == PHY_STAT_EXT_INIT) {
  2987. break;
  2988. }
  2989. msleep(20);
  2990. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  2991. break;
  2992. }
  2993. return data;
  2994. }
  2995. static void r8153b_ups_en(struct r8152 *tp, bool enable)
  2996. {
  2997. u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2998. if (enable) {
  2999. r8153b_ups_flags(tp);
  3000. ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
  3001. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3002. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  3003. ocp_data |= UPS_FORCE_PWR_DOWN;
  3004. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  3005. } else {
  3006. ocp_data &= ~(UPS_EN | USP_PREWAKE);
  3007. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3008. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  3009. ocp_data &= ~UPS_FORCE_PWR_DOWN;
  3010. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  3011. if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
  3012. int i;
  3013. for (i = 0; i < 500; i++) {
  3014. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  3015. return;
  3016. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  3017. AUTOLOAD_DONE)
  3018. break;
  3019. msleep(20);
  3020. }
  3021. tp->rtl_ops.hw_phy_cfg(tp);
  3022. rtl8152_set_speed(tp, tp->autoneg, tp->speed,
  3023. tp->duplex, tp->advertising);
  3024. }
  3025. }
  3026. }
  3027. static void r8153c_ups_en(struct r8152 *tp, bool enable)
  3028. {
  3029. u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
  3030. if (enable) {
  3031. r8153b_ups_flags(tp);
  3032. ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
  3033. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3034. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  3035. ocp_data |= UPS_FORCE_PWR_DOWN;
  3036. ocp_data &= ~BIT(7);
  3037. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  3038. } else {
  3039. ocp_data &= ~(UPS_EN | USP_PREWAKE);
  3040. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3041. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  3042. ocp_data &= ~UPS_FORCE_PWR_DOWN;
  3043. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  3044. if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
  3045. int i;
  3046. for (i = 0; i < 500; i++) {
  3047. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  3048. return;
  3049. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  3050. AUTOLOAD_DONE)
  3051. break;
  3052. msleep(20);
  3053. }
  3054. tp->rtl_ops.hw_phy_cfg(tp);
  3055. rtl8152_set_speed(tp, tp->autoneg, tp->speed,
  3056. tp->duplex, tp->advertising);
  3057. }
  3058. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  3059. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  3060. ocp_data |= BIT(8);
  3061. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  3062. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  3063. }
  3064. }
  3065. static void r8156_ups_en(struct r8152 *tp, bool enable)
  3066. {
  3067. u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
  3068. if (enable) {
  3069. r8156_ups_flags(tp);
  3070. ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
  3071. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3072. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  3073. ocp_data |= UPS_FORCE_PWR_DOWN;
  3074. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  3075. switch (tp->version) {
  3076. case RTL_VER_13:
  3077. case RTL_VER_15:
  3078. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
  3079. ocp_data &= ~OOBS_POLLING;
  3080. ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
  3081. break;
  3082. default:
  3083. break;
  3084. }
  3085. } else {
  3086. ocp_data &= ~(UPS_EN | USP_PREWAKE);
  3087. ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3088. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  3089. ocp_data &= ~UPS_FORCE_PWR_DOWN;
  3090. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  3091. if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
  3092. tp->rtl_ops.hw_phy_cfg(tp);
  3093. rtl8152_set_speed(tp, tp->autoneg, tp->speed,
  3094. tp->duplex, tp->advertising);
  3095. }
  3096. }
  3097. }
  3098. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  3099. {
  3100. u32 ocp_data;
  3101. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  3102. if (enable)
  3103. ocp_data |= PWR_EN | PHASE2_EN;
  3104. else
  3105. ocp_data &= ~(PWR_EN | PHASE2_EN);
  3106. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3107. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  3108. ocp_data &= ~PCUT_STATUS;
  3109. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  3110. }
  3111. static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
  3112. {
  3113. u32 ocp_data;
  3114. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  3115. if (enable)
  3116. ocp_data |= PWR_EN | PHASE2_EN;
  3117. else
  3118. ocp_data &= ~PWR_EN;
  3119. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  3120. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  3121. ocp_data &= ~PCUT_STATUS;
  3122. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  3123. }
  3124. static void r8153_queue_wake(struct r8152 *tp, bool enable)
  3125. {
  3126. u32 ocp_data;
  3127. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
  3128. if (enable)
  3129. ocp_data |= UPCOMING_RUNTIME_D3;
  3130. else
  3131. ocp_data &= ~UPCOMING_RUNTIME_D3;
  3132. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
  3133. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
  3134. ocp_data &= ~LINK_CHG_EVENT;
  3135. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
  3136. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  3137. ocp_data &= ~LINK_CHANGE_FLAG;
  3138. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  3139. }
  3140. static bool rtl_can_wakeup(struct r8152 *tp)
  3141. {
  3142. struct usb_device *udev = tp->udev;
  3143. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  3144. }
  3145. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  3146. {
  3147. if (enable) {
  3148. u32 ocp_data;
  3149. __rtl_set_wol(tp, WAKE_ANY);
  3150. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  3151. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  3152. ocp_data |= LINK_OFF_WAKE_EN;
  3153. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  3154. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  3155. } else {
  3156. u32 ocp_data;
  3157. __rtl_set_wol(tp, tp->saved_wolopts);
  3158. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  3159. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  3160. ocp_data &= ~LINK_OFF_WAKE_EN;
  3161. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  3162. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  3163. }
  3164. }
  3165. static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
  3166. {
  3167. if (enable) {
  3168. r8153_u1u2en(tp, false);
  3169. r8153_u2p3en(tp, false);
  3170. rtl_runtime_suspend_enable(tp, true);
  3171. } else {
  3172. rtl_runtime_suspend_enable(tp, false);
  3173. switch (tp->version) {
  3174. case RTL_VER_03:
  3175. case RTL_VER_04:
  3176. break;
  3177. case RTL_VER_05:
  3178. case RTL_VER_06:
  3179. default:
  3180. r8153_u2p3en(tp, true);
  3181. break;
  3182. }
  3183. r8153_u1u2en(tp, true);
  3184. }
  3185. }
  3186. static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
  3187. {
  3188. if (enable) {
  3189. r8153_queue_wake(tp, true);
  3190. r8153b_u1u2en(tp, false);
  3191. r8153_u2p3en(tp, false);
  3192. rtl_runtime_suspend_enable(tp, true);
  3193. r8153b_ups_en(tp, true);
  3194. } else {
  3195. r8153b_ups_en(tp, false);
  3196. r8153_queue_wake(tp, false);
  3197. rtl_runtime_suspend_enable(tp, false);
  3198. if (tp->udev->speed >= USB_SPEED_SUPER)
  3199. r8153b_u1u2en(tp, true);
  3200. }
  3201. }
  3202. static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
  3203. {
  3204. if (enable) {
  3205. r8153_queue_wake(tp, true);
  3206. r8153b_u1u2en(tp, false);
  3207. r8153_u2p3en(tp, false);
  3208. rtl_runtime_suspend_enable(tp, true);
  3209. r8153c_ups_en(tp, true);
  3210. } else {
  3211. r8153c_ups_en(tp, false);
  3212. r8153_queue_wake(tp, false);
  3213. rtl_runtime_suspend_enable(tp, false);
  3214. r8153b_u1u2en(tp, true);
  3215. }
  3216. }
  3217. static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
  3218. {
  3219. if (enable) {
  3220. r8153_queue_wake(tp, true);
  3221. r8153b_u1u2en(tp, false);
  3222. r8153_u2p3en(tp, false);
  3223. rtl_runtime_suspend_enable(tp, true);
  3224. } else {
  3225. r8153_queue_wake(tp, false);
  3226. rtl_runtime_suspend_enable(tp, false);
  3227. r8153_u2p3en(tp, true);
  3228. if (tp->udev->speed >= USB_SPEED_SUPER)
  3229. r8153b_u1u2en(tp, true);
  3230. }
  3231. }
  3232. static void r8153_teredo_off(struct r8152 *tp)
  3233. {
  3234. u32 ocp_data;
  3235. switch (tp->version) {
  3236. case RTL_VER_01:
  3237. case RTL_VER_02:
  3238. case RTL_VER_03:
  3239. case RTL_VER_04:
  3240. case RTL_VER_05:
  3241. case RTL_VER_06:
  3242. case RTL_VER_07:
  3243. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  3244. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
  3245. OOB_TEREDO_EN);
  3246. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  3247. break;
  3248. case RTL_VER_08:
  3249. case RTL_VER_09:
  3250. case RTL_TEST_01:
  3251. case RTL_VER_10:
  3252. case RTL_VER_11:
  3253. case RTL_VER_12:
  3254. case RTL_VER_13:
  3255. case RTL_VER_14:
  3256. case RTL_VER_15:
  3257. default:
  3258. /* The bit 0 ~ 7 are relative with teredo settings. They are
  3259. * W1C (write 1 to clear), so set all 1 to disable it.
  3260. */
  3261. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
  3262. break;
  3263. }
  3264. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  3265. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  3266. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  3267. }
  3268. static void rtl_reset_bmu(struct r8152 *tp)
  3269. {
  3270. u32 ocp_data;
  3271. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
  3272. ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
  3273. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  3274. ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
  3275. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  3276. }
  3277. /* Clear the bp to stop the firmware before loading a new one */
  3278. static void rtl_clear_bp(struct r8152 *tp, u16 type)
  3279. {
  3280. switch (tp->version) {
  3281. case RTL_VER_01:
  3282. case RTL_VER_02:
  3283. case RTL_VER_07:
  3284. break;
  3285. case RTL_VER_03:
  3286. case RTL_VER_04:
  3287. case RTL_VER_05:
  3288. case RTL_VER_06:
  3289. ocp_write_byte(tp, type, PLA_BP_EN, 0);
  3290. break;
  3291. case RTL_VER_14:
  3292. ocp_write_word(tp, type, USB_BP2_EN, 0);
  3293. ocp_write_word(tp, type, USB_BP_8, 0);
  3294. ocp_write_word(tp, type, USB_BP_9, 0);
  3295. ocp_write_word(tp, type, USB_BP_10, 0);
  3296. ocp_write_word(tp, type, USB_BP_11, 0);
  3297. ocp_write_word(tp, type, USB_BP_12, 0);
  3298. ocp_write_word(tp, type, USB_BP_13, 0);
  3299. ocp_write_word(tp, type, USB_BP_14, 0);
  3300. ocp_write_word(tp, type, USB_BP_15, 0);
  3301. break;
  3302. case RTL_VER_08:
  3303. case RTL_VER_09:
  3304. case RTL_VER_10:
  3305. case RTL_VER_11:
  3306. case RTL_VER_12:
  3307. case RTL_VER_13:
  3308. case RTL_VER_15:
  3309. default:
  3310. if (type == MCU_TYPE_USB) {
  3311. ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
  3312. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
  3313. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
  3314. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
  3315. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
  3316. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
  3317. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
  3318. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
  3319. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
  3320. } else {
  3321. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
  3322. }
  3323. break;
  3324. }
  3325. ocp_write_word(tp, type, PLA_BP_0, 0);
  3326. ocp_write_word(tp, type, PLA_BP_1, 0);
  3327. ocp_write_word(tp, type, PLA_BP_2, 0);
  3328. ocp_write_word(tp, type, PLA_BP_3, 0);
  3329. ocp_write_word(tp, type, PLA_BP_4, 0);
  3330. ocp_write_word(tp, type, PLA_BP_5, 0);
  3331. ocp_write_word(tp, type, PLA_BP_6, 0);
  3332. ocp_write_word(tp, type, PLA_BP_7, 0);
  3333. /* wait 3 ms to make sure the firmware is stopped */
  3334. usleep_range(3000, 6000);
  3335. ocp_write_word(tp, type, PLA_BP_BA, 0);
  3336. }
  3337. static inline void rtl_reset_ocp_base(struct r8152 *tp)
  3338. {
  3339. tp->ocp_base = -1;
  3340. }
  3341. static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
  3342. {
  3343. u16 data, check;
  3344. int i;
  3345. data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
  3346. if (request) {
  3347. data |= PATCH_REQUEST;
  3348. check = 0;
  3349. } else {
  3350. data &= ~PATCH_REQUEST;
  3351. check = PATCH_READY;
  3352. }
  3353. ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
  3354. for (i = 0; wait && i < 5000; i++) {
  3355. u32 ocp_data;
  3356. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  3357. return -ENODEV;
  3358. usleep_range(1000, 2000);
  3359. ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
  3360. if ((ocp_data & PATCH_READY) ^ check)
  3361. break;
  3362. }
  3363. if (request && wait &&
  3364. !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
  3365. dev_err(&tp->intf->dev, "PHY patch request fail\n");
  3366. rtl_phy_patch_request(tp, false, false);
  3367. return -ETIME;
  3368. } else {
  3369. return 0;
  3370. }
  3371. }
  3372. static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
  3373. {
  3374. if (patch_key && key_addr) {
  3375. sram_write(tp, key_addr, patch_key);
  3376. sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
  3377. } else if (key_addr) {
  3378. u16 data;
  3379. sram_write(tp, 0x0000, 0x0000);
  3380. data = ocp_reg_read(tp, OCP_PHY_LOCK);
  3381. data &= ~PATCH_LOCK;
  3382. ocp_reg_write(tp, OCP_PHY_LOCK, data);
  3383. sram_write(tp, key_addr, 0x0000);
  3384. } else {
  3385. WARN_ON_ONCE(1);
  3386. }
  3387. }
  3388. static int
  3389. rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
  3390. {
  3391. if (rtl_phy_patch_request(tp, true, wait))
  3392. return -ETIME;
  3393. rtl_patch_key_set(tp, key_addr, patch_key);
  3394. return 0;
  3395. }
  3396. static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
  3397. {
  3398. rtl_patch_key_set(tp, key_addr, 0);
  3399. rtl_phy_patch_request(tp, false, wait);
  3400. return 0;
  3401. }
  3402. static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
  3403. {
  3404. u16 fw_offset;
  3405. u32 length;
  3406. bool rc = false;
  3407. switch (tp->version) {
  3408. case RTL_VER_01:
  3409. case RTL_VER_02:
  3410. case RTL_VER_03:
  3411. case RTL_VER_04:
  3412. case RTL_VER_05:
  3413. case RTL_VER_06:
  3414. case RTL_VER_07:
  3415. case RTL_VER_08:
  3416. case RTL_VER_09:
  3417. case RTL_VER_10:
  3418. case RTL_VER_11:
  3419. case RTL_VER_12:
  3420. case RTL_VER_14:
  3421. goto out;
  3422. case RTL_VER_13:
  3423. case RTL_VER_15:
  3424. default:
  3425. break;
  3426. }
  3427. fw_offset = __le16_to_cpu(phy->fw_offset);
  3428. length = __le32_to_cpu(phy->blk_hdr.length);
  3429. if (fw_offset < sizeof(*phy) || length <= fw_offset) {
  3430. dev_err(&tp->intf->dev, "invalid fw_offset\n");
  3431. goto out;
  3432. }
  3433. length -= fw_offset;
  3434. if (length & 3) {
  3435. dev_err(&tp->intf->dev, "invalid block length\n");
  3436. goto out;
  3437. }
  3438. if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
  3439. dev_err(&tp->intf->dev, "invalid register to load firmware\n");
  3440. goto out;
  3441. }
  3442. rc = true;
  3443. out:
  3444. return rc;
  3445. }
  3446. static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
  3447. {
  3448. bool rc = false;
  3449. switch (tp->version) {
  3450. case RTL_VER_10:
  3451. case RTL_VER_11:
  3452. case RTL_VER_12:
  3453. case RTL_VER_13:
  3454. case RTL_VER_15:
  3455. break;
  3456. default:
  3457. goto out;
  3458. }
  3459. if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
  3460. dev_err(&tp->intf->dev, "invalid block length\n");
  3461. goto out;
  3462. }
  3463. if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
  3464. dev_err(&tp->intf->dev, "invalid phy ver addr\n");
  3465. goto out;
  3466. }
  3467. rc = true;
  3468. out:
  3469. return rc;
  3470. }
  3471. static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
  3472. {
  3473. bool rc = false;
  3474. switch (tp->version) {
  3475. case RTL_VER_10:
  3476. case RTL_VER_11:
  3477. case RTL_VER_12:
  3478. case RTL_VER_13:
  3479. case RTL_VER_15:
  3480. break;
  3481. default:
  3482. goto out;
  3483. }
  3484. if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
  3485. dev_err(&tp->intf->dev, "invalid block length\n");
  3486. goto out;
  3487. }
  3488. if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
  3489. __le16_to_cpu(fix->setting.data) != BIT(7)) {
  3490. dev_err(&tp->intf->dev, "invalid phy fixup\n");
  3491. goto out;
  3492. }
  3493. rc = true;
  3494. out:
  3495. return rc;
  3496. }
  3497. static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
  3498. {
  3499. u16 fw_offset;
  3500. u32 length;
  3501. bool rc = false;
  3502. switch (tp->version) {
  3503. case RTL_VER_10:
  3504. case RTL_VER_11:
  3505. case RTL_VER_12:
  3506. case RTL_VER_13:
  3507. case RTL_VER_15:
  3508. break;
  3509. default:
  3510. goto out;
  3511. }
  3512. fw_offset = __le16_to_cpu(phy->fw_offset);
  3513. length = __le32_to_cpu(phy->blk_hdr.length);
  3514. if (fw_offset < sizeof(*phy) || length <= fw_offset) {
  3515. dev_err(&tp->intf->dev, "invalid fw_offset\n");
  3516. goto out;
  3517. }
  3518. length -= fw_offset;
  3519. if (length & 1) {
  3520. dev_err(&tp->intf->dev, "invalid block length\n");
  3521. goto out;
  3522. }
  3523. if (phy->pre_num > 2) {
  3524. dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
  3525. goto out;
  3526. }
  3527. if (phy->bp_num > 8) {
  3528. dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
  3529. goto out;
  3530. }
  3531. rc = true;
  3532. out:
  3533. return rc;
  3534. }
  3535. static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
  3536. {
  3537. u32 length;
  3538. u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
  3539. bool rc = false;
  3540. switch (tp->version) {
  3541. case RTL_VER_04:
  3542. case RTL_VER_05:
  3543. case RTL_VER_06:
  3544. fw_reg = 0xa014;
  3545. ba_reg = 0xa012;
  3546. patch_en_addr = 0xa01a;
  3547. mode_reg = 0xb820;
  3548. bp_start = 0xa000;
  3549. break;
  3550. default:
  3551. goto out;
  3552. }
  3553. fw_offset = __le16_to_cpu(phy->fw_offset);
  3554. if (fw_offset < sizeof(*phy)) {
  3555. dev_err(&tp->intf->dev, "fw_offset too small\n");
  3556. goto out;
  3557. }
  3558. length = __le32_to_cpu(phy->blk_hdr.length);
  3559. if (length < fw_offset) {
  3560. dev_err(&tp->intf->dev, "invalid fw_offset\n");
  3561. goto out;
  3562. }
  3563. length -= __le16_to_cpu(phy->fw_offset);
  3564. if (!length || (length & 1)) {
  3565. dev_err(&tp->intf->dev, "invalid block length\n");
  3566. goto out;
  3567. }
  3568. if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
  3569. dev_err(&tp->intf->dev, "invalid register to load firmware\n");
  3570. goto out;
  3571. }
  3572. if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
  3573. dev_err(&tp->intf->dev, "invalid base address register\n");
  3574. goto out;
  3575. }
  3576. if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
  3577. dev_err(&tp->intf->dev,
  3578. "invalid patch mode enabled register\n");
  3579. goto out;
  3580. }
  3581. if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
  3582. dev_err(&tp->intf->dev,
  3583. "invalid register to switch the mode\n");
  3584. goto out;
  3585. }
  3586. if (__le16_to_cpu(phy->bp_start) != bp_start) {
  3587. dev_err(&tp->intf->dev,
  3588. "invalid start register of break point\n");
  3589. goto out;
  3590. }
  3591. if (__le16_to_cpu(phy->bp_num) > 4) {
  3592. dev_err(&tp->intf->dev, "invalid break point number\n");
  3593. goto out;
  3594. }
  3595. rc = true;
  3596. out:
  3597. return rc;
  3598. }
  3599. static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
  3600. {
  3601. u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
  3602. bool rc = false;
  3603. u32 length, type;
  3604. int i, max_bp;
  3605. type = __le32_to_cpu(mac->blk_hdr.type);
  3606. if (type == RTL_FW_PLA) {
  3607. switch (tp->version) {
  3608. case RTL_VER_01:
  3609. case RTL_VER_02:
  3610. case RTL_VER_07:
  3611. fw_reg = 0xf800;
  3612. bp_ba_addr = PLA_BP_BA;
  3613. bp_en_addr = 0;
  3614. bp_start = PLA_BP_0;
  3615. max_bp = 8;
  3616. break;
  3617. case RTL_VER_03:
  3618. case RTL_VER_04:
  3619. case RTL_VER_05:
  3620. case RTL_VER_06:
  3621. case RTL_VER_08:
  3622. case RTL_VER_09:
  3623. case RTL_VER_11:
  3624. case RTL_VER_12:
  3625. case RTL_VER_13:
  3626. case RTL_VER_15:
  3627. fw_reg = 0xf800;
  3628. bp_ba_addr = PLA_BP_BA;
  3629. bp_en_addr = PLA_BP_EN;
  3630. bp_start = PLA_BP_0;
  3631. max_bp = 8;
  3632. break;
  3633. case RTL_VER_14:
  3634. fw_reg = 0xf800;
  3635. bp_ba_addr = PLA_BP_BA;
  3636. bp_en_addr = USB_BP2_EN;
  3637. bp_start = PLA_BP_0;
  3638. max_bp = 16;
  3639. break;
  3640. default:
  3641. goto out;
  3642. }
  3643. } else if (type == RTL_FW_USB) {
  3644. switch (tp->version) {
  3645. case RTL_VER_03:
  3646. case RTL_VER_04:
  3647. case RTL_VER_05:
  3648. case RTL_VER_06:
  3649. fw_reg = 0xf800;
  3650. bp_ba_addr = USB_BP_BA;
  3651. bp_en_addr = USB_BP_EN;
  3652. bp_start = USB_BP_0;
  3653. max_bp = 8;
  3654. break;
  3655. case RTL_VER_08:
  3656. case RTL_VER_09:
  3657. case RTL_VER_11:
  3658. case RTL_VER_12:
  3659. case RTL_VER_13:
  3660. case RTL_VER_14:
  3661. case RTL_VER_15:
  3662. fw_reg = 0xe600;
  3663. bp_ba_addr = USB_BP_BA;
  3664. bp_en_addr = USB_BP2_EN;
  3665. bp_start = USB_BP_0;
  3666. max_bp = 16;
  3667. break;
  3668. case RTL_VER_01:
  3669. case RTL_VER_02:
  3670. case RTL_VER_07:
  3671. default:
  3672. goto out;
  3673. }
  3674. } else {
  3675. goto out;
  3676. }
  3677. fw_offset = __le16_to_cpu(mac->fw_offset);
  3678. if (fw_offset < sizeof(*mac)) {
  3679. dev_err(&tp->intf->dev, "fw_offset too small\n");
  3680. goto out;
  3681. }
  3682. length = __le32_to_cpu(mac->blk_hdr.length);
  3683. if (length < fw_offset) {
  3684. dev_err(&tp->intf->dev, "invalid fw_offset\n");
  3685. goto out;
  3686. }
  3687. length -= fw_offset;
  3688. if (length < 4 || (length & 3)) {
  3689. dev_err(&tp->intf->dev, "invalid block length\n");
  3690. goto out;
  3691. }
  3692. if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
  3693. dev_err(&tp->intf->dev, "invalid register to load firmware\n");
  3694. goto out;
  3695. }
  3696. if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
  3697. dev_err(&tp->intf->dev, "invalid base address register\n");
  3698. goto out;
  3699. }
  3700. if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
  3701. dev_err(&tp->intf->dev, "invalid enabled mask register\n");
  3702. goto out;
  3703. }
  3704. if (__le16_to_cpu(mac->bp_start) != bp_start) {
  3705. dev_err(&tp->intf->dev,
  3706. "invalid start register of break point\n");
  3707. goto out;
  3708. }
  3709. if (__le16_to_cpu(mac->bp_num) > max_bp) {
  3710. dev_err(&tp->intf->dev, "invalid break point number\n");
  3711. goto out;
  3712. }
  3713. for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
  3714. if (mac->bp[i]) {
  3715. dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
  3716. goto out;
  3717. }
  3718. }
  3719. rc = true;
  3720. out:
  3721. return rc;
  3722. }
  3723. /* Verify the checksum for the firmware file. It is calculated from the version
  3724. * field to the end of the file. Compare the result with the checksum field to
  3725. * make sure the file is correct.
  3726. */
  3727. static long rtl8152_fw_verify_checksum(struct r8152 *tp,
  3728. struct fw_header *fw_hdr, size_t size)
  3729. {
  3730. unsigned char checksum[sizeof(fw_hdr->checksum)];
  3731. struct crypto_shash *alg;
  3732. struct shash_desc *sdesc;
  3733. size_t len;
  3734. long rc;
  3735. alg = crypto_alloc_shash("sha256", 0, 0);
  3736. if (IS_ERR(alg)) {
  3737. rc = PTR_ERR(alg);
  3738. goto out;
  3739. }
  3740. if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
  3741. rc = -EFAULT;
  3742. dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
  3743. crypto_shash_digestsize(alg));
  3744. goto free_shash;
  3745. }
  3746. len = sizeof(*sdesc) + crypto_shash_descsize(alg);
  3747. sdesc = kmalloc(len, GFP_KERNEL);
  3748. if (!sdesc) {
  3749. rc = -ENOMEM;
  3750. goto free_shash;
  3751. }
  3752. sdesc->tfm = alg;
  3753. len = size - sizeof(fw_hdr->checksum);
  3754. rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
  3755. kfree(sdesc);
  3756. if (rc)
  3757. goto free_shash;
  3758. if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
  3759. dev_err(&tp->intf->dev, "checksum fail\n");
  3760. rc = -EFAULT;
  3761. }
  3762. free_shash:
  3763. crypto_free_shash(alg);
  3764. out:
  3765. return rc;
  3766. }
  3767. static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
  3768. {
  3769. const struct firmware *fw = rtl_fw->fw;
  3770. struct fw_header *fw_hdr = (struct fw_header *)fw->data;
  3771. unsigned long fw_flags = 0;
  3772. long ret = -EFAULT;
  3773. int i;
  3774. if (fw->size < sizeof(*fw_hdr)) {
  3775. dev_err(&tp->intf->dev, "file too small\n");
  3776. goto fail;
  3777. }
  3778. ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
  3779. if (ret)
  3780. goto fail;
  3781. ret = -EFAULT;
  3782. for (i = sizeof(*fw_hdr); i < fw->size;) {
  3783. struct fw_block *block = (struct fw_block *)&fw->data[i];
  3784. u32 type;
  3785. if ((i + sizeof(*block)) > fw->size)
  3786. goto fail;
  3787. type = __le32_to_cpu(block->type);
  3788. switch (type) {
  3789. case RTL_FW_END:
  3790. if (__le32_to_cpu(block->length) != sizeof(*block))
  3791. goto fail;
  3792. goto fw_end;
  3793. case RTL_FW_PLA:
  3794. if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
  3795. dev_err(&tp->intf->dev,
  3796. "multiple PLA firmware encountered");
  3797. goto fail;
  3798. }
  3799. if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
  3800. dev_err(&tp->intf->dev,
  3801. "check PLA firmware failed\n");
  3802. goto fail;
  3803. }
  3804. __set_bit(FW_FLAGS_PLA, &fw_flags);
  3805. break;
  3806. case RTL_FW_USB:
  3807. if (test_bit(FW_FLAGS_USB, &fw_flags)) {
  3808. dev_err(&tp->intf->dev,
  3809. "multiple USB firmware encountered");
  3810. goto fail;
  3811. }
  3812. if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
  3813. dev_err(&tp->intf->dev,
  3814. "check USB firmware failed\n");
  3815. goto fail;
  3816. }
  3817. __set_bit(FW_FLAGS_USB, &fw_flags);
  3818. break;
  3819. case RTL_FW_PHY_START:
  3820. if (test_bit(FW_FLAGS_START, &fw_flags) ||
  3821. test_bit(FW_FLAGS_NC, &fw_flags) ||
  3822. test_bit(FW_FLAGS_NC1, &fw_flags) ||
  3823. test_bit(FW_FLAGS_NC2, &fw_flags) ||
  3824. test_bit(FW_FLAGS_UC2, &fw_flags) ||
  3825. test_bit(FW_FLAGS_UC, &fw_flags) ||
  3826. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3827. dev_err(&tp->intf->dev,
  3828. "check PHY_START fail\n");
  3829. goto fail;
  3830. }
  3831. if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
  3832. dev_err(&tp->intf->dev,
  3833. "Invalid length for PHY_START\n");
  3834. goto fail;
  3835. }
  3836. __set_bit(FW_FLAGS_START, &fw_flags);
  3837. break;
  3838. case RTL_FW_PHY_STOP:
  3839. if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
  3840. !test_bit(FW_FLAGS_START, &fw_flags)) {
  3841. dev_err(&tp->intf->dev,
  3842. "Check PHY_STOP fail\n");
  3843. goto fail;
  3844. }
  3845. if (__le32_to_cpu(block->length) != sizeof(*block)) {
  3846. dev_err(&tp->intf->dev,
  3847. "Invalid length for PHY_STOP\n");
  3848. goto fail;
  3849. }
  3850. __set_bit(FW_FLAGS_STOP, &fw_flags);
  3851. break;
  3852. case RTL_FW_PHY_NC:
  3853. if (!test_bit(FW_FLAGS_START, &fw_flags) ||
  3854. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3855. dev_err(&tp->intf->dev,
  3856. "check PHY_NC fail\n");
  3857. goto fail;
  3858. }
  3859. if (test_bit(FW_FLAGS_NC, &fw_flags)) {
  3860. dev_err(&tp->intf->dev,
  3861. "multiple PHY NC encountered\n");
  3862. goto fail;
  3863. }
  3864. if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
  3865. dev_err(&tp->intf->dev,
  3866. "check PHY NC firmware failed\n");
  3867. goto fail;
  3868. }
  3869. __set_bit(FW_FLAGS_NC, &fw_flags);
  3870. break;
  3871. case RTL_FW_PHY_UNION_NC:
  3872. if (!test_bit(FW_FLAGS_START, &fw_flags) ||
  3873. test_bit(FW_FLAGS_NC1, &fw_flags) ||
  3874. test_bit(FW_FLAGS_NC2, &fw_flags) ||
  3875. test_bit(FW_FLAGS_UC2, &fw_flags) ||
  3876. test_bit(FW_FLAGS_UC, &fw_flags) ||
  3877. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3878. dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
  3879. goto fail;
  3880. }
  3881. if (test_bit(FW_FLAGS_NC, &fw_flags)) {
  3882. dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
  3883. goto fail;
  3884. }
  3885. if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
  3886. dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
  3887. goto fail;
  3888. }
  3889. __set_bit(FW_FLAGS_NC, &fw_flags);
  3890. break;
  3891. case RTL_FW_PHY_UNION_NC1:
  3892. if (!test_bit(FW_FLAGS_START, &fw_flags) ||
  3893. test_bit(FW_FLAGS_NC2, &fw_flags) ||
  3894. test_bit(FW_FLAGS_UC2, &fw_flags) ||
  3895. test_bit(FW_FLAGS_UC, &fw_flags) ||
  3896. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3897. dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
  3898. goto fail;
  3899. }
  3900. if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
  3901. dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
  3902. goto fail;
  3903. }
  3904. if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
  3905. dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
  3906. goto fail;
  3907. }
  3908. __set_bit(FW_FLAGS_NC1, &fw_flags);
  3909. break;
  3910. case RTL_FW_PHY_UNION_NC2:
  3911. if (!test_bit(FW_FLAGS_START, &fw_flags) ||
  3912. test_bit(FW_FLAGS_UC2, &fw_flags) ||
  3913. test_bit(FW_FLAGS_UC, &fw_flags) ||
  3914. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3915. dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
  3916. goto fail;
  3917. }
  3918. if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
  3919. dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
  3920. goto fail;
  3921. }
  3922. if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
  3923. dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
  3924. goto fail;
  3925. }
  3926. __set_bit(FW_FLAGS_NC2, &fw_flags);
  3927. break;
  3928. case RTL_FW_PHY_UNION_UC2:
  3929. if (!test_bit(FW_FLAGS_START, &fw_flags) ||
  3930. test_bit(FW_FLAGS_UC, &fw_flags) ||
  3931. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3932. dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
  3933. goto fail;
  3934. }
  3935. if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
  3936. dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
  3937. goto fail;
  3938. }
  3939. if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
  3940. dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
  3941. goto fail;
  3942. }
  3943. __set_bit(FW_FLAGS_UC2, &fw_flags);
  3944. break;
  3945. case RTL_FW_PHY_UNION_UC:
  3946. if (!test_bit(FW_FLAGS_START, &fw_flags) ||
  3947. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3948. dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
  3949. goto fail;
  3950. }
  3951. if (test_bit(FW_FLAGS_UC, &fw_flags)) {
  3952. dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
  3953. goto fail;
  3954. }
  3955. if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
  3956. dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
  3957. goto fail;
  3958. }
  3959. __set_bit(FW_FLAGS_UC, &fw_flags);
  3960. break;
  3961. case RTL_FW_PHY_UNION_MISC:
  3962. if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
  3963. dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
  3964. goto fail;
  3965. }
  3966. break;
  3967. case RTL_FW_PHY_FIXUP:
  3968. if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
  3969. dev_err(&tp->intf->dev, "check PHY fixup failed\n");
  3970. goto fail;
  3971. }
  3972. break;
  3973. case RTL_FW_PHY_SPEED_UP:
  3974. if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
  3975. dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
  3976. goto fail;
  3977. }
  3978. if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
  3979. dev_err(&tp->intf->dev, "check PHY speed up failed\n");
  3980. goto fail;
  3981. }
  3982. __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
  3983. break;
  3984. case RTL_FW_PHY_VER:
  3985. if (test_bit(FW_FLAGS_START, &fw_flags) ||
  3986. test_bit(FW_FLAGS_NC, &fw_flags) ||
  3987. test_bit(FW_FLAGS_NC1, &fw_flags) ||
  3988. test_bit(FW_FLAGS_NC2, &fw_flags) ||
  3989. test_bit(FW_FLAGS_UC2, &fw_flags) ||
  3990. test_bit(FW_FLAGS_UC, &fw_flags) ||
  3991. test_bit(FW_FLAGS_STOP, &fw_flags)) {
  3992. dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
  3993. goto fail;
  3994. }
  3995. if (test_bit(FW_FLAGS_VER, &fw_flags)) {
  3996. dev_err(&tp->intf->dev, "multiple PHY version encountered");
  3997. goto fail;
  3998. }
  3999. if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
  4000. dev_err(&tp->intf->dev, "check PHY version failed\n");
  4001. goto fail;
  4002. }
  4003. __set_bit(FW_FLAGS_VER, &fw_flags);
  4004. break;
  4005. default:
  4006. dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
  4007. type);
  4008. break;
  4009. }
  4010. /* next block */
  4011. i += ALIGN(__le32_to_cpu(block->length), 8);
  4012. }
  4013. fw_end:
  4014. if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
  4015. dev_err(&tp->intf->dev, "without PHY_STOP\n");
  4016. goto fail;
  4017. }
  4018. return 0;
  4019. fail:
  4020. return ret;
  4021. }
  4022. static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
  4023. {
  4024. u32 len;
  4025. u8 *data;
  4026. rtl_reset_ocp_base(tp);
  4027. if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
  4028. dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
  4029. return;
  4030. }
  4031. len = __le32_to_cpu(phy->blk_hdr.length);
  4032. len -= __le16_to_cpu(phy->fw_offset);
  4033. data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
  4034. if (rtl_phy_patch_request(tp, true, wait))
  4035. return;
  4036. while (len) {
  4037. u32 ocp_data, size;
  4038. int i;
  4039. if (len < 2048)
  4040. size = len;
  4041. else
  4042. size = 2048;
  4043. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
  4044. ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
  4045. ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
  4046. generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
  4047. data += size;
  4048. len -= size;
  4049. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
  4050. ocp_data |= POL_GPHY_PATCH;
  4051. ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
  4052. for (i = 0; i < 1000; i++) {
  4053. if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
  4054. break;
  4055. }
  4056. if (i == 1000) {
  4057. dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
  4058. break;
  4059. }
  4060. }
  4061. rtl_reset_ocp_base(tp);
  4062. rtl_phy_patch_request(tp, false, wait);
  4063. if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
  4064. dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
  4065. else
  4066. dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
  4067. }
  4068. static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
  4069. {
  4070. u16 ver_addr, ver;
  4071. ver_addr = __le16_to_cpu(phy_ver->ver.addr);
  4072. ver = __le16_to_cpu(phy_ver->ver.data);
  4073. rtl_reset_ocp_base(tp);
  4074. if (sram_read(tp, ver_addr) >= ver) {
  4075. dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
  4076. return 0;
  4077. }
  4078. sram_write(tp, ver_addr, ver);
  4079. dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
  4080. return ver;
  4081. }
  4082. static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
  4083. {
  4084. u16 addr, data;
  4085. rtl_reset_ocp_base(tp);
  4086. addr = __le16_to_cpu(fix->setting.addr);
  4087. data = ocp_reg_read(tp, addr);
  4088. switch (__le16_to_cpu(fix->bit_cmd)) {
  4089. case FW_FIXUP_AND:
  4090. data &= __le16_to_cpu(fix->setting.data);
  4091. break;
  4092. case FW_FIXUP_OR:
  4093. data |= __le16_to_cpu(fix->setting.data);
  4094. break;
  4095. case FW_FIXUP_NOT:
  4096. data &= ~__le16_to_cpu(fix->setting.data);
  4097. break;
  4098. case FW_FIXUP_XOR:
  4099. data ^= __le16_to_cpu(fix->setting.data);
  4100. break;
  4101. default:
  4102. return;
  4103. }
  4104. ocp_reg_write(tp, addr, data);
  4105. dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
  4106. }
  4107. static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
  4108. {
  4109. __le16 *data;
  4110. u32 length;
  4111. int i, num;
  4112. rtl_reset_ocp_base(tp);
  4113. num = phy->pre_num;
  4114. for (i = 0; i < num; i++)
  4115. sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
  4116. __le16_to_cpu(phy->pre_set[i].data));
  4117. length = __le32_to_cpu(phy->blk_hdr.length);
  4118. length -= __le16_to_cpu(phy->fw_offset);
  4119. num = length / 2;
  4120. data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
  4121. ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
  4122. for (i = 0; i < num; i++)
  4123. ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
  4124. num = phy->bp_num;
  4125. for (i = 0; i < num; i++)
  4126. sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
  4127. if (phy->bp_num && phy->bp_en.addr)
  4128. sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
  4129. dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
  4130. }
  4131. static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
  4132. {
  4133. u16 mode_reg, bp_index;
  4134. u32 length, i, num;
  4135. __le16 *data;
  4136. rtl_reset_ocp_base(tp);
  4137. mode_reg = __le16_to_cpu(phy->mode_reg);
  4138. sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
  4139. sram_write(tp, __le16_to_cpu(phy->ba_reg),
  4140. __le16_to_cpu(phy->ba_data));
  4141. length = __le32_to_cpu(phy->blk_hdr.length);
  4142. length -= __le16_to_cpu(phy->fw_offset);
  4143. num = length / 2;
  4144. data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
  4145. ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
  4146. for (i = 0; i < num; i++)
  4147. ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
  4148. sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
  4149. __le16_to_cpu(phy->patch_en_value));
  4150. bp_index = __le16_to_cpu(phy->bp_start);
  4151. num = __le16_to_cpu(phy->bp_num);
  4152. for (i = 0; i < num; i++) {
  4153. sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
  4154. bp_index += 2;
  4155. }
  4156. sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
  4157. dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
  4158. }
  4159. static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
  4160. {
  4161. u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
  4162. u32 length;
  4163. u8 *data;
  4164. int i;
  4165. switch (__le32_to_cpu(mac->blk_hdr.type)) {
  4166. case RTL_FW_PLA:
  4167. type = MCU_TYPE_PLA;
  4168. break;
  4169. case RTL_FW_USB:
  4170. type = MCU_TYPE_USB;
  4171. break;
  4172. default:
  4173. return;
  4174. }
  4175. fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
  4176. if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
  4177. dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
  4178. return;
  4179. }
  4180. rtl_clear_bp(tp, type);
  4181. /* Enable backup/restore of MACDBG. This is required after clearing PLA
  4182. * break points and before applying the PLA firmware.
  4183. */
  4184. if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
  4185. !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
  4186. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
  4187. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
  4188. }
  4189. length = __le32_to_cpu(mac->blk_hdr.length);
  4190. length -= __le16_to_cpu(mac->fw_offset);
  4191. data = (u8 *)mac;
  4192. data += __le16_to_cpu(mac->fw_offset);
  4193. generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
  4194. type);
  4195. ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
  4196. __le16_to_cpu(mac->bp_ba_value));
  4197. bp_index = __le16_to_cpu(mac->bp_start);
  4198. bp_num = __le16_to_cpu(mac->bp_num);
  4199. for (i = 0; i < bp_num; i++) {
  4200. ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
  4201. bp_index += 2;
  4202. }
  4203. bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
  4204. if (bp_en_addr)
  4205. ocp_write_word(tp, type, bp_en_addr,
  4206. __le16_to_cpu(mac->bp_en_value));
  4207. if (fw_ver_reg)
  4208. ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
  4209. mac->fw_ver_data);
  4210. dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
  4211. }
  4212. static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
  4213. {
  4214. struct rtl_fw *rtl_fw = &tp->rtl_fw;
  4215. const struct firmware *fw;
  4216. struct fw_header *fw_hdr;
  4217. struct fw_phy_patch_key *key;
  4218. u16 key_addr = 0;
  4219. int i, patch_phy = 1;
  4220. if (IS_ERR_OR_NULL(rtl_fw->fw))
  4221. return;
  4222. fw = rtl_fw->fw;
  4223. fw_hdr = (struct fw_header *)fw->data;
  4224. if (rtl_fw->pre_fw)
  4225. rtl_fw->pre_fw(tp);
  4226. for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
  4227. struct fw_block *block = (struct fw_block *)&fw->data[i];
  4228. switch (__le32_to_cpu(block->type)) {
  4229. case RTL_FW_END:
  4230. goto post_fw;
  4231. case RTL_FW_PLA:
  4232. case RTL_FW_USB:
  4233. rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
  4234. break;
  4235. case RTL_FW_PHY_START:
  4236. if (!patch_phy)
  4237. break;
  4238. key = (struct fw_phy_patch_key *)block;
  4239. key_addr = __le16_to_cpu(key->key_reg);
  4240. rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
  4241. break;
  4242. case RTL_FW_PHY_STOP:
  4243. if (!patch_phy)
  4244. break;
  4245. WARN_ON(!key_addr);
  4246. rtl_post_ram_code(tp, key_addr, !power_cut);
  4247. break;
  4248. case RTL_FW_PHY_NC:
  4249. rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
  4250. break;
  4251. case RTL_FW_PHY_VER:
  4252. patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
  4253. break;
  4254. case RTL_FW_PHY_UNION_NC:
  4255. case RTL_FW_PHY_UNION_NC1:
  4256. case RTL_FW_PHY_UNION_NC2:
  4257. case RTL_FW_PHY_UNION_UC2:
  4258. case RTL_FW_PHY_UNION_UC:
  4259. case RTL_FW_PHY_UNION_MISC:
  4260. if (patch_phy)
  4261. rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
  4262. break;
  4263. case RTL_FW_PHY_FIXUP:
  4264. if (patch_phy)
  4265. rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
  4266. break;
  4267. case RTL_FW_PHY_SPEED_UP:
  4268. rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
  4269. break;
  4270. default:
  4271. break;
  4272. }
  4273. i += ALIGN(__le32_to_cpu(block->length), 8);
  4274. }
  4275. post_fw:
  4276. if (rtl_fw->post_fw)
  4277. rtl_fw->post_fw(tp);
  4278. rtl_reset_ocp_base(tp);
  4279. strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
  4280. dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
  4281. }
  4282. static void rtl8152_release_firmware(struct r8152 *tp)
  4283. {
  4284. struct rtl_fw *rtl_fw = &tp->rtl_fw;
  4285. if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
  4286. release_firmware(rtl_fw->fw);
  4287. rtl_fw->fw = NULL;
  4288. }
  4289. }
  4290. static int rtl8152_request_firmware(struct r8152 *tp)
  4291. {
  4292. struct rtl_fw *rtl_fw = &tp->rtl_fw;
  4293. long rc;
  4294. if (rtl_fw->fw || !rtl_fw->fw_name) {
  4295. dev_info(&tp->intf->dev, "skip request firmware\n");
  4296. rc = 0;
  4297. goto result;
  4298. }
  4299. rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
  4300. if (rc < 0)
  4301. goto result;
  4302. rc = rtl8152_check_firmware(tp, rtl_fw);
  4303. if (rc < 0)
  4304. release_firmware(rtl_fw->fw);
  4305. result:
  4306. if (rc) {
  4307. rtl_fw->fw = ERR_PTR(rc);
  4308. dev_warn(&tp->intf->dev,
  4309. "unable to load firmware patch %s (%ld)\n",
  4310. rtl_fw->fw_name, rc);
  4311. }
  4312. return rc;
  4313. }
  4314. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  4315. {
  4316. if (enable) {
  4317. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  4318. LINKENA | DIS_SDSAVE);
  4319. } else {
  4320. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  4321. DIS_SDSAVE);
  4322. msleep(20);
  4323. }
  4324. }
  4325. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  4326. {
  4327. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  4328. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  4329. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  4330. }
  4331. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  4332. {
  4333. u16 data;
  4334. r8152_mmd_indirect(tp, dev, reg);
  4335. data = ocp_reg_read(tp, OCP_EEE_DATA);
  4336. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  4337. return data;
  4338. }
  4339. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  4340. {
  4341. r8152_mmd_indirect(tp, dev, reg);
  4342. ocp_reg_write(tp, OCP_EEE_DATA, data);
  4343. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  4344. }
  4345. static void r8152_eee_en(struct r8152 *tp, bool enable)
  4346. {
  4347. u16 config1, config2, config3;
  4348. u32 ocp_data;
  4349. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  4350. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  4351. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  4352. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  4353. if (enable) {
  4354. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  4355. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  4356. config1 |= sd_rise_time(1);
  4357. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  4358. config3 |= fast_snr(42);
  4359. } else {
  4360. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  4361. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  4362. RX_QUIET_EN);
  4363. config1 |= sd_rise_time(7);
  4364. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  4365. config3 |= fast_snr(511);
  4366. }
  4367. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  4368. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  4369. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  4370. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  4371. }
  4372. static void r8153_eee_en(struct r8152 *tp, bool enable)
  4373. {
  4374. u32 ocp_data;
  4375. u16 config;
  4376. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  4377. config = ocp_reg_read(tp, OCP_EEE_CFG);
  4378. if (enable) {
  4379. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  4380. config |= EEE10_EN;
  4381. } else {
  4382. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  4383. config &= ~EEE10_EN;
  4384. }
  4385. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  4386. ocp_reg_write(tp, OCP_EEE_CFG, config);
  4387. tp->ups_info.eee = enable;
  4388. }
  4389. static void r8156_eee_en(struct r8152 *tp, bool enable)
  4390. {
  4391. u16 config;
  4392. r8153_eee_en(tp, enable);
  4393. config = ocp_reg_read(tp, OCP_EEE_ADV2);
  4394. if (enable)
  4395. config |= MDIO_EEE_2_5GT;
  4396. else
  4397. config &= ~MDIO_EEE_2_5GT;
  4398. ocp_reg_write(tp, OCP_EEE_ADV2, config);
  4399. }
  4400. static void rtl_eee_enable(struct r8152 *tp, bool enable)
  4401. {
  4402. switch (tp->version) {
  4403. case RTL_VER_01:
  4404. case RTL_VER_02:
  4405. case RTL_VER_07:
  4406. if (enable) {
  4407. r8152_eee_en(tp, true);
  4408. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
  4409. tp->eee_adv);
  4410. } else {
  4411. r8152_eee_en(tp, false);
  4412. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
  4413. }
  4414. break;
  4415. case RTL_VER_03:
  4416. case RTL_VER_04:
  4417. case RTL_VER_05:
  4418. case RTL_VER_06:
  4419. case RTL_VER_08:
  4420. case RTL_VER_09:
  4421. case RTL_VER_14:
  4422. if (enable) {
  4423. r8153_eee_en(tp, true);
  4424. ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
  4425. } else {
  4426. r8153_eee_en(tp, false);
  4427. ocp_reg_write(tp, OCP_EEE_ADV, 0);
  4428. }
  4429. break;
  4430. case RTL_VER_10:
  4431. case RTL_VER_11:
  4432. case RTL_VER_12:
  4433. case RTL_VER_13:
  4434. case RTL_VER_15:
  4435. if (enable) {
  4436. r8156_eee_en(tp, true);
  4437. ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
  4438. } else {
  4439. r8156_eee_en(tp, false);
  4440. ocp_reg_write(tp, OCP_EEE_ADV, 0);
  4441. }
  4442. break;
  4443. default:
  4444. break;
  4445. }
  4446. }
  4447. static void r8152b_enable_fc(struct r8152 *tp)
  4448. {
  4449. u16 anar;
  4450. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  4451. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  4452. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  4453. tp->ups_info.flow_control = true;
  4454. }
  4455. static void rtl8152_disable(struct r8152 *tp)
  4456. {
  4457. r8152_aldps_en(tp, false);
  4458. rtl_disable(tp);
  4459. r8152_aldps_en(tp, true);
  4460. }
  4461. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  4462. {
  4463. rtl8152_apply_firmware(tp, false);
  4464. rtl_eee_enable(tp, tp->eee_en);
  4465. r8152_aldps_en(tp, true);
  4466. r8152b_enable_fc(tp);
  4467. set_bit(PHY_RESET, &tp->flags);
  4468. }
  4469. static void wait_oob_link_list_ready(struct r8152 *tp)
  4470. {
  4471. u32 ocp_data;
  4472. int i;
  4473. for (i = 0; i < 1000; i++) {
  4474. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  4475. break;
  4476. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4477. if (ocp_data & LINK_LIST_READY)
  4478. break;
  4479. usleep_range(1000, 2000);
  4480. }
  4481. }
  4482. static void r8156b_wait_loading_flash(struct r8152 *tp)
  4483. {
  4484. if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
  4485. !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
  4486. int i;
  4487. for (i = 0; i < 100; i++) {
  4488. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  4489. break;
  4490. if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
  4491. break;
  4492. usleep_range(1000, 2000);
  4493. }
  4494. }
  4495. }
  4496. static void r8152b_exit_oob(struct r8152 *tp)
  4497. {
  4498. u32 ocp_data;
  4499. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  4500. ocp_data &= ~RCR_ACPT_ALL;
  4501. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  4502. rxdy_gated_en(tp, true);
  4503. r8153_teredo_off(tp);
  4504. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  4505. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  4506. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4507. ocp_data &= ~NOW_IS_OOB;
  4508. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  4509. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4510. ocp_data &= ~MCU_BORW_EN;
  4511. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4512. wait_oob_link_list_ready(tp);
  4513. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4514. ocp_data |= RE_INIT_LL;
  4515. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4516. wait_oob_link_list_ready(tp);
  4517. rtl8152_nic_reset(tp);
  4518. /* rx share fifo credit full threshold */
  4519. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  4520. if (tp->udev->speed == USB_SPEED_FULL ||
  4521. tp->udev->speed == USB_SPEED_LOW) {
  4522. /* rx share fifo credit near full threshold */
  4523. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  4524. RXFIFO_THR2_FULL);
  4525. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  4526. RXFIFO_THR3_FULL);
  4527. } else {
  4528. /* rx share fifo credit near full threshold */
  4529. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  4530. RXFIFO_THR2_HIGH);
  4531. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  4532. RXFIFO_THR3_HIGH);
  4533. }
  4534. /* TX share fifo free credit full threshold */
  4535. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  4536. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  4537. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  4538. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  4539. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  4540. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  4541. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  4542. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  4543. ocp_data |= TCR0_AUTO_FIFO;
  4544. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  4545. }
  4546. static void r8152b_enter_oob(struct r8152 *tp)
  4547. {
  4548. u32 ocp_data;
  4549. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4550. ocp_data &= ~NOW_IS_OOB;
  4551. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  4552. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  4553. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  4554. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  4555. rtl_disable(tp);
  4556. wait_oob_link_list_ready(tp);
  4557. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4558. ocp_data |= RE_INIT_LL;
  4559. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4560. wait_oob_link_list_ready(tp);
  4561. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  4562. rtl_rx_vlan_en(tp, true);
  4563. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  4564. ocp_data |= ALDPS_PROXY_MODE;
  4565. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  4566. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4567. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  4568. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  4569. rxdy_gated_en(tp, false);
  4570. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  4571. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  4572. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  4573. }
  4574. static int r8153_pre_firmware_1(struct r8152 *tp)
  4575. {
  4576. int i;
  4577. /* Wait till the WTD timer is ready. It would take at most 104 ms. */
  4578. for (i = 0; i < 104; i++) {
  4579. u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
  4580. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  4581. return -ENODEV;
  4582. if (!(ocp_data & WTD1_EN))
  4583. break;
  4584. usleep_range(1000, 2000);
  4585. }
  4586. return 0;
  4587. }
  4588. static int r8153_post_firmware_1(struct r8152 *tp)
  4589. {
  4590. /* set USB_BP_4 to support USB_SPEED_SUPER only */
  4591. if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
  4592. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
  4593. /* reset UPHY timer to 36 ms */
  4594. ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
  4595. return 0;
  4596. }
  4597. static int r8153_pre_firmware_2(struct r8152 *tp)
  4598. {
  4599. u32 ocp_data;
  4600. r8153_pre_firmware_1(tp);
  4601. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
  4602. ocp_data &= ~FW_FIX_SUSPEND;
  4603. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
  4604. return 0;
  4605. }
  4606. static int r8153_post_firmware_2(struct r8152 *tp)
  4607. {
  4608. u32 ocp_data;
  4609. /* enable bp0 if support USB_SPEED_SUPER only */
  4610. if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
  4611. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
  4612. ocp_data |= BIT(0);
  4613. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
  4614. }
  4615. /* reset UPHY timer to 36 ms */
  4616. ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
  4617. /* enable U3P3 check, set the counter to 4 */
  4618. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
  4619. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
  4620. ocp_data |= FW_FIX_SUSPEND;
  4621. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
  4622. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  4623. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  4624. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  4625. return 0;
  4626. }
  4627. static int r8153_post_firmware_3(struct r8152 *tp)
  4628. {
  4629. u32 ocp_data;
  4630. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  4631. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  4632. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  4633. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
  4634. ocp_data |= FW_IP_RESET_EN;
  4635. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
  4636. return 0;
  4637. }
  4638. static int r8153b_pre_firmware_1(struct r8152 *tp)
  4639. {
  4640. /* enable fc timer and set timer to 1 second. */
  4641. ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
  4642. CTRL_TIMER_EN | (1000 / 8));
  4643. return 0;
  4644. }
  4645. static int r8153b_post_firmware_1(struct r8152 *tp)
  4646. {
  4647. u32 ocp_data;
  4648. /* enable bp0 for RTL8153-BND */
  4649. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
  4650. if (ocp_data & BND_MASK) {
  4651. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
  4652. ocp_data |= BIT(0);
  4653. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
  4654. }
  4655. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
  4656. ocp_data |= FLOW_CTRL_PATCH_OPT;
  4657. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
  4658. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
  4659. ocp_data |= FC_PATCH_TASK;
  4660. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  4661. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
  4662. ocp_data |= FW_IP_RESET_EN;
  4663. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
  4664. return 0;
  4665. }
  4666. static int r8153c_post_firmware_1(struct r8152 *tp)
  4667. {
  4668. u32 ocp_data;
  4669. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
  4670. ocp_data |= FLOW_CTRL_PATCH_2;
  4671. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
  4672. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
  4673. ocp_data |= FC_PATCH_TASK;
  4674. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  4675. return 0;
  4676. }
  4677. static int r8156a_post_firmware_1(struct r8152 *tp)
  4678. {
  4679. u32 ocp_data;
  4680. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
  4681. ocp_data |= FW_IP_RESET_EN;
  4682. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
  4683. /* Modify U3PHY parameter for compatibility issue */
  4684. ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
  4685. ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
  4686. return 0;
  4687. }
  4688. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  4689. {
  4690. u16 data;
  4691. data = ocp_reg_read(tp, OCP_POWER_CFG);
  4692. if (enable) {
  4693. data |= EN_ALDPS;
  4694. ocp_reg_write(tp, OCP_POWER_CFG, data);
  4695. } else {
  4696. int i;
  4697. data &= ~EN_ALDPS;
  4698. ocp_reg_write(tp, OCP_POWER_CFG, data);
  4699. for (i = 0; i < 20; i++) {
  4700. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  4701. return;
  4702. usleep_range(1000, 2000);
  4703. if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
  4704. break;
  4705. }
  4706. }
  4707. tp->ups_info.aldps = enable;
  4708. }
  4709. static void r8153_hw_phy_cfg(struct r8152 *tp)
  4710. {
  4711. u32 ocp_data;
  4712. u16 data;
  4713. /* disable ALDPS before updating the PHY parameters */
  4714. r8153_aldps_en(tp, false);
  4715. /* disable EEE before updating the PHY parameters */
  4716. rtl_eee_enable(tp, false);
  4717. rtl8152_apply_firmware(tp, false);
  4718. if (tp->version == RTL_VER_03) {
  4719. data = ocp_reg_read(tp, OCP_EEE_CFG);
  4720. data &= ~CTAP_SHORT_EN;
  4721. ocp_reg_write(tp, OCP_EEE_CFG, data);
  4722. }
  4723. data = ocp_reg_read(tp, OCP_POWER_CFG);
  4724. data |= EEE_CLKDIV_EN;
  4725. ocp_reg_write(tp, OCP_POWER_CFG, data);
  4726. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  4727. data |= EN_10M_BGOFF;
  4728. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  4729. data = ocp_reg_read(tp, OCP_POWER_CFG);
  4730. data |= EN_10M_PLLOFF;
  4731. ocp_reg_write(tp, OCP_POWER_CFG, data);
  4732. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  4733. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  4734. ocp_data |= PFM_PWM_SWITCH;
  4735. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  4736. /* Enable LPF corner auto tune */
  4737. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  4738. /* Adjust 10M Amplitude */
  4739. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  4740. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  4741. if (tp->eee_en)
  4742. rtl_eee_enable(tp, true);
  4743. r8153_aldps_en(tp, true);
  4744. r8152b_enable_fc(tp);
  4745. switch (tp->version) {
  4746. case RTL_VER_03:
  4747. case RTL_VER_04:
  4748. break;
  4749. case RTL_VER_05:
  4750. case RTL_VER_06:
  4751. default:
  4752. r8153_u2p3en(tp, true);
  4753. break;
  4754. }
  4755. set_bit(PHY_RESET, &tp->flags);
  4756. }
  4757. static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
  4758. {
  4759. u32 ocp_data;
  4760. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
  4761. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
  4762. ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
  4763. ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
  4764. return ocp_data;
  4765. }
  4766. static void r8153b_hw_phy_cfg(struct r8152 *tp)
  4767. {
  4768. u32 ocp_data;
  4769. u16 data;
  4770. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  4771. if (ocp_data & PCUT_STATUS) {
  4772. ocp_data &= ~PCUT_STATUS;
  4773. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  4774. }
  4775. /* disable ALDPS before updating the PHY parameters */
  4776. r8153_aldps_en(tp, false);
  4777. /* disable EEE before updating the PHY parameters */
  4778. rtl_eee_enable(tp, false);
  4779. /* U1/U2/L1 idle timer. 500 us */
  4780. ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
  4781. data = r8153_phy_status(tp, 0);
  4782. switch (data) {
  4783. case PHY_STAT_PWRDN:
  4784. case PHY_STAT_EXT_INIT:
  4785. rtl8152_apply_firmware(tp, true);
  4786. data = r8152_mdio_read(tp, MII_BMCR);
  4787. data &= ~BMCR_PDOWN;
  4788. r8152_mdio_write(tp, MII_BMCR, data);
  4789. break;
  4790. case PHY_STAT_LAN_ON:
  4791. default:
  4792. rtl8152_apply_firmware(tp, false);
  4793. break;
  4794. }
  4795. r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
  4796. data = sram_read(tp, SRAM_GREEN_CFG);
  4797. data |= R_TUNE_EN;
  4798. sram_write(tp, SRAM_GREEN_CFG, data);
  4799. data = ocp_reg_read(tp, OCP_NCTL_CFG);
  4800. data |= PGA_RETURN_EN;
  4801. ocp_reg_write(tp, OCP_NCTL_CFG, data);
  4802. /* ADC Bias Calibration:
  4803. * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
  4804. * bit (bit3) to rebuild the real 16-bit data. Write the data to the
  4805. * ADC ioffset.
  4806. */
  4807. ocp_data = r8152_efuse_read(tp, 0x7d);
  4808. data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
  4809. if (data != 0xffff)
  4810. ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
  4811. /* ups mode tx-link-pulse timing adjustment:
  4812. * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
  4813. * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
  4814. */
  4815. ocp_data = ocp_reg_read(tp, 0xc426);
  4816. ocp_data &= 0x3fff;
  4817. if (ocp_data) {
  4818. u32 swr_cnt_1ms_ini;
  4819. swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
  4820. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
  4821. ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
  4822. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
  4823. }
  4824. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  4825. ocp_data |= PFM_PWM_SWITCH;
  4826. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  4827. /* Advnace EEE */
  4828. if (!rtl_phy_patch_request(tp, true, true)) {
  4829. data = ocp_reg_read(tp, OCP_POWER_CFG);
  4830. data |= EEE_CLKDIV_EN;
  4831. ocp_reg_write(tp, OCP_POWER_CFG, data);
  4832. tp->ups_info.eee_ckdiv = true;
  4833. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  4834. data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
  4835. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  4836. tp->ups_info.eee_cmod_lv = true;
  4837. tp->ups_info._10m_ckdiv = true;
  4838. tp->ups_info.eee_plloff_giga = true;
  4839. ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
  4840. ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
  4841. tp->ups_info._250m_ckdiv = true;
  4842. rtl_phy_patch_request(tp, false, true);
  4843. }
  4844. if (tp->eee_en)
  4845. rtl_eee_enable(tp, true);
  4846. r8153_aldps_en(tp, true);
  4847. r8152b_enable_fc(tp);
  4848. set_bit(PHY_RESET, &tp->flags);
  4849. }
  4850. static void r8153c_hw_phy_cfg(struct r8152 *tp)
  4851. {
  4852. r8153b_hw_phy_cfg(tp);
  4853. tp->ups_info.r_tune = true;
  4854. }
  4855. static void rtl8153_change_mtu(struct r8152 *tp)
  4856. {
  4857. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
  4858. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  4859. }
  4860. static void r8153_first_init(struct r8152 *tp)
  4861. {
  4862. u32 ocp_data;
  4863. rxdy_gated_en(tp, true);
  4864. r8153_teredo_off(tp);
  4865. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  4866. ocp_data &= ~RCR_ACPT_ALL;
  4867. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  4868. rtl8152_nic_reset(tp);
  4869. rtl_reset_bmu(tp);
  4870. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4871. ocp_data &= ~NOW_IS_OOB;
  4872. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  4873. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4874. ocp_data &= ~MCU_BORW_EN;
  4875. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4876. wait_oob_link_list_ready(tp);
  4877. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4878. ocp_data |= RE_INIT_LL;
  4879. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4880. wait_oob_link_list_ready(tp);
  4881. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  4882. rtl8153_change_mtu(tp);
  4883. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  4884. ocp_data |= TCR0_AUTO_FIFO;
  4885. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  4886. rtl8152_nic_reset(tp);
  4887. /* rx share fifo credit full threshold */
  4888. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  4889. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  4890. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  4891. /* TX share fifo free credit full threshold */
  4892. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  4893. }
  4894. static void r8153_enter_oob(struct r8152 *tp)
  4895. {
  4896. u32 ocp_data;
  4897. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4898. ocp_data &= ~NOW_IS_OOB;
  4899. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  4900. /* RX FIFO settings for OOB */
  4901. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  4902. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  4903. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  4904. rtl_disable(tp);
  4905. rtl_reset_bmu(tp);
  4906. wait_oob_link_list_ready(tp);
  4907. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4908. ocp_data |= RE_INIT_LL;
  4909. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4910. wait_oob_link_list_ready(tp);
  4911. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
  4912. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
  4913. switch (tp->version) {
  4914. case RTL_VER_03:
  4915. case RTL_VER_04:
  4916. case RTL_VER_05:
  4917. case RTL_VER_06:
  4918. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  4919. ocp_data &= ~TEREDO_WAKE_MASK;
  4920. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  4921. break;
  4922. case RTL_VER_08:
  4923. case RTL_VER_09:
  4924. case RTL_VER_14:
  4925. /* Clear teredo wake event. bit[15:8] is the teredo wakeup
  4926. * type. Set it to zero. bits[7:0] are the W1C bits about
  4927. * the events. Set them to all 1 to clear them.
  4928. */
  4929. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
  4930. break;
  4931. default:
  4932. break;
  4933. }
  4934. rtl_rx_vlan_en(tp, true);
  4935. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  4936. ocp_data |= ALDPS_PROXY_MODE;
  4937. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  4938. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  4939. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  4940. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  4941. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  4942. ocp_data |= MCU_BORW_EN;
  4943. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  4944. rxdy_gated_en(tp, false);
  4945. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  4946. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  4947. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  4948. }
  4949. static void rtl8153_disable(struct r8152 *tp)
  4950. {
  4951. r8153_aldps_en(tp, false);
  4952. rtl_disable(tp);
  4953. rtl_reset_bmu(tp);
  4954. r8153_aldps_en(tp, true);
  4955. }
  4956. static u32 fc_pause_on_auto(struct r8152 *tp)
  4957. {
  4958. return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
  4959. }
  4960. static u32 fc_pause_off_auto(struct r8152 *tp)
  4961. {
  4962. return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
  4963. }
  4964. static void r8156_fc_parameter(struct r8152 *tp)
  4965. {
  4966. u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
  4967. u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
  4968. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
  4969. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
  4970. }
  4971. static int rtl8156_enable(struct r8152 *tp)
  4972. {
  4973. u32 ocp_data;
  4974. u16 speed;
  4975. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  4976. return -ENODEV;
  4977. r8156_fc_parameter(tp);
  4978. set_tx_qlen(tp);
  4979. rtl_set_eee_plus(tp);
  4980. r8153_set_rx_early_timeout(tp);
  4981. r8153_set_rx_early_size(tp);
  4982. speed = rtl8152_get_speed(tp);
  4983. rtl_set_ifg(tp, speed);
  4984. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
  4985. if (speed & _2500bps)
  4986. ocp_data &= ~IDLE_SPDWN_EN;
  4987. else
  4988. ocp_data |= IDLE_SPDWN_EN;
  4989. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
  4990. if (speed & _1000bps)
  4991. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
  4992. else if (speed & _500bps)
  4993. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
  4994. if (tp->udev->speed == USB_SPEED_HIGH) {
  4995. /* USB 0xb45e[3:0] l1_nyet_hird */
  4996. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
  4997. ocp_data &= ~0xf;
  4998. if (is_flow_control(speed))
  4999. ocp_data |= 0xf;
  5000. else
  5001. ocp_data |= 0x1;
  5002. ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
  5003. }
  5004. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
  5005. ocp_data &= ~FC_PATCH_TASK;
  5006. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  5007. usleep_range(1000, 2000);
  5008. ocp_data |= FC_PATCH_TASK;
  5009. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  5010. return rtl_enable(tp);
  5011. }
  5012. static void rtl8156_disable(struct r8152 *tp)
  5013. {
  5014. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0);
  5015. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0);
  5016. rtl8153_disable(tp);
  5017. }
  5018. static int rtl8156b_enable(struct r8152 *tp)
  5019. {
  5020. u32 ocp_data;
  5021. u16 speed;
  5022. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5023. return -ENODEV;
  5024. set_tx_qlen(tp);
  5025. rtl_set_eee_plus(tp);
  5026. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
  5027. ocp_data &= ~RX_AGGR_NUM_MASK;
  5028. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
  5029. r8153_set_rx_early_timeout(tp);
  5030. r8153_set_rx_early_size(tp);
  5031. speed = rtl8152_get_speed(tp);
  5032. rtl_set_ifg(tp, speed);
  5033. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
  5034. if (speed & _2500bps)
  5035. ocp_data &= ~IDLE_SPDWN_EN;
  5036. else
  5037. ocp_data |= IDLE_SPDWN_EN;
  5038. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
  5039. if (tp->udev->speed == USB_SPEED_HIGH) {
  5040. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
  5041. ocp_data &= ~0xf;
  5042. if (is_flow_control(speed))
  5043. ocp_data |= 0xf;
  5044. else
  5045. ocp_data |= 0x1;
  5046. ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
  5047. }
  5048. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
  5049. ocp_data &= ~FC_PATCH_TASK;
  5050. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  5051. usleep_range(1000, 2000);
  5052. ocp_data |= FC_PATCH_TASK;
  5053. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  5054. return rtl_enable(tp);
  5055. }
  5056. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
  5057. u32 advertising)
  5058. {
  5059. u16 bmcr;
  5060. int ret = 0;
  5061. if (autoneg == AUTONEG_DISABLE) {
  5062. if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
  5063. return -EINVAL;
  5064. switch (speed) {
  5065. case SPEED_10:
  5066. bmcr = BMCR_SPEED10;
  5067. if (duplex == DUPLEX_FULL) {
  5068. bmcr |= BMCR_FULLDPLX;
  5069. tp->ups_info.speed_duplex = FORCE_10M_FULL;
  5070. } else {
  5071. tp->ups_info.speed_duplex = FORCE_10M_HALF;
  5072. }
  5073. break;
  5074. case SPEED_100:
  5075. bmcr = BMCR_SPEED100;
  5076. if (duplex == DUPLEX_FULL) {
  5077. bmcr |= BMCR_FULLDPLX;
  5078. tp->ups_info.speed_duplex = FORCE_100M_FULL;
  5079. } else {
  5080. tp->ups_info.speed_duplex = FORCE_100M_HALF;
  5081. }
  5082. break;
  5083. case SPEED_1000:
  5084. if (tp->mii.supports_gmii) {
  5085. bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
  5086. tp->ups_info.speed_duplex = NWAY_1000M_FULL;
  5087. break;
  5088. }
  5089. fallthrough;
  5090. default:
  5091. ret = -EINVAL;
  5092. goto out;
  5093. }
  5094. if (duplex == DUPLEX_FULL)
  5095. tp->mii.full_duplex = 1;
  5096. else
  5097. tp->mii.full_duplex = 0;
  5098. tp->mii.force_media = 1;
  5099. } else {
  5100. u16 orig, new1;
  5101. u32 support;
  5102. support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
  5103. RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
  5104. if (tp->mii.supports_gmii) {
  5105. support |= RTL_ADVERTISED_1000_FULL;
  5106. if (tp->support_2500full)
  5107. support |= RTL_ADVERTISED_2500_FULL;
  5108. }
  5109. if (!(advertising & support))
  5110. return -EINVAL;
  5111. orig = r8152_mdio_read(tp, MII_ADVERTISE);
  5112. new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  5113. ADVERTISE_100HALF | ADVERTISE_100FULL);
  5114. if (advertising & RTL_ADVERTISED_10_HALF) {
  5115. new1 |= ADVERTISE_10HALF;
  5116. tp->ups_info.speed_duplex = NWAY_10M_HALF;
  5117. }
  5118. if (advertising & RTL_ADVERTISED_10_FULL) {
  5119. new1 |= ADVERTISE_10FULL;
  5120. tp->ups_info.speed_duplex = NWAY_10M_FULL;
  5121. }
  5122. if (advertising & RTL_ADVERTISED_100_HALF) {
  5123. new1 |= ADVERTISE_100HALF;
  5124. tp->ups_info.speed_duplex = NWAY_100M_HALF;
  5125. }
  5126. if (advertising & RTL_ADVERTISED_100_FULL) {
  5127. new1 |= ADVERTISE_100FULL;
  5128. tp->ups_info.speed_duplex = NWAY_100M_FULL;
  5129. }
  5130. if (orig != new1) {
  5131. r8152_mdio_write(tp, MII_ADVERTISE, new1);
  5132. tp->mii.advertising = new1;
  5133. }
  5134. if (tp->mii.supports_gmii) {
  5135. orig = r8152_mdio_read(tp, MII_CTRL1000);
  5136. new1 = orig & ~(ADVERTISE_1000FULL |
  5137. ADVERTISE_1000HALF);
  5138. if (advertising & RTL_ADVERTISED_1000_FULL) {
  5139. new1 |= ADVERTISE_1000FULL;
  5140. tp->ups_info.speed_duplex = NWAY_1000M_FULL;
  5141. }
  5142. if (orig != new1)
  5143. r8152_mdio_write(tp, MII_CTRL1000, new1);
  5144. }
  5145. if (tp->support_2500full) {
  5146. orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
  5147. new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
  5148. if (advertising & RTL_ADVERTISED_2500_FULL) {
  5149. new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
  5150. tp->ups_info.speed_duplex = NWAY_2500M_FULL;
  5151. }
  5152. if (orig != new1)
  5153. ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
  5154. }
  5155. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  5156. tp->mii.force_media = 0;
  5157. }
  5158. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  5159. bmcr |= BMCR_RESET;
  5160. r8152_mdio_write(tp, MII_BMCR, bmcr);
  5161. if (bmcr & BMCR_RESET) {
  5162. int i;
  5163. for (i = 0; i < 50; i++) {
  5164. msleep(20);
  5165. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  5166. break;
  5167. }
  5168. }
  5169. out:
  5170. return ret;
  5171. }
  5172. static void rtl8152_up(struct r8152 *tp)
  5173. {
  5174. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5175. return;
  5176. r8152_aldps_en(tp, false);
  5177. r8152b_exit_oob(tp);
  5178. r8152_aldps_en(tp, true);
  5179. }
  5180. static void rtl8152_down(struct r8152 *tp)
  5181. {
  5182. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
  5183. rtl_drop_queued_tx(tp);
  5184. return;
  5185. }
  5186. r8152_power_cut_en(tp, false);
  5187. r8152_aldps_en(tp, false);
  5188. r8152b_enter_oob(tp);
  5189. r8152_aldps_en(tp, true);
  5190. }
  5191. static void rtl8153_up(struct r8152 *tp)
  5192. {
  5193. u32 ocp_data;
  5194. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5195. return;
  5196. r8153_u1u2en(tp, false);
  5197. r8153_u2p3en(tp, false);
  5198. r8153_aldps_en(tp, false);
  5199. r8153_first_init(tp);
  5200. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
  5201. ocp_data |= LANWAKE_CLR_EN;
  5202. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
  5203. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
  5204. ocp_data &= ~LANWAKE_PIN;
  5205. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
  5206. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
  5207. ocp_data &= ~DELAY_PHY_PWR_CHG;
  5208. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
  5209. r8153_aldps_en(tp, true);
  5210. switch (tp->version) {
  5211. case RTL_VER_03:
  5212. case RTL_VER_04:
  5213. break;
  5214. case RTL_VER_05:
  5215. case RTL_VER_06:
  5216. default:
  5217. r8153_u2p3en(tp, true);
  5218. break;
  5219. }
  5220. r8153_u1u2en(tp, true);
  5221. }
  5222. static void rtl8153_down(struct r8152 *tp)
  5223. {
  5224. u32 ocp_data;
  5225. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
  5226. rtl_drop_queued_tx(tp);
  5227. return;
  5228. }
  5229. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
  5230. ocp_data &= ~LANWAKE_CLR_EN;
  5231. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
  5232. r8153_u1u2en(tp, false);
  5233. r8153_u2p3en(tp, false);
  5234. r8153_power_cut_en(tp, false);
  5235. r8153_aldps_en(tp, false);
  5236. r8153_enter_oob(tp);
  5237. r8153_aldps_en(tp, true);
  5238. }
  5239. static void rtl8153b_up(struct r8152 *tp)
  5240. {
  5241. u32 ocp_data;
  5242. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5243. return;
  5244. r8153b_u1u2en(tp, false);
  5245. r8153_u2p3en(tp, false);
  5246. r8153_aldps_en(tp, false);
  5247. r8153_first_init(tp);
  5248. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
  5249. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  5250. ocp_data &= ~PLA_MCU_SPDWN_EN;
  5251. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  5252. r8153_aldps_en(tp, true);
  5253. if (tp->udev->speed >= USB_SPEED_SUPER)
  5254. r8153b_u1u2en(tp, true);
  5255. }
  5256. static void rtl8153b_down(struct r8152 *tp)
  5257. {
  5258. u32 ocp_data;
  5259. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
  5260. rtl_drop_queued_tx(tp);
  5261. return;
  5262. }
  5263. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  5264. ocp_data |= PLA_MCU_SPDWN_EN;
  5265. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  5266. r8153b_u1u2en(tp, false);
  5267. r8153_u2p3en(tp, false);
  5268. r8153b_power_cut_en(tp, false);
  5269. r8153_aldps_en(tp, false);
  5270. r8153_enter_oob(tp);
  5271. r8153_aldps_en(tp, true);
  5272. }
  5273. static void rtl8153c_change_mtu(struct r8152 *tp)
  5274. {
  5275. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
  5276. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
  5277. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
  5278. /* Adjust the tx fifo free credit full threshold, otherwise
  5279. * the fifo would be too small to send a jumbo frame packet.
  5280. */
  5281. if (tp->netdev->mtu < 8000)
  5282. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
  5283. else
  5284. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
  5285. }
  5286. static void rtl8153c_up(struct r8152 *tp)
  5287. {
  5288. u32 ocp_data;
  5289. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5290. return;
  5291. r8153b_u1u2en(tp, false);
  5292. r8153_u2p3en(tp, false);
  5293. r8153_aldps_en(tp, false);
  5294. rxdy_gated_en(tp, true);
  5295. r8153_teredo_off(tp);
  5296. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  5297. ocp_data &= ~RCR_ACPT_ALL;
  5298. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  5299. rtl8152_nic_reset(tp);
  5300. rtl_reset_bmu(tp);
  5301. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  5302. ocp_data &= ~NOW_IS_OOB;
  5303. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  5304. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  5305. ocp_data &= ~MCU_BORW_EN;
  5306. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  5307. wait_oob_link_list_ready(tp);
  5308. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  5309. ocp_data |= RE_INIT_LL;
  5310. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  5311. wait_oob_link_list_ready(tp);
  5312. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  5313. rtl8153c_change_mtu(tp);
  5314. rtl8152_nic_reset(tp);
  5315. /* rx share fifo credit full threshold */
  5316. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
  5317. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
  5318. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  5319. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  5320. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
  5321. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  5322. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  5323. ocp_data |= BIT(8);
  5324. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  5325. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  5326. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  5327. ocp_data &= ~PLA_MCU_SPDWN_EN;
  5328. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  5329. r8153_aldps_en(tp, true);
  5330. r8153b_u1u2en(tp, true);
  5331. }
  5332. static void rtl8156_change_mtu(struct r8152 *tp)
  5333. {
  5334. u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
  5335. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
  5336. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  5337. r8156_fc_parameter(tp);
  5338. /* TX share fifo free credit full threshold */
  5339. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
  5340. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
  5341. ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
  5342. }
  5343. static void rtl8156_up(struct r8152 *tp)
  5344. {
  5345. u32 ocp_data;
  5346. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5347. return;
  5348. r8153b_u1u2en(tp, false);
  5349. r8153_u2p3en(tp, false);
  5350. r8153_aldps_en(tp, false);
  5351. rxdy_gated_en(tp, true);
  5352. r8153_teredo_off(tp);
  5353. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  5354. ocp_data &= ~RCR_ACPT_ALL;
  5355. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  5356. rtl8152_nic_reset(tp);
  5357. rtl_reset_bmu(tp);
  5358. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  5359. ocp_data &= ~NOW_IS_OOB;
  5360. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  5361. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  5362. ocp_data &= ~MCU_BORW_EN;
  5363. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  5364. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  5365. rtl8156_change_mtu(tp);
  5366. switch (tp->version) {
  5367. case RTL_TEST_01:
  5368. case RTL_VER_10:
  5369. case RTL_VER_11:
  5370. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
  5371. ocp_data |= ACT_ODMA;
  5372. ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
  5373. break;
  5374. default:
  5375. break;
  5376. }
  5377. /* share FIFO settings */
  5378. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
  5379. ocp_data &= ~RXFIFO_FULL_MASK;
  5380. ocp_data |= 0x08;
  5381. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
  5382. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  5383. ocp_data &= ~PLA_MCU_SPDWN_EN;
  5384. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  5385. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
  5386. ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
  5387. ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
  5388. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
  5389. if (tp->saved_wolopts != __rtl_get_wol(tp)) {
  5390. netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
  5391. __rtl_set_wol(tp, tp->saved_wolopts);
  5392. }
  5393. r8153_aldps_en(tp, true);
  5394. r8153_u2p3en(tp, true);
  5395. if (tp->udev->speed >= USB_SPEED_SUPER)
  5396. r8153b_u1u2en(tp, true);
  5397. }
  5398. static void rtl8156_down(struct r8152 *tp)
  5399. {
  5400. u32 ocp_data;
  5401. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
  5402. rtl_drop_queued_tx(tp);
  5403. return;
  5404. }
  5405. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  5406. ocp_data |= PLA_MCU_SPDWN_EN;
  5407. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  5408. r8153b_u1u2en(tp, false);
  5409. r8153_u2p3en(tp, false);
  5410. r8153b_power_cut_en(tp, false);
  5411. r8153_aldps_en(tp, false);
  5412. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  5413. ocp_data &= ~NOW_IS_OOB;
  5414. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  5415. /* RX FIFO settings for OOB */
  5416. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
  5417. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
  5418. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
  5419. rtl_disable(tp);
  5420. rtl_reset_bmu(tp);
  5421. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
  5422. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
  5423. /* Clear teredo wake event. bit[15:8] is the teredo wakeup
  5424. * type. Set it to zero. bits[7:0] are the W1C bits about
  5425. * the events. Set them to all 1 to clear them.
  5426. */
  5427. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
  5428. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  5429. ocp_data |= NOW_IS_OOB;
  5430. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  5431. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  5432. ocp_data |= MCU_BORW_EN;
  5433. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  5434. rtl_rx_vlan_en(tp, true);
  5435. rxdy_gated_en(tp, false);
  5436. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  5437. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  5438. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  5439. r8153_aldps_en(tp, true);
  5440. }
  5441. static bool rtl8152_in_nway(struct r8152 *tp)
  5442. {
  5443. u16 nway_state;
  5444. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  5445. tp->ocp_base = 0x2000;
  5446. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  5447. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  5448. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  5449. if (nway_state & 0xc000)
  5450. return false;
  5451. else
  5452. return true;
  5453. }
  5454. static bool rtl8153_in_nway(struct r8152 *tp)
  5455. {
  5456. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  5457. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  5458. return false;
  5459. else
  5460. return true;
  5461. }
  5462. static void r8156_mdio_force_mode(struct r8152 *tp)
  5463. {
  5464. u16 data;
  5465. /* Select force mode through 0xa5b4 bit 15
  5466. * 0: MDIO force mode
  5467. * 1: MMD force mode
  5468. */
  5469. data = ocp_reg_read(tp, 0xa5b4);
  5470. if (data & BIT(15)) {
  5471. data &= ~BIT(15);
  5472. ocp_reg_write(tp, 0xa5b4, data);
  5473. }
  5474. }
  5475. static void set_carrier(struct r8152 *tp)
  5476. {
  5477. struct net_device *netdev = tp->netdev;
  5478. struct napi_struct *napi = &tp->napi;
  5479. u16 speed;
  5480. speed = rtl8152_get_speed(tp);
  5481. if (speed & LINK_STATUS) {
  5482. if (!netif_carrier_ok(netdev)) {
  5483. tp->rtl_ops.enable(tp);
  5484. netif_stop_queue(netdev);
  5485. napi_disable(napi);
  5486. netif_carrier_on(netdev);
  5487. rtl_start_rx(tp);
  5488. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  5489. _rtl8152_set_rx_mode(netdev);
  5490. napi_enable(napi);
  5491. netif_wake_queue(netdev);
  5492. netif_info(tp, link, netdev, "carrier on\n");
  5493. } else if (netif_queue_stopped(netdev) &&
  5494. skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
  5495. netif_wake_queue(netdev);
  5496. }
  5497. } else {
  5498. if (netif_carrier_ok(netdev)) {
  5499. netif_carrier_off(netdev);
  5500. tasklet_disable(&tp->tx_tl);
  5501. napi_disable(napi);
  5502. tp->rtl_ops.disable(tp);
  5503. napi_enable(napi);
  5504. tasklet_enable(&tp->tx_tl);
  5505. netif_info(tp, link, netdev, "carrier off\n");
  5506. }
  5507. }
  5508. }
  5509. static void rtl_work_func_t(struct work_struct *work)
  5510. {
  5511. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  5512. /* If the device is unplugged or !netif_running(), the workqueue
  5513. * doesn't need to wake the device, and could return directly.
  5514. */
  5515. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))
  5516. return;
  5517. if (usb_autopm_get_interface(tp->intf) < 0)
  5518. return;
  5519. if (!test_bit(WORK_ENABLE, &tp->flags))
  5520. goto out1;
  5521. if (!mutex_trylock(&tp->control)) {
  5522. schedule_delayed_work(&tp->schedule, 0);
  5523. goto out1;
  5524. }
  5525. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  5526. set_carrier(tp);
  5527. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  5528. _rtl8152_set_rx_mode(tp->netdev);
  5529. /* don't schedule tasket before linking */
  5530. if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
  5531. netif_carrier_ok(tp->netdev))
  5532. tasklet_schedule(&tp->tx_tl);
  5533. if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
  5534. !list_empty(&tp->rx_done))
  5535. napi_schedule(&tp->napi);
  5536. mutex_unlock(&tp->control);
  5537. out1:
  5538. usb_autopm_put_interface(tp->intf);
  5539. }
  5540. static void rtl_hw_phy_work_func_t(struct work_struct *work)
  5541. {
  5542. struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
  5543. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5544. return;
  5545. if (usb_autopm_get_interface(tp->intf) < 0)
  5546. return;
  5547. mutex_lock(&tp->control);
  5548. if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
  5549. tp->rtl_fw.retry = false;
  5550. tp->rtl_fw.fw = NULL;
  5551. /* Delay execution in case request_firmware() is not ready yet.
  5552. */
  5553. queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
  5554. goto ignore_once;
  5555. }
  5556. tp->rtl_ops.hw_phy_cfg(tp);
  5557. rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
  5558. tp->advertising);
  5559. ignore_once:
  5560. mutex_unlock(&tp->control);
  5561. usb_autopm_put_interface(tp->intf);
  5562. }
  5563. #ifdef CONFIG_PM_SLEEP
  5564. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  5565. void *data)
  5566. {
  5567. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  5568. switch (action) {
  5569. case PM_HIBERNATION_PREPARE:
  5570. case PM_SUSPEND_PREPARE:
  5571. usb_autopm_get_interface(tp->intf);
  5572. break;
  5573. case PM_POST_HIBERNATION:
  5574. case PM_POST_SUSPEND:
  5575. usb_autopm_put_interface(tp->intf);
  5576. break;
  5577. case PM_POST_RESTORE:
  5578. case PM_RESTORE_PREPARE:
  5579. default:
  5580. break;
  5581. }
  5582. return NOTIFY_DONE;
  5583. }
  5584. #endif
  5585. static int rtl8152_open(struct net_device *netdev)
  5586. {
  5587. struct r8152 *tp = netdev_priv(netdev);
  5588. int res = 0;
  5589. if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
  5590. cancel_delayed_work_sync(&tp->hw_phy_work);
  5591. rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
  5592. }
  5593. res = alloc_all_mem(tp);
  5594. if (res)
  5595. goto out;
  5596. res = usb_autopm_get_interface(tp->intf);
  5597. if (res < 0)
  5598. goto out_free;
  5599. mutex_lock(&tp->control);
  5600. tp->rtl_ops.up(tp);
  5601. netif_carrier_off(netdev);
  5602. netif_start_queue(netdev);
  5603. set_bit(WORK_ENABLE, &tp->flags);
  5604. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  5605. if (res) {
  5606. if (res == -ENODEV)
  5607. netif_device_detach(tp->netdev);
  5608. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  5609. res);
  5610. goto out_unlock;
  5611. }
  5612. napi_enable(&tp->napi);
  5613. tasklet_enable(&tp->tx_tl);
  5614. mutex_unlock(&tp->control);
  5615. usb_autopm_put_interface(tp->intf);
  5616. #ifdef CONFIG_PM_SLEEP
  5617. tp->pm_notifier.notifier_call = rtl_notifier;
  5618. register_pm_notifier(&tp->pm_notifier);
  5619. #endif
  5620. return 0;
  5621. out_unlock:
  5622. mutex_unlock(&tp->control);
  5623. usb_autopm_put_interface(tp->intf);
  5624. out_free:
  5625. free_all_mem(tp);
  5626. out:
  5627. return res;
  5628. }
  5629. static int rtl8152_close(struct net_device *netdev)
  5630. {
  5631. struct r8152 *tp = netdev_priv(netdev);
  5632. int res = 0;
  5633. #ifdef CONFIG_PM_SLEEP
  5634. unregister_pm_notifier(&tp->pm_notifier);
  5635. #endif
  5636. tasklet_disable(&tp->tx_tl);
  5637. clear_bit(WORK_ENABLE, &tp->flags);
  5638. usb_kill_urb(tp->intr_urb);
  5639. cancel_delayed_work_sync(&tp->schedule);
  5640. napi_disable(&tp->napi);
  5641. netif_stop_queue(netdev);
  5642. res = usb_autopm_get_interface(tp->intf);
  5643. if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
  5644. rtl_drop_queued_tx(tp);
  5645. rtl_stop_rx(tp);
  5646. } else {
  5647. mutex_lock(&tp->control);
  5648. tp->rtl_ops.down(tp);
  5649. mutex_unlock(&tp->control);
  5650. }
  5651. if (!res)
  5652. usb_autopm_put_interface(tp->intf);
  5653. free_all_mem(tp);
  5654. return res;
  5655. }
  5656. static void rtl_tally_reset(struct r8152 *tp)
  5657. {
  5658. u32 ocp_data;
  5659. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  5660. ocp_data |= TALLY_RESET;
  5661. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  5662. }
  5663. static void r8152b_init(struct r8152 *tp)
  5664. {
  5665. u32 ocp_data;
  5666. u16 data;
  5667. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5668. return;
  5669. data = r8152_mdio_read(tp, MII_BMCR);
  5670. if (data & BMCR_PDOWN) {
  5671. data &= ~BMCR_PDOWN;
  5672. r8152_mdio_write(tp, MII_BMCR, data);
  5673. }
  5674. r8152_aldps_en(tp, false);
  5675. if (tp->version == RTL_VER_01) {
  5676. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  5677. ocp_data &= ~LED_MODE_MASK;
  5678. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  5679. }
  5680. r8152_power_cut_en(tp, false);
  5681. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  5682. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  5683. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  5684. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  5685. ocp_data &= ~MCU_CLK_RATIO_MASK;
  5686. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  5687. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  5688. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  5689. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  5690. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  5691. rtl_tally_reset(tp);
  5692. /* enable rx aggregation */
  5693. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  5694. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  5695. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  5696. }
  5697. static void r8153_init(struct r8152 *tp)
  5698. {
  5699. u32 ocp_data;
  5700. u16 data;
  5701. int i;
  5702. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5703. return;
  5704. r8153_u1u2en(tp, false);
  5705. for (i = 0; i < 500; i++) {
  5706. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  5707. AUTOLOAD_DONE)
  5708. break;
  5709. msleep(20);
  5710. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5711. break;
  5712. }
  5713. data = r8153_phy_status(tp, 0);
  5714. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  5715. tp->version == RTL_VER_05)
  5716. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  5717. data = r8152_mdio_read(tp, MII_BMCR);
  5718. if (data & BMCR_PDOWN) {
  5719. data &= ~BMCR_PDOWN;
  5720. r8152_mdio_write(tp, MII_BMCR, data);
  5721. }
  5722. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  5723. r8153_u2p3en(tp, false);
  5724. if (tp->version == RTL_VER_04) {
  5725. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  5726. ocp_data &= ~pwd_dn_scale_mask;
  5727. ocp_data |= pwd_dn_scale(96);
  5728. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  5729. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  5730. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  5731. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  5732. } else if (tp->version == RTL_VER_05) {
  5733. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  5734. ocp_data &= ~ECM_ALDPS;
  5735. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  5736. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  5737. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  5738. ocp_data &= ~DYNAMIC_BURST;
  5739. else
  5740. ocp_data |= DYNAMIC_BURST;
  5741. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  5742. } else if (tp->version == RTL_VER_06) {
  5743. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  5744. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  5745. ocp_data &= ~DYNAMIC_BURST;
  5746. else
  5747. ocp_data |= DYNAMIC_BURST;
  5748. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  5749. r8153_queue_wake(tp, false);
  5750. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  5751. if (rtl8152_get_speed(tp) & LINK_STATUS)
  5752. ocp_data |= CUR_LINK_OK;
  5753. else
  5754. ocp_data &= ~CUR_LINK_OK;
  5755. ocp_data |= POLL_LINK_CHG;
  5756. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  5757. }
  5758. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  5759. ocp_data |= EP4_FULL_FC;
  5760. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  5761. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  5762. ocp_data &= ~TIMER11_EN;
  5763. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  5764. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  5765. ocp_data &= ~LED_MODE_MASK;
  5766. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  5767. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  5768. if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
  5769. ocp_data |= LPM_TIMER_500MS;
  5770. else
  5771. ocp_data |= LPM_TIMER_500US;
  5772. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  5773. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  5774. ocp_data &= ~SEN_VAL_MASK;
  5775. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  5776. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  5777. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  5778. r8153_power_cut_en(tp, false);
  5779. rtl_runtime_suspend_enable(tp, false);
  5780. r8153_mac_clk_speed_down(tp, false);
  5781. r8153_u1u2en(tp, true);
  5782. usb_enable_lpm(tp->udev);
  5783. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
  5784. ocp_data |= LANWAKE_CLR_EN;
  5785. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
  5786. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
  5787. ocp_data &= ~LANWAKE_PIN;
  5788. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
  5789. /* rx aggregation */
  5790. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  5791. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  5792. if (tp->dell_tb_rx_agg_bug)
  5793. ocp_data |= RX_AGG_DISABLE;
  5794. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  5795. rtl_tally_reset(tp);
  5796. switch (tp->udev->speed) {
  5797. case USB_SPEED_SUPER:
  5798. case USB_SPEED_SUPER_PLUS:
  5799. tp->coalesce = COALESCE_SUPER;
  5800. break;
  5801. case USB_SPEED_HIGH:
  5802. tp->coalesce = COALESCE_HIGH;
  5803. break;
  5804. default:
  5805. tp->coalesce = COALESCE_SLOW;
  5806. break;
  5807. }
  5808. }
  5809. static void r8153b_init(struct r8152 *tp)
  5810. {
  5811. u32 ocp_data;
  5812. u16 data;
  5813. int i;
  5814. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5815. return;
  5816. r8153b_u1u2en(tp, false);
  5817. for (i = 0; i < 500; i++) {
  5818. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  5819. AUTOLOAD_DONE)
  5820. break;
  5821. msleep(20);
  5822. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5823. break;
  5824. }
  5825. data = r8153_phy_status(tp, 0);
  5826. data = r8152_mdio_read(tp, MII_BMCR);
  5827. if (data & BMCR_PDOWN) {
  5828. data &= ~BMCR_PDOWN;
  5829. r8152_mdio_write(tp, MII_BMCR, data);
  5830. }
  5831. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  5832. r8153_u2p3en(tp, false);
  5833. /* MSC timer = 0xfff * 8ms = 32760 ms */
  5834. ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
  5835. r8153b_power_cut_en(tp, false);
  5836. r8153b_ups_en(tp, false);
  5837. r8153_queue_wake(tp, false);
  5838. rtl_runtime_suspend_enable(tp, false);
  5839. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  5840. if (rtl8152_get_speed(tp) & LINK_STATUS)
  5841. ocp_data |= CUR_LINK_OK;
  5842. else
  5843. ocp_data &= ~CUR_LINK_OK;
  5844. ocp_data |= POLL_LINK_CHG;
  5845. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  5846. if (tp->udev->speed >= USB_SPEED_SUPER)
  5847. r8153b_u1u2en(tp, true);
  5848. usb_enable_lpm(tp->udev);
  5849. /* MAC clock speed down */
  5850. r8153_mac_clk_speed_down(tp, true);
  5851. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  5852. ocp_data &= ~PLA_MCU_SPDWN_EN;
  5853. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  5854. if (tp->version == RTL_VER_09) {
  5855. /* Disable Test IO for 32QFN */
  5856. if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
  5857. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  5858. ocp_data |= TEST_IO_OFF;
  5859. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  5860. }
  5861. }
  5862. set_bit(GREEN_ETHERNET, &tp->flags);
  5863. /* rx aggregation */
  5864. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  5865. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  5866. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  5867. rtl_tally_reset(tp);
  5868. tp->coalesce = 15000; /* 15 us */
  5869. }
  5870. static void r8153c_init(struct r8152 *tp)
  5871. {
  5872. u32 ocp_data;
  5873. u16 data;
  5874. int i;
  5875. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5876. return;
  5877. r8153b_u1u2en(tp, false);
  5878. /* Disable spi_en */
  5879. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  5880. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  5881. ocp_data &= ~BIT(3);
  5882. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  5883. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
  5884. ocp_data |= BIT(1);
  5885. ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
  5886. for (i = 0; i < 500; i++) {
  5887. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  5888. AUTOLOAD_DONE)
  5889. break;
  5890. msleep(20);
  5891. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  5892. return;
  5893. }
  5894. data = r8153_phy_status(tp, 0);
  5895. data = r8152_mdio_read(tp, MII_BMCR);
  5896. if (data & BMCR_PDOWN) {
  5897. data &= ~BMCR_PDOWN;
  5898. r8152_mdio_write(tp, MII_BMCR, data);
  5899. }
  5900. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  5901. r8153_u2p3en(tp, false);
  5902. /* MSC timer = 0xfff * 8ms = 32760 ms */
  5903. ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
  5904. r8153b_power_cut_en(tp, false);
  5905. r8153c_ups_en(tp, false);
  5906. r8153_queue_wake(tp, false);
  5907. rtl_runtime_suspend_enable(tp, false);
  5908. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  5909. if (rtl8152_get_speed(tp) & LINK_STATUS)
  5910. ocp_data |= CUR_LINK_OK;
  5911. else
  5912. ocp_data &= ~CUR_LINK_OK;
  5913. ocp_data |= POLL_LINK_CHG;
  5914. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  5915. r8153b_u1u2en(tp, true);
  5916. usb_enable_lpm(tp->udev);
  5917. /* MAC clock speed down */
  5918. r8153_mac_clk_speed_down(tp, true);
  5919. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
  5920. ocp_data &= ~BIT(7);
  5921. ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
  5922. set_bit(GREEN_ETHERNET, &tp->flags);
  5923. /* rx aggregation */
  5924. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  5925. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  5926. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  5927. rtl_tally_reset(tp);
  5928. tp->coalesce = 15000; /* 15 us */
  5929. }
  5930. static void r8156_hw_phy_cfg(struct r8152 *tp)
  5931. {
  5932. u32 ocp_data;
  5933. u16 data;
  5934. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  5935. if (ocp_data & PCUT_STATUS) {
  5936. ocp_data &= ~PCUT_STATUS;
  5937. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  5938. }
  5939. data = r8153_phy_status(tp, 0);
  5940. switch (data) {
  5941. case PHY_STAT_EXT_INIT:
  5942. rtl8152_apply_firmware(tp, true);
  5943. data = ocp_reg_read(tp, 0xa468);
  5944. data &= ~(BIT(3) | BIT(1));
  5945. ocp_reg_write(tp, 0xa468, data);
  5946. break;
  5947. case PHY_STAT_LAN_ON:
  5948. case PHY_STAT_PWRDN:
  5949. default:
  5950. rtl8152_apply_firmware(tp, false);
  5951. break;
  5952. }
  5953. /* disable ALDPS before updating the PHY parameters */
  5954. r8153_aldps_en(tp, false);
  5955. /* disable EEE before updating the PHY parameters */
  5956. rtl_eee_enable(tp, false);
  5957. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  5958. WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
  5959. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  5960. ocp_data |= PFM_PWM_SWITCH;
  5961. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  5962. switch (tp->version) {
  5963. case RTL_VER_10:
  5964. data = ocp_reg_read(tp, 0xad40);
  5965. data &= ~0x3ff;
  5966. data |= BIT(7) | BIT(2);
  5967. ocp_reg_write(tp, 0xad40, data);
  5968. data = ocp_reg_read(tp, 0xad4e);
  5969. data |= BIT(4);
  5970. ocp_reg_write(tp, 0xad4e, data);
  5971. data = ocp_reg_read(tp, 0xad16);
  5972. data &= ~0x3ff;
  5973. data |= 0x6;
  5974. ocp_reg_write(tp, 0xad16, data);
  5975. data = ocp_reg_read(tp, 0xad32);
  5976. data &= ~0x3f;
  5977. data |= 6;
  5978. ocp_reg_write(tp, 0xad32, data);
  5979. data = ocp_reg_read(tp, 0xac08);
  5980. data &= ~(BIT(12) | BIT(8));
  5981. ocp_reg_write(tp, 0xac08, data);
  5982. data = ocp_reg_read(tp, 0xac8a);
  5983. data |= BIT(12) | BIT(13) | BIT(14);
  5984. data &= ~BIT(15);
  5985. ocp_reg_write(tp, 0xac8a, data);
  5986. data = ocp_reg_read(tp, 0xad18);
  5987. data |= BIT(10);
  5988. ocp_reg_write(tp, 0xad18, data);
  5989. data = ocp_reg_read(tp, 0xad1a);
  5990. data |= 0x3ff;
  5991. ocp_reg_write(tp, 0xad1a, data);
  5992. data = ocp_reg_read(tp, 0xad1c);
  5993. data |= 0x3ff;
  5994. ocp_reg_write(tp, 0xad1c, data);
  5995. data = sram_read(tp, 0x80ea);
  5996. data &= ~0xff00;
  5997. data |= 0xc400;
  5998. sram_write(tp, 0x80ea, data);
  5999. data = sram_read(tp, 0x80eb);
  6000. data &= ~0x0700;
  6001. data |= 0x0300;
  6002. sram_write(tp, 0x80eb, data);
  6003. data = sram_read(tp, 0x80f8);
  6004. data &= ~0xff00;
  6005. data |= 0x1c00;
  6006. sram_write(tp, 0x80f8, data);
  6007. data = sram_read(tp, 0x80f1);
  6008. data &= ~0xff00;
  6009. data |= 0x3000;
  6010. sram_write(tp, 0x80f1, data);
  6011. data = sram_read(tp, 0x80fe);
  6012. data &= ~0xff00;
  6013. data |= 0xa500;
  6014. sram_write(tp, 0x80fe, data);
  6015. data = sram_read(tp, 0x8102);
  6016. data &= ~0xff00;
  6017. data |= 0x5000;
  6018. sram_write(tp, 0x8102, data);
  6019. data = sram_read(tp, 0x8015);
  6020. data &= ~0xff00;
  6021. data |= 0x3300;
  6022. sram_write(tp, 0x8015, data);
  6023. data = sram_read(tp, 0x8100);
  6024. data &= ~0xff00;
  6025. data |= 0x7000;
  6026. sram_write(tp, 0x8100, data);
  6027. data = sram_read(tp, 0x8014);
  6028. data &= ~0xff00;
  6029. data |= 0xf000;
  6030. sram_write(tp, 0x8014, data);
  6031. data = sram_read(tp, 0x8016);
  6032. data &= ~0xff00;
  6033. data |= 0x6500;
  6034. sram_write(tp, 0x8016, data);
  6035. data = sram_read(tp, 0x80dc);
  6036. data &= ~0xff00;
  6037. data |= 0xed00;
  6038. sram_write(tp, 0x80dc, data);
  6039. data = sram_read(tp, 0x80df);
  6040. data |= BIT(8);
  6041. sram_write(tp, 0x80df, data);
  6042. data = sram_read(tp, 0x80e1);
  6043. data &= ~BIT(8);
  6044. sram_write(tp, 0x80e1, data);
  6045. data = ocp_reg_read(tp, 0xbf06);
  6046. data &= ~0x003f;
  6047. data |= 0x0038;
  6048. ocp_reg_write(tp, 0xbf06, data);
  6049. sram_write(tp, 0x819f, 0xddb6);
  6050. ocp_reg_write(tp, 0xbc34, 0x5555);
  6051. data = ocp_reg_read(tp, 0xbf0a);
  6052. data &= ~0x0e00;
  6053. data |= 0x0a00;
  6054. ocp_reg_write(tp, 0xbf0a, data);
  6055. data = ocp_reg_read(tp, 0xbd2c);
  6056. data &= ~BIT(13);
  6057. ocp_reg_write(tp, 0xbd2c, data);
  6058. break;
  6059. case RTL_VER_11:
  6060. data = ocp_reg_read(tp, 0xad16);
  6061. data |= 0x3ff;
  6062. ocp_reg_write(tp, 0xad16, data);
  6063. data = ocp_reg_read(tp, 0xad32);
  6064. data &= ~0x3f;
  6065. data |= 6;
  6066. ocp_reg_write(tp, 0xad32, data);
  6067. data = ocp_reg_read(tp, 0xac08);
  6068. data &= ~(BIT(12) | BIT(8));
  6069. ocp_reg_write(tp, 0xac08, data);
  6070. data = ocp_reg_read(tp, 0xacc0);
  6071. data &= ~0x3;
  6072. data |= BIT(1);
  6073. ocp_reg_write(tp, 0xacc0, data);
  6074. data = ocp_reg_read(tp, 0xad40);
  6075. data &= ~0xe7;
  6076. data |= BIT(6) | BIT(2);
  6077. ocp_reg_write(tp, 0xad40, data);
  6078. data = ocp_reg_read(tp, 0xac14);
  6079. data &= ~BIT(7);
  6080. ocp_reg_write(tp, 0xac14, data);
  6081. data = ocp_reg_read(tp, 0xac80);
  6082. data &= ~(BIT(8) | BIT(9));
  6083. ocp_reg_write(tp, 0xac80, data);
  6084. data = ocp_reg_read(tp, 0xac5e);
  6085. data &= ~0x7;
  6086. data |= BIT(1);
  6087. ocp_reg_write(tp, 0xac5e, data);
  6088. ocp_reg_write(tp, 0xad4c, 0x00a8);
  6089. ocp_reg_write(tp, 0xac5c, 0x01ff);
  6090. data = ocp_reg_read(tp, 0xac8a);
  6091. data &= ~0xf0;
  6092. data |= BIT(4) | BIT(5);
  6093. ocp_reg_write(tp, 0xac8a, data);
  6094. ocp_reg_write(tp, 0xb87c, 0x8157);
  6095. data = ocp_reg_read(tp, 0xb87e);
  6096. data &= ~0xff00;
  6097. data |= 0x0500;
  6098. ocp_reg_write(tp, 0xb87e, data);
  6099. ocp_reg_write(tp, 0xb87c, 0x8159);
  6100. data = ocp_reg_read(tp, 0xb87e);
  6101. data &= ~0xff00;
  6102. data |= 0x0700;
  6103. ocp_reg_write(tp, 0xb87e, data);
  6104. /* AAGC */
  6105. ocp_reg_write(tp, 0xb87c, 0x80a2);
  6106. ocp_reg_write(tp, 0xb87e, 0x0153);
  6107. ocp_reg_write(tp, 0xb87c, 0x809c);
  6108. ocp_reg_write(tp, 0xb87e, 0x0153);
  6109. /* EEE parameter */
  6110. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
  6111. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
  6112. ocp_data |= EN_XG_LIP | EN_G_LIP;
  6113. ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
  6114. sram_write(tp, 0x8257, 0x020f); /* XG PLL */
  6115. sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
  6116. if (rtl_phy_patch_request(tp, true, true))
  6117. return;
  6118. /* Advance EEE */
  6119. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
  6120. ocp_data |= EEE_SPDWN_EN;
  6121. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
  6122. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  6123. data &= ~(EN_EEE_100 | EN_EEE_1000);
  6124. data |= EN_10M_CLKDIV;
  6125. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  6126. tp->ups_info._10m_ckdiv = true;
  6127. tp->ups_info.eee_plloff_100 = false;
  6128. tp->ups_info.eee_plloff_giga = false;
  6129. data = ocp_reg_read(tp, OCP_POWER_CFG);
  6130. data &= ~EEE_CLKDIV_EN;
  6131. ocp_reg_write(tp, OCP_POWER_CFG, data);
  6132. tp->ups_info.eee_ckdiv = false;
  6133. ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
  6134. ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
  6135. tp->ups_info._250m_ckdiv = false;
  6136. rtl_phy_patch_request(tp, false, true);
  6137. /* enable ADC Ibias Cal */
  6138. data = ocp_reg_read(tp, 0xd068);
  6139. data |= BIT(13);
  6140. ocp_reg_write(tp, 0xd068, data);
  6141. /* enable Thermal Sensor */
  6142. data = sram_read(tp, 0x81a2);
  6143. data &= ~BIT(8);
  6144. sram_write(tp, 0x81a2, data);
  6145. data = ocp_reg_read(tp, 0xb54c);
  6146. data &= ~0xff00;
  6147. data |= 0xdb00;
  6148. ocp_reg_write(tp, 0xb54c, data);
  6149. /* Nway 2.5G Lite */
  6150. data = ocp_reg_read(tp, 0xa454);
  6151. data &= ~BIT(0);
  6152. ocp_reg_write(tp, 0xa454, data);
  6153. /* CS DSP solution */
  6154. data = ocp_reg_read(tp, OCP_10GBT_CTRL);
  6155. data |= RTL_ADV2_5G_F_R;
  6156. ocp_reg_write(tp, OCP_10GBT_CTRL, data);
  6157. data = ocp_reg_read(tp, 0xad4e);
  6158. data &= ~BIT(4);
  6159. ocp_reg_write(tp, 0xad4e, data);
  6160. data = ocp_reg_read(tp, 0xa86a);
  6161. data &= ~BIT(0);
  6162. ocp_reg_write(tp, 0xa86a, data);
  6163. /* MDI SWAP */
  6164. if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
  6165. (ocp_reg_read(tp, 0xd068) & BIT(1))) {
  6166. u16 swap_a, swap_b;
  6167. data = ocp_reg_read(tp, 0xd068);
  6168. data &= ~0x1f;
  6169. data |= 0x1; /* p0 */
  6170. ocp_reg_write(tp, 0xd068, data);
  6171. swap_a = ocp_reg_read(tp, 0xd06a);
  6172. data &= ~0x18;
  6173. data |= 0x18; /* p3 */
  6174. ocp_reg_write(tp, 0xd068, data);
  6175. swap_b = ocp_reg_read(tp, 0xd06a);
  6176. data &= ~0x18; /* p0 */
  6177. ocp_reg_write(tp, 0xd068, data);
  6178. ocp_reg_write(tp, 0xd06a,
  6179. (swap_a & ~0x7ff) | (swap_b & 0x7ff));
  6180. data |= 0x18; /* p3 */
  6181. ocp_reg_write(tp, 0xd068, data);
  6182. ocp_reg_write(tp, 0xd06a,
  6183. (swap_b & ~0x7ff) | (swap_a & 0x7ff));
  6184. data &= ~0x18;
  6185. data |= 0x08; /* p1 */
  6186. ocp_reg_write(tp, 0xd068, data);
  6187. swap_a = ocp_reg_read(tp, 0xd06a);
  6188. data &= ~0x18;
  6189. data |= 0x10; /* p2 */
  6190. ocp_reg_write(tp, 0xd068, data);
  6191. swap_b = ocp_reg_read(tp, 0xd06a);
  6192. data &= ~0x18;
  6193. data |= 0x08; /* p1 */
  6194. ocp_reg_write(tp, 0xd068, data);
  6195. ocp_reg_write(tp, 0xd06a,
  6196. (swap_a & ~0x7ff) | (swap_b & 0x7ff));
  6197. data &= ~0x18;
  6198. data |= 0x10; /* p2 */
  6199. ocp_reg_write(tp, 0xd068, data);
  6200. ocp_reg_write(tp, 0xd06a,
  6201. (swap_b & ~0x7ff) | (swap_a & 0x7ff));
  6202. swap_a = ocp_reg_read(tp, 0xbd5a);
  6203. swap_b = ocp_reg_read(tp, 0xbd5c);
  6204. ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
  6205. ((swap_b & 0x1f) << 8) |
  6206. ((swap_b >> 8) & 0x1f));
  6207. ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
  6208. ((swap_a & 0x1f) << 8) |
  6209. ((swap_a >> 8) & 0x1f));
  6210. swap_a = ocp_reg_read(tp, 0xbc18);
  6211. swap_b = ocp_reg_read(tp, 0xbc1a);
  6212. ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
  6213. ((swap_b & 0x1f) << 8) |
  6214. ((swap_b >> 8) & 0x1f));
  6215. ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
  6216. ((swap_a & 0x1f) << 8) |
  6217. ((swap_a >> 8) & 0x1f));
  6218. }
  6219. /* Notify the MAC when the speed is changed to force mode. */
  6220. data = ocp_reg_read(tp, OCP_INTR_EN);
  6221. data |= INTR_SPEED_FORCE;
  6222. ocp_reg_write(tp, OCP_INTR_EN, data);
  6223. break;
  6224. default:
  6225. break;
  6226. }
  6227. rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
  6228. data = ocp_reg_read(tp, 0xa428);
  6229. data &= ~BIT(9);
  6230. ocp_reg_write(tp, 0xa428, data);
  6231. data = ocp_reg_read(tp, 0xa5ea);
  6232. data &= ~BIT(0);
  6233. ocp_reg_write(tp, 0xa5ea, data);
  6234. tp->ups_info.lite_mode = 0;
  6235. if (tp->eee_en)
  6236. rtl_eee_enable(tp, true);
  6237. r8153_aldps_en(tp, true);
  6238. r8152b_enable_fc(tp);
  6239. r8153_u2p3en(tp, true);
  6240. set_bit(PHY_RESET, &tp->flags);
  6241. }
  6242. static void r8156b_hw_phy_cfg(struct r8152 *tp)
  6243. {
  6244. u32 ocp_data;
  6245. u16 data;
  6246. switch (tp->version) {
  6247. case RTL_VER_12:
  6248. ocp_reg_write(tp, 0xbf86, 0x9000);
  6249. data = ocp_reg_read(tp, 0xc402);
  6250. data |= BIT(10);
  6251. ocp_reg_write(tp, 0xc402, data);
  6252. data &= ~BIT(10);
  6253. ocp_reg_write(tp, 0xc402, data);
  6254. ocp_reg_write(tp, 0xbd86, 0x1010);
  6255. ocp_reg_write(tp, 0xbd88, 0x1010);
  6256. data = ocp_reg_read(tp, 0xbd4e);
  6257. data &= ~(BIT(10) | BIT(11));
  6258. data |= BIT(11);
  6259. ocp_reg_write(tp, 0xbd4e, data);
  6260. data = ocp_reg_read(tp, 0xbf46);
  6261. data &= ~0xf00;
  6262. data |= 0x700;
  6263. ocp_reg_write(tp, 0xbf46, data);
  6264. break;
  6265. case RTL_VER_13:
  6266. case RTL_VER_15:
  6267. r8156b_wait_loading_flash(tp);
  6268. break;
  6269. default:
  6270. break;
  6271. }
  6272. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  6273. if (ocp_data & PCUT_STATUS) {
  6274. ocp_data &= ~PCUT_STATUS;
  6275. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  6276. }
  6277. data = r8153_phy_status(tp, 0);
  6278. switch (data) {
  6279. case PHY_STAT_EXT_INIT:
  6280. rtl8152_apply_firmware(tp, true);
  6281. data = ocp_reg_read(tp, 0xa466);
  6282. data &= ~BIT(0);
  6283. ocp_reg_write(tp, 0xa466, data);
  6284. data = ocp_reg_read(tp, 0xa468);
  6285. data &= ~(BIT(3) | BIT(1));
  6286. ocp_reg_write(tp, 0xa468, data);
  6287. break;
  6288. case PHY_STAT_LAN_ON:
  6289. case PHY_STAT_PWRDN:
  6290. default:
  6291. rtl8152_apply_firmware(tp, false);
  6292. break;
  6293. }
  6294. data = r8152_mdio_read(tp, MII_BMCR);
  6295. if (data & BMCR_PDOWN) {
  6296. data &= ~BMCR_PDOWN;
  6297. r8152_mdio_write(tp, MII_BMCR, data);
  6298. }
  6299. /* disable ALDPS before updating the PHY parameters */
  6300. r8153_aldps_en(tp, false);
  6301. /* disable EEE before updating the PHY parameters */
  6302. rtl_eee_enable(tp, false);
  6303. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  6304. WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
  6305. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  6306. ocp_data |= PFM_PWM_SWITCH;
  6307. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  6308. switch (tp->version) {
  6309. case RTL_VER_12:
  6310. data = ocp_reg_read(tp, 0xbc08);
  6311. data |= BIT(3) | BIT(2);
  6312. ocp_reg_write(tp, 0xbc08, data);
  6313. data = sram_read(tp, 0x8fff);
  6314. data &= ~0xff00;
  6315. data |= 0x0400;
  6316. sram_write(tp, 0x8fff, data);
  6317. data = ocp_reg_read(tp, 0xacda);
  6318. data |= 0xff00;
  6319. ocp_reg_write(tp, 0xacda, data);
  6320. data = ocp_reg_read(tp, 0xacde);
  6321. data |= 0xf000;
  6322. ocp_reg_write(tp, 0xacde, data);
  6323. ocp_reg_write(tp, 0xac8c, 0x0ffc);
  6324. ocp_reg_write(tp, 0xac46, 0xb7b4);
  6325. ocp_reg_write(tp, 0xac50, 0x0fbc);
  6326. ocp_reg_write(tp, 0xac3c, 0x9240);
  6327. ocp_reg_write(tp, 0xac4e, 0x0db4);
  6328. ocp_reg_write(tp, 0xacc6, 0x0707);
  6329. ocp_reg_write(tp, 0xacc8, 0xa0d3);
  6330. ocp_reg_write(tp, 0xad08, 0x0007);
  6331. ocp_reg_write(tp, 0xb87c, 0x8560);
  6332. ocp_reg_write(tp, 0xb87e, 0x19cc);
  6333. ocp_reg_write(tp, 0xb87c, 0x8562);
  6334. ocp_reg_write(tp, 0xb87e, 0x19cc);
  6335. ocp_reg_write(tp, 0xb87c, 0x8564);
  6336. ocp_reg_write(tp, 0xb87e, 0x19cc);
  6337. ocp_reg_write(tp, 0xb87c, 0x8566);
  6338. ocp_reg_write(tp, 0xb87e, 0x147d);
  6339. ocp_reg_write(tp, 0xb87c, 0x8568);
  6340. ocp_reg_write(tp, 0xb87e, 0x147d);
  6341. ocp_reg_write(tp, 0xb87c, 0x856a);
  6342. ocp_reg_write(tp, 0xb87e, 0x147d);
  6343. ocp_reg_write(tp, 0xb87c, 0x8ffe);
  6344. ocp_reg_write(tp, 0xb87e, 0x0907);
  6345. ocp_reg_write(tp, 0xb87c, 0x80d6);
  6346. ocp_reg_write(tp, 0xb87e, 0x2801);
  6347. ocp_reg_write(tp, 0xb87c, 0x80f2);
  6348. ocp_reg_write(tp, 0xb87e, 0x2801);
  6349. ocp_reg_write(tp, 0xb87c, 0x80f4);
  6350. ocp_reg_write(tp, 0xb87e, 0x6077);
  6351. ocp_reg_write(tp, 0xb506, 0x01e7);
  6352. ocp_reg_write(tp, 0xb87c, 0x8013);
  6353. ocp_reg_write(tp, 0xb87e, 0x0700);
  6354. ocp_reg_write(tp, 0xb87c, 0x8fb9);
  6355. ocp_reg_write(tp, 0xb87e, 0x2801);
  6356. ocp_reg_write(tp, 0xb87c, 0x8fba);
  6357. ocp_reg_write(tp, 0xb87e, 0x0100);
  6358. ocp_reg_write(tp, 0xb87c, 0x8fbc);
  6359. ocp_reg_write(tp, 0xb87e, 0x1900);
  6360. ocp_reg_write(tp, 0xb87c, 0x8fbe);
  6361. ocp_reg_write(tp, 0xb87e, 0xe100);
  6362. ocp_reg_write(tp, 0xb87c, 0x8fc0);
  6363. ocp_reg_write(tp, 0xb87e, 0x0800);
  6364. ocp_reg_write(tp, 0xb87c, 0x8fc2);
  6365. ocp_reg_write(tp, 0xb87e, 0xe500);
  6366. ocp_reg_write(tp, 0xb87c, 0x8fc4);
  6367. ocp_reg_write(tp, 0xb87e, 0x0f00);
  6368. ocp_reg_write(tp, 0xb87c, 0x8fc6);
  6369. ocp_reg_write(tp, 0xb87e, 0xf100);
  6370. ocp_reg_write(tp, 0xb87c, 0x8fc8);
  6371. ocp_reg_write(tp, 0xb87e, 0x0400);
  6372. ocp_reg_write(tp, 0xb87c, 0x8fca);
  6373. ocp_reg_write(tp, 0xb87e, 0xf300);
  6374. ocp_reg_write(tp, 0xb87c, 0x8fcc);
  6375. ocp_reg_write(tp, 0xb87e, 0xfd00);
  6376. ocp_reg_write(tp, 0xb87c, 0x8fce);
  6377. ocp_reg_write(tp, 0xb87e, 0xff00);
  6378. ocp_reg_write(tp, 0xb87c, 0x8fd0);
  6379. ocp_reg_write(tp, 0xb87e, 0xfb00);
  6380. ocp_reg_write(tp, 0xb87c, 0x8fd2);
  6381. ocp_reg_write(tp, 0xb87e, 0x0100);
  6382. ocp_reg_write(tp, 0xb87c, 0x8fd4);
  6383. ocp_reg_write(tp, 0xb87e, 0xf400);
  6384. ocp_reg_write(tp, 0xb87c, 0x8fd6);
  6385. ocp_reg_write(tp, 0xb87e, 0xff00);
  6386. ocp_reg_write(tp, 0xb87c, 0x8fd8);
  6387. ocp_reg_write(tp, 0xb87e, 0xf600);
  6388. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
  6389. ocp_data |= EN_XG_LIP | EN_G_LIP;
  6390. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
  6391. ocp_reg_write(tp, 0xb87c, 0x813d);
  6392. ocp_reg_write(tp, 0xb87e, 0x390e);
  6393. ocp_reg_write(tp, 0xb87c, 0x814f);
  6394. ocp_reg_write(tp, 0xb87e, 0x790e);
  6395. ocp_reg_write(tp, 0xb87c, 0x80b0);
  6396. ocp_reg_write(tp, 0xb87e, 0x0f31);
  6397. data = ocp_reg_read(tp, 0xbf4c);
  6398. data |= BIT(1);
  6399. ocp_reg_write(tp, 0xbf4c, data);
  6400. data = ocp_reg_read(tp, 0xbcca);
  6401. data |= BIT(9) | BIT(8);
  6402. ocp_reg_write(tp, 0xbcca, data);
  6403. ocp_reg_write(tp, 0xb87c, 0x8141);
  6404. ocp_reg_write(tp, 0xb87e, 0x320e);
  6405. ocp_reg_write(tp, 0xb87c, 0x8153);
  6406. ocp_reg_write(tp, 0xb87e, 0x720e);
  6407. ocp_reg_write(tp, 0xb87c, 0x8529);
  6408. ocp_reg_write(tp, 0xb87e, 0x050e);
  6409. data = ocp_reg_read(tp, OCP_EEE_CFG);
  6410. data &= ~CTAP_SHORT_EN;
  6411. ocp_reg_write(tp, OCP_EEE_CFG, data);
  6412. sram_write(tp, 0x816c, 0xc4a0);
  6413. sram_write(tp, 0x8170, 0xc4a0);
  6414. sram_write(tp, 0x8174, 0x04a0);
  6415. sram_write(tp, 0x8178, 0x04a0);
  6416. sram_write(tp, 0x817c, 0x0719);
  6417. sram_write(tp, 0x8ff4, 0x0400);
  6418. sram_write(tp, 0x8ff1, 0x0404);
  6419. ocp_reg_write(tp, 0xbf4a, 0x001b);
  6420. ocp_reg_write(tp, 0xb87c, 0x8033);
  6421. ocp_reg_write(tp, 0xb87e, 0x7c13);
  6422. ocp_reg_write(tp, 0xb87c, 0x8037);
  6423. ocp_reg_write(tp, 0xb87e, 0x7c13);
  6424. ocp_reg_write(tp, 0xb87c, 0x803b);
  6425. ocp_reg_write(tp, 0xb87e, 0xfc32);
  6426. ocp_reg_write(tp, 0xb87c, 0x803f);
  6427. ocp_reg_write(tp, 0xb87e, 0x7c13);
  6428. ocp_reg_write(tp, 0xb87c, 0x8043);
  6429. ocp_reg_write(tp, 0xb87e, 0x7c13);
  6430. ocp_reg_write(tp, 0xb87c, 0x8047);
  6431. ocp_reg_write(tp, 0xb87e, 0x7c13);
  6432. ocp_reg_write(tp, 0xb87c, 0x8145);
  6433. ocp_reg_write(tp, 0xb87e, 0x370e);
  6434. ocp_reg_write(tp, 0xb87c, 0x8157);
  6435. ocp_reg_write(tp, 0xb87e, 0x770e);
  6436. ocp_reg_write(tp, 0xb87c, 0x8169);
  6437. ocp_reg_write(tp, 0xb87e, 0x0d0a);
  6438. ocp_reg_write(tp, 0xb87c, 0x817b);
  6439. ocp_reg_write(tp, 0xb87e, 0x1d0a);
  6440. data = sram_read(tp, 0x8217);
  6441. data &= ~0xff00;
  6442. data |= 0x5000;
  6443. sram_write(tp, 0x8217, data);
  6444. data = sram_read(tp, 0x821a);
  6445. data &= ~0xff00;
  6446. data |= 0x5000;
  6447. sram_write(tp, 0x821a, data);
  6448. sram_write(tp, 0x80da, 0x0403);
  6449. data = sram_read(tp, 0x80dc);
  6450. data &= ~0xff00;
  6451. data |= 0x1000;
  6452. sram_write(tp, 0x80dc, data);
  6453. sram_write(tp, 0x80b3, 0x0384);
  6454. sram_write(tp, 0x80b7, 0x2007);
  6455. data = sram_read(tp, 0x80ba);
  6456. data &= ~0xff00;
  6457. data |= 0x6c00;
  6458. sram_write(tp, 0x80ba, data);
  6459. sram_write(tp, 0x80b5, 0xf009);
  6460. data = sram_read(tp, 0x80bd);
  6461. data &= ~0xff00;
  6462. data |= 0x9f00;
  6463. sram_write(tp, 0x80bd, data);
  6464. sram_write(tp, 0x80c7, 0xf083);
  6465. sram_write(tp, 0x80dd, 0x03f0);
  6466. data = sram_read(tp, 0x80df);
  6467. data &= ~0xff00;
  6468. data |= 0x1000;
  6469. sram_write(tp, 0x80df, data);
  6470. sram_write(tp, 0x80cb, 0x2007);
  6471. data = sram_read(tp, 0x80ce);
  6472. data &= ~0xff00;
  6473. data |= 0x6c00;
  6474. sram_write(tp, 0x80ce, data);
  6475. sram_write(tp, 0x80c9, 0x8009);
  6476. data = sram_read(tp, 0x80d1);
  6477. data &= ~0xff00;
  6478. data |= 0x8000;
  6479. sram_write(tp, 0x80d1, data);
  6480. sram_write(tp, 0x80a3, 0x200a);
  6481. sram_write(tp, 0x80a5, 0xf0ad);
  6482. sram_write(tp, 0x809f, 0x6073);
  6483. sram_write(tp, 0x80a1, 0x000b);
  6484. data = sram_read(tp, 0x80a9);
  6485. data &= ~0xff00;
  6486. data |= 0xc000;
  6487. sram_write(tp, 0x80a9, data);
  6488. if (rtl_phy_patch_request(tp, true, true))
  6489. return;
  6490. data = ocp_reg_read(tp, 0xb896);
  6491. data &= ~BIT(0);
  6492. ocp_reg_write(tp, 0xb896, data);
  6493. data = ocp_reg_read(tp, 0xb892);
  6494. data &= ~0xff00;
  6495. ocp_reg_write(tp, 0xb892, data);
  6496. ocp_reg_write(tp, 0xb88e, 0xc23e);
  6497. ocp_reg_write(tp, 0xb890, 0x0000);
  6498. ocp_reg_write(tp, 0xb88e, 0xc240);
  6499. ocp_reg_write(tp, 0xb890, 0x0103);
  6500. ocp_reg_write(tp, 0xb88e, 0xc242);
  6501. ocp_reg_write(tp, 0xb890, 0x0507);
  6502. ocp_reg_write(tp, 0xb88e, 0xc244);
  6503. ocp_reg_write(tp, 0xb890, 0x090b);
  6504. ocp_reg_write(tp, 0xb88e, 0xc246);
  6505. ocp_reg_write(tp, 0xb890, 0x0c0e);
  6506. ocp_reg_write(tp, 0xb88e, 0xc248);
  6507. ocp_reg_write(tp, 0xb890, 0x1012);
  6508. ocp_reg_write(tp, 0xb88e, 0xc24a);
  6509. ocp_reg_write(tp, 0xb890, 0x1416);
  6510. data = ocp_reg_read(tp, 0xb896);
  6511. data |= BIT(0);
  6512. ocp_reg_write(tp, 0xb896, data);
  6513. rtl_phy_patch_request(tp, false, true);
  6514. data = ocp_reg_read(tp, 0xa86a);
  6515. data |= BIT(0);
  6516. ocp_reg_write(tp, 0xa86a, data);
  6517. data = ocp_reg_read(tp, 0xa6f0);
  6518. data |= BIT(0);
  6519. ocp_reg_write(tp, 0xa6f0, data);
  6520. ocp_reg_write(tp, 0xbfa0, 0xd70d);
  6521. ocp_reg_write(tp, 0xbfa2, 0x4100);
  6522. ocp_reg_write(tp, 0xbfa4, 0xe868);
  6523. ocp_reg_write(tp, 0xbfa6, 0xdc59);
  6524. ocp_reg_write(tp, 0xb54c, 0x3c18);
  6525. data = ocp_reg_read(tp, 0xbfa4);
  6526. data &= ~BIT(5);
  6527. ocp_reg_write(tp, 0xbfa4, data);
  6528. data = sram_read(tp, 0x817d);
  6529. data |= BIT(12);
  6530. sram_write(tp, 0x817d, data);
  6531. break;
  6532. case RTL_VER_13:
  6533. /* 2.5G INRX */
  6534. data = ocp_reg_read(tp, 0xac46);
  6535. data &= ~0x00f0;
  6536. data |= 0x0090;
  6537. ocp_reg_write(tp, 0xac46, data);
  6538. data = ocp_reg_read(tp, 0xad30);
  6539. data &= ~0x0003;
  6540. data |= 0x0001;
  6541. ocp_reg_write(tp, 0xad30, data);
  6542. fallthrough;
  6543. case RTL_VER_15:
  6544. /* EEE parameter */
  6545. ocp_reg_write(tp, 0xb87c, 0x80f5);
  6546. ocp_reg_write(tp, 0xb87e, 0x760e);
  6547. ocp_reg_write(tp, 0xb87c, 0x8107);
  6548. ocp_reg_write(tp, 0xb87e, 0x360e);
  6549. ocp_reg_write(tp, 0xb87c, 0x8551);
  6550. data = ocp_reg_read(tp, 0xb87e);
  6551. data &= ~0xff00;
  6552. data |= 0x0800;
  6553. ocp_reg_write(tp, 0xb87e, data);
  6554. /* ADC_PGA parameter */
  6555. data = ocp_reg_read(tp, 0xbf00);
  6556. data &= ~0xe000;
  6557. data |= 0xa000;
  6558. ocp_reg_write(tp, 0xbf00, data);
  6559. data = ocp_reg_read(tp, 0xbf46);
  6560. data &= ~0x0f00;
  6561. data |= 0x0300;
  6562. ocp_reg_write(tp, 0xbf46, data);
  6563. /* Green Table-PGA, 1G full viterbi */
  6564. sram_write(tp, 0x8044, 0x2417);
  6565. sram_write(tp, 0x804a, 0x2417);
  6566. sram_write(tp, 0x8050, 0x2417);
  6567. sram_write(tp, 0x8056, 0x2417);
  6568. sram_write(tp, 0x805c, 0x2417);
  6569. sram_write(tp, 0x8062, 0x2417);
  6570. sram_write(tp, 0x8068, 0x2417);
  6571. sram_write(tp, 0x806e, 0x2417);
  6572. sram_write(tp, 0x8074, 0x2417);
  6573. sram_write(tp, 0x807a, 0x2417);
  6574. /* XG PLL */
  6575. data = ocp_reg_read(tp, 0xbf84);
  6576. data &= ~0xe000;
  6577. data |= 0xa000;
  6578. ocp_reg_write(tp, 0xbf84, data);
  6579. break;
  6580. default:
  6581. break;
  6582. }
  6583. /* Notify the MAC when the speed is changed to force mode. */
  6584. data = ocp_reg_read(tp, OCP_INTR_EN);
  6585. data |= INTR_SPEED_FORCE;
  6586. ocp_reg_write(tp, OCP_INTR_EN, data);
  6587. if (rtl_phy_patch_request(tp, true, true))
  6588. return;
  6589. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
  6590. ocp_data |= EEE_SPDWN_EN;
  6591. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
  6592. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  6593. data &= ~(EN_EEE_100 | EN_EEE_1000);
  6594. data |= EN_10M_CLKDIV;
  6595. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  6596. tp->ups_info._10m_ckdiv = true;
  6597. tp->ups_info.eee_plloff_100 = false;
  6598. tp->ups_info.eee_plloff_giga = false;
  6599. data = ocp_reg_read(tp, OCP_POWER_CFG);
  6600. data &= ~EEE_CLKDIV_EN;
  6601. ocp_reg_write(tp, OCP_POWER_CFG, data);
  6602. tp->ups_info.eee_ckdiv = false;
  6603. rtl_phy_patch_request(tp, false, true);
  6604. rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
  6605. data = ocp_reg_read(tp, 0xa428);
  6606. data &= ~BIT(9);
  6607. ocp_reg_write(tp, 0xa428, data);
  6608. data = ocp_reg_read(tp, 0xa5ea);
  6609. data &= ~BIT(0);
  6610. ocp_reg_write(tp, 0xa5ea, data);
  6611. tp->ups_info.lite_mode = 0;
  6612. if (tp->eee_en)
  6613. rtl_eee_enable(tp, true);
  6614. r8153_aldps_en(tp, true);
  6615. r8152b_enable_fc(tp);
  6616. r8153_u2p3en(tp, true);
  6617. set_bit(PHY_RESET, &tp->flags);
  6618. }
  6619. static void r8156_init(struct r8152 *tp)
  6620. {
  6621. u32 ocp_data;
  6622. u16 data;
  6623. int i;
  6624. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  6625. return;
  6626. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
  6627. ocp_data &= ~EN_ALL_SPEED;
  6628. ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
  6629. ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
  6630. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
  6631. ocp_data |= BYPASS_MAC_RESET;
  6632. ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
  6633. r8153b_u1u2en(tp, false);
  6634. for (i = 0; i < 500; i++) {
  6635. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  6636. AUTOLOAD_DONE)
  6637. break;
  6638. msleep(20);
  6639. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  6640. return;
  6641. }
  6642. data = r8153_phy_status(tp, 0);
  6643. if (data == PHY_STAT_EXT_INIT) {
  6644. data = ocp_reg_read(tp, 0xa468);
  6645. data &= ~(BIT(3) | BIT(1));
  6646. ocp_reg_write(tp, 0xa468, data);
  6647. }
  6648. data = r8152_mdio_read(tp, MII_BMCR);
  6649. if (data & BMCR_PDOWN) {
  6650. data &= ~BMCR_PDOWN;
  6651. r8152_mdio_write(tp, MII_BMCR, data);
  6652. }
  6653. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  6654. WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
  6655. r8153_u2p3en(tp, false);
  6656. /* MSC timer = 0xfff * 8ms = 32760 ms */
  6657. ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
  6658. /* U1/U2/L1 idle timer. 500 us */
  6659. ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
  6660. r8153b_power_cut_en(tp, false);
  6661. r8156_ups_en(tp, false);
  6662. r8153_queue_wake(tp, false);
  6663. rtl_runtime_suspend_enable(tp, false);
  6664. if (tp->udev->speed >= USB_SPEED_SUPER)
  6665. r8153b_u1u2en(tp, true);
  6666. usb_enable_lpm(tp->udev);
  6667. r8156_mac_clk_spd(tp, true);
  6668. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  6669. ocp_data &= ~PLA_MCU_SPDWN_EN;
  6670. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  6671. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  6672. if (rtl8152_get_speed(tp) & LINK_STATUS)
  6673. ocp_data |= CUR_LINK_OK;
  6674. else
  6675. ocp_data &= ~CUR_LINK_OK;
  6676. ocp_data |= POLL_LINK_CHG;
  6677. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  6678. set_bit(GREEN_ETHERNET, &tp->flags);
  6679. /* rx aggregation */
  6680. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  6681. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  6682. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  6683. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
  6684. ocp_data |= ACT_ODMA;
  6685. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
  6686. r8156_mdio_force_mode(tp);
  6687. rtl_tally_reset(tp);
  6688. tp->coalesce = 15000; /* 15 us */
  6689. }
  6690. static void r8156b_init(struct r8152 *tp)
  6691. {
  6692. u32 ocp_data;
  6693. u16 data;
  6694. int i;
  6695. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  6696. return;
  6697. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
  6698. ocp_data &= ~EN_ALL_SPEED;
  6699. ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
  6700. ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
  6701. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
  6702. ocp_data |= BYPASS_MAC_RESET;
  6703. ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
  6704. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  6705. ocp_data |= RX_DETECT8;
  6706. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  6707. r8153b_u1u2en(tp, false);
  6708. switch (tp->version) {
  6709. case RTL_VER_13:
  6710. case RTL_VER_15:
  6711. r8156b_wait_loading_flash(tp);
  6712. break;
  6713. default:
  6714. break;
  6715. }
  6716. for (i = 0; i < 500; i++) {
  6717. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  6718. AUTOLOAD_DONE)
  6719. break;
  6720. msleep(20);
  6721. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  6722. return;
  6723. }
  6724. data = r8153_phy_status(tp, 0);
  6725. if (data == PHY_STAT_EXT_INIT) {
  6726. data = ocp_reg_read(tp, 0xa468);
  6727. data &= ~(BIT(3) | BIT(1));
  6728. ocp_reg_write(tp, 0xa468, data);
  6729. data = ocp_reg_read(tp, 0xa466);
  6730. data &= ~BIT(0);
  6731. ocp_reg_write(tp, 0xa466, data);
  6732. }
  6733. data = r8152_mdio_read(tp, MII_BMCR);
  6734. if (data & BMCR_PDOWN) {
  6735. data &= ~BMCR_PDOWN;
  6736. r8152_mdio_write(tp, MII_BMCR, data);
  6737. }
  6738. data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
  6739. r8153_u2p3en(tp, false);
  6740. /* MSC timer = 0xfff * 8ms = 32760 ms */
  6741. ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
  6742. /* U1/U2/L1 idle timer. 500 us */
  6743. ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
  6744. r8153b_power_cut_en(tp, false);
  6745. r8156_ups_en(tp, false);
  6746. r8153_queue_wake(tp, false);
  6747. rtl_runtime_suspend_enable(tp, false);
  6748. if (tp->udev->speed >= USB_SPEED_SUPER)
  6749. r8153b_u1u2en(tp, true);
  6750. usb_enable_lpm(tp->udev);
  6751. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
  6752. ocp_data &= ~SLOT_EN;
  6753. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  6754. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  6755. ocp_data |= FLOW_CTRL_EN;
  6756. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  6757. /* enable fc timer and set timer to 600 ms. */
  6758. ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
  6759. CTRL_TIMER_EN | (600 / 8));
  6760. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
  6761. if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
  6762. ocp_data |= FLOW_CTRL_PATCH_2;
  6763. ocp_data &= ~AUTO_SPEEDUP;
  6764. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
  6765. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
  6766. ocp_data |= FC_PATCH_TASK;
  6767. ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
  6768. r8156_mac_clk_spd(tp, true);
  6769. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  6770. ocp_data &= ~PLA_MCU_SPDWN_EN;
  6771. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  6772. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
  6773. if (rtl8152_get_speed(tp) & LINK_STATUS)
  6774. ocp_data |= CUR_LINK_OK;
  6775. else
  6776. ocp_data &= ~CUR_LINK_OK;
  6777. ocp_data |= POLL_LINK_CHG;
  6778. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
  6779. set_bit(GREEN_ETHERNET, &tp->flags);
  6780. /* rx aggregation */
  6781. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  6782. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  6783. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  6784. r8156_mdio_force_mode(tp);
  6785. rtl_tally_reset(tp);
  6786. tp->coalesce = 15000; /* 15 us */
  6787. }
  6788. static bool rtl_check_vendor_ok(struct usb_interface *intf)
  6789. {
  6790. struct usb_host_interface *alt = intf->cur_altsetting;
  6791. struct usb_endpoint_descriptor *in, *out, *intr;
  6792. if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
  6793. dev_err(&intf->dev, "Expected endpoints are not found\n");
  6794. return false;
  6795. }
  6796. /* Check Rx endpoint address */
  6797. if (usb_endpoint_num(in) != 1) {
  6798. dev_err(&intf->dev, "Invalid Rx endpoint address\n");
  6799. return false;
  6800. }
  6801. /* Check Tx endpoint address */
  6802. if (usb_endpoint_num(out) != 2) {
  6803. dev_err(&intf->dev, "Invalid Tx endpoint address\n");
  6804. return false;
  6805. }
  6806. /* Check interrupt endpoint address */
  6807. if (usb_endpoint_num(intr) != 3) {
  6808. dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
  6809. return false;
  6810. }
  6811. return true;
  6812. }
  6813. static bool rtl_vendor_mode(struct usb_interface *intf)
  6814. {
  6815. struct usb_host_interface *alt = intf->cur_altsetting;
  6816. struct usb_device *udev;
  6817. struct usb_host_config *c;
  6818. int i, num_configs;
  6819. if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
  6820. return rtl_check_vendor_ok(intf);
  6821. /* The vendor mode is not always config #1, so to find it out. */
  6822. udev = interface_to_usbdev(intf);
  6823. c = udev->config;
  6824. num_configs = udev->descriptor.bNumConfigurations;
  6825. if (num_configs < 2)
  6826. return false;
  6827. for (i = 0; i < num_configs; (i++, c++)) {
  6828. struct usb_interface_descriptor *desc = NULL;
  6829. if (c->desc.bNumInterfaces > 0)
  6830. desc = &c->intf_cache[0]->altsetting->desc;
  6831. else
  6832. continue;
  6833. if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
  6834. usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
  6835. break;
  6836. }
  6837. }
  6838. if (i == num_configs)
  6839. dev_err(&intf->dev, "Unexpected Device\n");
  6840. return false;
  6841. }
  6842. static int rtl8152_pre_reset(struct usb_interface *intf)
  6843. {
  6844. struct r8152 *tp = usb_get_intfdata(intf);
  6845. struct net_device *netdev;
  6846. if (!tp)
  6847. return 0;
  6848. netdev = tp->netdev;
  6849. if (!netif_running(netdev))
  6850. return 0;
  6851. netif_stop_queue(netdev);
  6852. tasklet_disable(&tp->tx_tl);
  6853. clear_bit(WORK_ENABLE, &tp->flags);
  6854. usb_kill_urb(tp->intr_urb);
  6855. cancel_delayed_work_sync(&tp->schedule);
  6856. napi_disable(&tp->napi);
  6857. if (netif_carrier_ok(netdev)) {
  6858. mutex_lock(&tp->control);
  6859. tp->rtl_ops.disable(tp);
  6860. mutex_unlock(&tp->control);
  6861. }
  6862. return 0;
  6863. }
  6864. static int rtl8152_post_reset(struct usb_interface *intf)
  6865. {
  6866. struct r8152 *tp = usb_get_intfdata(intf);
  6867. struct net_device *netdev;
  6868. struct sockaddr sa;
  6869. if (!tp)
  6870. return 0;
  6871. /* reset the MAC address in case of policy change */
  6872. if (determine_ethernet_addr(tp, &sa) >= 0) {
  6873. rtnl_lock();
  6874. dev_set_mac_address (tp->netdev, &sa, NULL);
  6875. rtnl_unlock();
  6876. }
  6877. netdev = tp->netdev;
  6878. if (!netif_running(netdev))
  6879. return 0;
  6880. set_bit(WORK_ENABLE, &tp->flags);
  6881. if (netif_carrier_ok(netdev)) {
  6882. mutex_lock(&tp->control);
  6883. tp->rtl_ops.enable(tp);
  6884. rtl_start_rx(tp);
  6885. _rtl8152_set_rx_mode(netdev);
  6886. mutex_unlock(&tp->control);
  6887. }
  6888. napi_enable(&tp->napi);
  6889. tasklet_enable(&tp->tx_tl);
  6890. netif_wake_queue(netdev);
  6891. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  6892. if (!list_empty(&tp->rx_done))
  6893. napi_schedule(&tp->napi);
  6894. return 0;
  6895. }
  6896. static bool delay_autosuspend(struct r8152 *tp)
  6897. {
  6898. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  6899. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  6900. /* This means a linking change occurs and the driver doesn't detect it,
  6901. * yet. If the driver has disabled tx/rx and hw is linking on, the
  6902. * device wouldn't wake up by receiving any packet.
  6903. */
  6904. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  6905. return true;
  6906. /* If the linking down is occurred by nway, the device may miss the
  6907. * linking change event. And it wouldn't wake when linking on.
  6908. */
  6909. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  6910. return true;
  6911. else if (!skb_queue_empty(&tp->tx_queue))
  6912. return true;
  6913. else
  6914. return false;
  6915. }
  6916. static int rtl8152_runtime_resume(struct r8152 *tp)
  6917. {
  6918. struct net_device *netdev = tp->netdev;
  6919. if (netif_running(netdev) && netdev->flags & IFF_UP) {
  6920. struct napi_struct *napi = &tp->napi;
  6921. tp->rtl_ops.autosuspend_en(tp, false);
  6922. napi_disable(napi);
  6923. set_bit(WORK_ENABLE, &tp->flags);
  6924. if (netif_carrier_ok(netdev)) {
  6925. if (rtl8152_get_speed(tp) & LINK_STATUS) {
  6926. rtl_start_rx(tp);
  6927. } else {
  6928. netif_carrier_off(netdev);
  6929. tp->rtl_ops.disable(tp);
  6930. netif_info(tp, link, netdev, "linking down\n");
  6931. }
  6932. }
  6933. napi_enable(napi);
  6934. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  6935. smp_mb__after_atomic();
  6936. if (!list_empty(&tp->rx_done))
  6937. napi_schedule(&tp->napi);
  6938. usb_submit_urb(tp->intr_urb, GFP_NOIO);
  6939. } else {
  6940. if (netdev->flags & IFF_UP)
  6941. tp->rtl_ops.autosuspend_en(tp, false);
  6942. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  6943. }
  6944. return 0;
  6945. }
  6946. static int rtl8152_system_resume(struct r8152 *tp)
  6947. {
  6948. struct net_device *netdev = tp->netdev;
  6949. netif_device_attach(netdev);
  6950. if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
  6951. tp->rtl_ops.up(tp);
  6952. netif_carrier_off(netdev);
  6953. set_bit(WORK_ENABLE, &tp->flags);
  6954. usb_submit_urb(tp->intr_urb, GFP_NOIO);
  6955. }
  6956. return 0;
  6957. }
  6958. static int rtl8152_runtime_suspend(struct r8152 *tp)
  6959. {
  6960. struct net_device *netdev = tp->netdev;
  6961. int ret = 0;
  6962. if (!tp->rtl_ops.autosuspend_en)
  6963. return -EBUSY;
  6964. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  6965. smp_mb__after_atomic();
  6966. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  6967. u32 rcr = 0;
  6968. if (netif_carrier_ok(netdev)) {
  6969. u32 ocp_data;
  6970. rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  6971. ocp_data = rcr & ~RCR_ACPT_ALL;
  6972. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  6973. rxdy_gated_en(tp, true);
  6974. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
  6975. PLA_OOB_CTRL);
  6976. if (!(ocp_data & RXFIFO_EMPTY)) {
  6977. rxdy_gated_en(tp, false);
  6978. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  6979. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  6980. smp_mb__after_atomic();
  6981. ret = -EBUSY;
  6982. goto out1;
  6983. }
  6984. }
  6985. clear_bit(WORK_ENABLE, &tp->flags);
  6986. usb_kill_urb(tp->intr_urb);
  6987. tp->rtl_ops.autosuspend_en(tp, true);
  6988. if (netif_carrier_ok(netdev)) {
  6989. struct napi_struct *napi = &tp->napi;
  6990. napi_disable(napi);
  6991. rtl_stop_rx(tp);
  6992. rxdy_gated_en(tp, false);
  6993. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  6994. napi_enable(napi);
  6995. }
  6996. if (delay_autosuspend(tp)) {
  6997. rtl8152_runtime_resume(tp);
  6998. ret = -EBUSY;
  6999. }
  7000. }
  7001. out1:
  7002. return ret;
  7003. }
  7004. static int rtl8152_system_suspend(struct r8152 *tp)
  7005. {
  7006. struct net_device *netdev = tp->netdev;
  7007. netif_device_detach(netdev);
  7008. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  7009. struct napi_struct *napi = &tp->napi;
  7010. clear_bit(WORK_ENABLE, &tp->flags);
  7011. usb_kill_urb(tp->intr_urb);
  7012. tasklet_disable(&tp->tx_tl);
  7013. napi_disable(napi);
  7014. cancel_delayed_work_sync(&tp->schedule);
  7015. tp->rtl_ops.down(tp);
  7016. napi_enable(napi);
  7017. tasklet_enable(&tp->tx_tl);
  7018. }
  7019. return 0;
  7020. }
  7021. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  7022. {
  7023. struct r8152 *tp = usb_get_intfdata(intf);
  7024. int ret;
  7025. mutex_lock(&tp->control);
  7026. if (PMSG_IS_AUTO(message))
  7027. ret = rtl8152_runtime_suspend(tp);
  7028. else
  7029. ret = rtl8152_system_suspend(tp);
  7030. mutex_unlock(&tp->control);
  7031. return ret;
  7032. }
  7033. static int rtl8152_resume(struct usb_interface *intf)
  7034. {
  7035. struct r8152 *tp = usb_get_intfdata(intf);
  7036. int ret;
  7037. mutex_lock(&tp->control);
  7038. rtl_reset_ocp_base(tp);
  7039. if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
  7040. ret = rtl8152_runtime_resume(tp);
  7041. else
  7042. ret = rtl8152_system_resume(tp);
  7043. mutex_unlock(&tp->control);
  7044. return ret;
  7045. }
  7046. static int rtl8152_reset_resume(struct usb_interface *intf)
  7047. {
  7048. struct r8152 *tp = usb_get_intfdata(intf);
  7049. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  7050. rtl_reset_ocp_base(tp);
  7051. tp->rtl_ops.init(tp);
  7052. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  7053. set_ethernet_addr(tp, true);
  7054. return rtl8152_resume(intf);
  7055. }
  7056. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  7057. {
  7058. struct r8152 *tp = netdev_priv(dev);
  7059. if (usb_autopm_get_interface(tp->intf) < 0)
  7060. return;
  7061. if (!rtl_can_wakeup(tp)) {
  7062. wol->supported = 0;
  7063. wol->wolopts = 0;
  7064. } else {
  7065. mutex_lock(&tp->control);
  7066. wol->supported = WAKE_ANY;
  7067. wol->wolopts = __rtl_get_wol(tp);
  7068. mutex_unlock(&tp->control);
  7069. }
  7070. usb_autopm_put_interface(tp->intf);
  7071. }
  7072. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  7073. {
  7074. struct r8152 *tp = netdev_priv(dev);
  7075. int ret;
  7076. if (!rtl_can_wakeup(tp))
  7077. return -EOPNOTSUPP;
  7078. if (wol->wolopts & ~WAKE_ANY)
  7079. return -EINVAL;
  7080. ret = usb_autopm_get_interface(tp->intf);
  7081. if (ret < 0)
  7082. goto out_set_wol;
  7083. mutex_lock(&tp->control);
  7084. __rtl_set_wol(tp, wol->wolopts);
  7085. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  7086. mutex_unlock(&tp->control);
  7087. usb_autopm_put_interface(tp->intf);
  7088. out_set_wol:
  7089. return ret;
  7090. }
  7091. static u32 rtl8152_get_msglevel(struct net_device *dev)
  7092. {
  7093. struct r8152 *tp = netdev_priv(dev);
  7094. return tp->msg_enable;
  7095. }
  7096. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  7097. {
  7098. struct r8152 *tp = netdev_priv(dev);
  7099. tp->msg_enable = value;
  7100. }
  7101. static void rtl8152_get_drvinfo(struct net_device *netdev,
  7102. struct ethtool_drvinfo *info)
  7103. {
  7104. struct r8152 *tp = netdev_priv(netdev);
  7105. strscpy(info->driver, MODULENAME, sizeof(info->driver));
  7106. strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
  7107. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  7108. if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
  7109. strscpy(info->fw_version, tp->rtl_fw.version,
  7110. sizeof(info->fw_version));
  7111. }
  7112. static
  7113. int rtl8152_get_link_ksettings(struct net_device *netdev,
  7114. struct ethtool_link_ksettings *cmd)
  7115. {
  7116. struct r8152 *tp = netdev_priv(netdev);
  7117. int ret;
  7118. if (!tp->mii.mdio_read)
  7119. return -EOPNOTSUPP;
  7120. ret = usb_autopm_get_interface(tp->intf);
  7121. if (ret < 0)
  7122. goto out;
  7123. mutex_lock(&tp->control);
  7124. mii_ethtool_get_link_ksettings(&tp->mii, cmd);
  7125. linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  7126. cmd->link_modes.supported, tp->support_2500full);
  7127. if (tp->support_2500full) {
  7128. linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  7129. cmd->link_modes.advertising,
  7130. ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
  7131. linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  7132. cmd->link_modes.lp_advertising,
  7133. ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
  7134. if (is_speed_2500(rtl8152_get_speed(tp)))
  7135. cmd->base.speed = SPEED_2500;
  7136. }
  7137. mutex_unlock(&tp->control);
  7138. usb_autopm_put_interface(tp->intf);
  7139. out:
  7140. return ret;
  7141. }
  7142. static int rtl8152_set_link_ksettings(struct net_device *dev,
  7143. const struct ethtool_link_ksettings *cmd)
  7144. {
  7145. struct r8152 *tp = netdev_priv(dev);
  7146. u32 advertising = 0;
  7147. int ret;
  7148. ret = usb_autopm_get_interface(tp->intf);
  7149. if (ret < 0)
  7150. goto out;
  7151. if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
  7152. cmd->link_modes.advertising))
  7153. advertising |= RTL_ADVERTISED_10_HALF;
  7154. if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
  7155. cmd->link_modes.advertising))
  7156. advertising |= RTL_ADVERTISED_10_FULL;
  7157. if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
  7158. cmd->link_modes.advertising))
  7159. advertising |= RTL_ADVERTISED_100_HALF;
  7160. if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
  7161. cmd->link_modes.advertising))
  7162. advertising |= RTL_ADVERTISED_100_FULL;
  7163. if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
  7164. cmd->link_modes.advertising))
  7165. advertising |= RTL_ADVERTISED_1000_HALF;
  7166. if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
  7167. cmd->link_modes.advertising))
  7168. advertising |= RTL_ADVERTISED_1000_FULL;
  7169. if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
  7170. cmd->link_modes.advertising))
  7171. advertising |= RTL_ADVERTISED_2500_FULL;
  7172. mutex_lock(&tp->control);
  7173. ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
  7174. cmd->base.duplex, advertising);
  7175. if (!ret) {
  7176. tp->autoneg = cmd->base.autoneg;
  7177. tp->speed = cmd->base.speed;
  7178. tp->duplex = cmd->base.duplex;
  7179. tp->advertising = advertising;
  7180. }
  7181. mutex_unlock(&tp->control);
  7182. usb_autopm_put_interface(tp->intf);
  7183. out:
  7184. return ret;
  7185. }
  7186. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  7187. "tx_packets",
  7188. "rx_packets",
  7189. "tx_errors",
  7190. "rx_errors",
  7191. "rx_missed",
  7192. "align_errors",
  7193. "tx_single_collisions",
  7194. "tx_multi_collisions",
  7195. "rx_unicast",
  7196. "rx_broadcast",
  7197. "rx_multicast",
  7198. "tx_aborted",
  7199. "tx_underrun",
  7200. };
  7201. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  7202. {
  7203. switch (sset) {
  7204. case ETH_SS_STATS:
  7205. return ARRAY_SIZE(rtl8152_gstrings);
  7206. default:
  7207. return -EOPNOTSUPP;
  7208. }
  7209. }
  7210. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  7211. struct ethtool_stats *stats, u64 *data)
  7212. {
  7213. struct r8152 *tp = netdev_priv(dev);
  7214. struct tally_counter tally;
  7215. if (usb_autopm_get_interface(tp->intf) < 0)
  7216. return;
  7217. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  7218. usb_autopm_put_interface(tp->intf);
  7219. data[0] = le64_to_cpu(tally.tx_packets);
  7220. data[1] = le64_to_cpu(tally.rx_packets);
  7221. data[2] = le64_to_cpu(tally.tx_errors);
  7222. data[3] = le32_to_cpu(tally.rx_errors);
  7223. data[4] = le16_to_cpu(tally.rx_missed);
  7224. data[5] = le16_to_cpu(tally.align_errors);
  7225. data[6] = le32_to_cpu(tally.tx_one_collision);
  7226. data[7] = le32_to_cpu(tally.tx_multi_collision);
  7227. data[8] = le64_to_cpu(tally.rx_unicast);
  7228. data[9] = le64_to_cpu(tally.rx_broadcast);
  7229. data[10] = le32_to_cpu(tally.rx_multicast);
  7230. data[11] = le16_to_cpu(tally.tx_aborted);
  7231. data[12] = le16_to_cpu(tally.tx_underrun);
  7232. }
  7233. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  7234. {
  7235. switch (stringset) {
  7236. case ETH_SS_STATS:
  7237. memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
  7238. break;
  7239. }
  7240. }
  7241. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  7242. {
  7243. u32 lp, adv, supported = 0;
  7244. u16 val;
  7245. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  7246. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  7247. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  7248. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  7249. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  7250. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  7251. eee->eee_enabled = tp->eee_en;
  7252. eee->eee_active = !!(supported & adv & lp);
  7253. eee->supported = supported;
  7254. eee->advertised = tp->eee_adv;
  7255. eee->lp_advertised = lp;
  7256. return 0;
  7257. }
  7258. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  7259. {
  7260. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  7261. tp->eee_en = eee->eee_enabled;
  7262. tp->eee_adv = val;
  7263. rtl_eee_enable(tp, tp->eee_en);
  7264. return 0;
  7265. }
  7266. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  7267. {
  7268. u32 lp, adv, supported = 0;
  7269. u16 val;
  7270. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  7271. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  7272. val = ocp_reg_read(tp, OCP_EEE_ADV);
  7273. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  7274. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  7275. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  7276. eee->eee_enabled = tp->eee_en;
  7277. eee->eee_active = !!(supported & adv & lp);
  7278. eee->supported = supported;
  7279. eee->advertised = tp->eee_adv;
  7280. eee->lp_advertised = lp;
  7281. return 0;
  7282. }
  7283. static int
  7284. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  7285. {
  7286. struct r8152 *tp = netdev_priv(net);
  7287. int ret;
  7288. if (!tp->rtl_ops.eee_get) {
  7289. ret = -EOPNOTSUPP;
  7290. goto out;
  7291. }
  7292. ret = usb_autopm_get_interface(tp->intf);
  7293. if (ret < 0)
  7294. goto out;
  7295. mutex_lock(&tp->control);
  7296. ret = tp->rtl_ops.eee_get(tp, edata);
  7297. mutex_unlock(&tp->control);
  7298. usb_autopm_put_interface(tp->intf);
  7299. out:
  7300. return ret;
  7301. }
  7302. static int
  7303. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  7304. {
  7305. struct r8152 *tp = netdev_priv(net);
  7306. int ret;
  7307. if (!tp->rtl_ops.eee_set) {
  7308. ret = -EOPNOTSUPP;
  7309. goto out;
  7310. }
  7311. ret = usb_autopm_get_interface(tp->intf);
  7312. if (ret < 0)
  7313. goto out;
  7314. mutex_lock(&tp->control);
  7315. ret = tp->rtl_ops.eee_set(tp, edata);
  7316. if (!ret)
  7317. ret = mii_nway_restart(&tp->mii);
  7318. mutex_unlock(&tp->control);
  7319. usb_autopm_put_interface(tp->intf);
  7320. out:
  7321. return ret;
  7322. }
  7323. static int rtl8152_nway_reset(struct net_device *dev)
  7324. {
  7325. struct r8152 *tp = netdev_priv(dev);
  7326. int ret;
  7327. ret = usb_autopm_get_interface(tp->intf);
  7328. if (ret < 0)
  7329. goto out;
  7330. mutex_lock(&tp->control);
  7331. ret = mii_nway_restart(&tp->mii);
  7332. mutex_unlock(&tp->control);
  7333. usb_autopm_put_interface(tp->intf);
  7334. out:
  7335. return ret;
  7336. }
  7337. static int rtl8152_get_coalesce(struct net_device *netdev,
  7338. struct ethtool_coalesce *coalesce,
  7339. struct kernel_ethtool_coalesce *kernel_coal,
  7340. struct netlink_ext_ack *extack)
  7341. {
  7342. struct r8152 *tp = netdev_priv(netdev);
  7343. switch (tp->version) {
  7344. case RTL_VER_01:
  7345. case RTL_VER_02:
  7346. case RTL_VER_07:
  7347. return -EOPNOTSUPP;
  7348. default:
  7349. break;
  7350. }
  7351. coalesce->rx_coalesce_usecs = tp->coalesce;
  7352. return 0;
  7353. }
  7354. static int rtl8152_set_coalesce(struct net_device *netdev,
  7355. struct ethtool_coalesce *coalesce,
  7356. struct kernel_ethtool_coalesce *kernel_coal,
  7357. struct netlink_ext_ack *extack)
  7358. {
  7359. struct r8152 *tp = netdev_priv(netdev);
  7360. int ret;
  7361. switch (tp->version) {
  7362. case RTL_VER_01:
  7363. case RTL_VER_02:
  7364. case RTL_VER_07:
  7365. return -EOPNOTSUPP;
  7366. default:
  7367. break;
  7368. }
  7369. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  7370. return -EINVAL;
  7371. ret = usb_autopm_get_interface(tp->intf);
  7372. if (ret < 0)
  7373. return ret;
  7374. mutex_lock(&tp->control);
  7375. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  7376. tp->coalesce = coalesce->rx_coalesce_usecs;
  7377. if (netif_running(netdev) && netif_carrier_ok(netdev)) {
  7378. netif_stop_queue(netdev);
  7379. napi_disable(&tp->napi);
  7380. tp->rtl_ops.disable(tp);
  7381. tp->rtl_ops.enable(tp);
  7382. rtl_start_rx(tp);
  7383. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  7384. _rtl8152_set_rx_mode(netdev);
  7385. napi_enable(&tp->napi);
  7386. netif_wake_queue(netdev);
  7387. }
  7388. }
  7389. mutex_unlock(&tp->control);
  7390. usb_autopm_put_interface(tp->intf);
  7391. return ret;
  7392. }
  7393. static int rtl8152_get_tunable(struct net_device *netdev,
  7394. const struct ethtool_tunable *tunable, void *d)
  7395. {
  7396. struct r8152 *tp = netdev_priv(netdev);
  7397. switch (tunable->id) {
  7398. case ETHTOOL_RX_COPYBREAK:
  7399. *(u32 *)d = tp->rx_copybreak;
  7400. break;
  7401. default:
  7402. return -EOPNOTSUPP;
  7403. }
  7404. return 0;
  7405. }
  7406. static int rtl8152_set_tunable(struct net_device *netdev,
  7407. const struct ethtool_tunable *tunable,
  7408. const void *d)
  7409. {
  7410. struct r8152 *tp = netdev_priv(netdev);
  7411. u32 val;
  7412. switch (tunable->id) {
  7413. case ETHTOOL_RX_COPYBREAK:
  7414. val = *(u32 *)d;
  7415. if (val < ETH_ZLEN) {
  7416. netif_err(tp, rx_err, netdev,
  7417. "Invalid rx copy break value\n");
  7418. return -EINVAL;
  7419. }
  7420. if (tp->rx_copybreak != val) {
  7421. if (netdev->flags & IFF_UP) {
  7422. mutex_lock(&tp->control);
  7423. napi_disable(&tp->napi);
  7424. tp->rx_copybreak = val;
  7425. napi_enable(&tp->napi);
  7426. mutex_unlock(&tp->control);
  7427. } else {
  7428. tp->rx_copybreak = val;
  7429. }
  7430. }
  7431. break;
  7432. default:
  7433. return -EOPNOTSUPP;
  7434. }
  7435. return 0;
  7436. }
  7437. static void rtl8152_get_ringparam(struct net_device *netdev,
  7438. struct ethtool_ringparam *ring,
  7439. struct kernel_ethtool_ringparam *kernel_ring,
  7440. struct netlink_ext_ack *extack)
  7441. {
  7442. struct r8152 *tp = netdev_priv(netdev);
  7443. ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
  7444. ring->rx_pending = tp->rx_pending;
  7445. }
  7446. static int rtl8152_set_ringparam(struct net_device *netdev,
  7447. struct ethtool_ringparam *ring,
  7448. struct kernel_ethtool_ringparam *kernel_ring,
  7449. struct netlink_ext_ack *extack)
  7450. {
  7451. struct r8152 *tp = netdev_priv(netdev);
  7452. if (ring->rx_pending < (RTL8152_MAX_RX * 2))
  7453. return -EINVAL;
  7454. if (tp->rx_pending != ring->rx_pending) {
  7455. if (netdev->flags & IFF_UP) {
  7456. mutex_lock(&tp->control);
  7457. napi_disable(&tp->napi);
  7458. tp->rx_pending = ring->rx_pending;
  7459. napi_enable(&tp->napi);
  7460. mutex_unlock(&tp->control);
  7461. } else {
  7462. tp->rx_pending = ring->rx_pending;
  7463. }
  7464. }
  7465. return 0;
  7466. }
  7467. static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
  7468. {
  7469. struct r8152 *tp = netdev_priv(netdev);
  7470. u16 bmcr, lcladv, rmtadv;
  7471. u8 cap;
  7472. if (usb_autopm_get_interface(tp->intf) < 0)
  7473. return;
  7474. mutex_lock(&tp->control);
  7475. bmcr = r8152_mdio_read(tp, MII_BMCR);
  7476. lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
  7477. rmtadv = r8152_mdio_read(tp, MII_LPA);
  7478. mutex_unlock(&tp->control);
  7479. usb_autopm_put_interface(tp->intf);
  7480. if (!(bmcr & BMCR_ANENABLE)) {
  7481. pause->autoneg = 0;
  7482. pause->rx_pause = 0;
  7483. pause->tx_pause = 0;
  7484. return;
  7485. }
  7486. pause->autoneg = 1;
  7487. cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  7488. if (cap & FLOW_CTRL_RX)
  7489. pause->rx_pause = 1;
  7490. if (cap & FLOW_CTRL_TX)
  7491. pause->tx_pause = 1;
  7492. }
  7493. static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
  7494. {
  7495. struct r8152 *tp = netdev_priv(netdev);
  7496. u16 old, new1;
  7497. u8 cap = 0;
  7498. int ret;
  7499. ret = usb_autopm_get_interface(tp->intf);
  7500. if (ret < 0)
  7501. return ret;
  7502. mutex_lock(&tp->control);
  7503. if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
  7504. ret = -EINVAL;
  7505. goto out;
  7506. }
  7507. if (pause->rx_pause)
  7508. cap |= FLOW_CTRL_RX;
  7509. if (pause->tx_pause)
  7510. cap |= FLOW_CTRL_TX;
  7511. old = r8152_mdio_read(tp, MII_ADVERTISE);
  7512. new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
  7513. if (old != new1)
  7514. r8152_mdio_write(tp, MII_ADVERTISE, new1);
  7515. out:
  7516. mutex_unlock(&tp->control);
  7517. usb_autopm_put_interface(tp->intf);
  7518. return ret;
  7519. }
  7520. static const struct ethtool_ops ops = {
  7521. .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
  7522. .get_drvinfo = rtl8152_get_drvinfo,
  7523. .get_link = ethtool_op_get_link,
  7524. .nway_reset = rtl8152_nway_reset,
  7525. .get_msglevel = rtl8152_get_msglevel,
  7526. .set_msglevel = rtl8152_set_msglevel,
  7527. .get_wol = rtl8152_get_wol,
  7528. .set_wol = rtl8152_set_wol,
  7529. .get_strings = rtl8152_get_strings,
  7530. .get_sset_count = rtl8152_get_sset_count,
  7531. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  7532. .get_coalesce = rtl8152_get_coalesce,
  7533. .set_coalesce = rtl8152_set_coalesce,
  7534. .get_eee = rtl_ethtool_get_eee,
  7535. .set_eee = rtl_ethtool_set_eee,
  7536. .get_link_ksettings = rtl8152_get_link_ksettings,
  7537. .set_link_ksettings = rtl8152_set_link_ksettings,
  7538. .get_tunable = rtl8152_get_tunable,
  7539. .set_tunable = rtl8152_set_tunable,
  7540. .get_ringparam = rtl8152_get_ringparam,
  7541. .set_ringparam = rtl8152_set_ringparam,
  7542. .get_pauseparam = rtl8152_get_pauseparam,
  7543. .set_pauseparam = rtl8152_set_pauseparam,
  7544. };
  7545. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  7546. {
  7547. struct r8152 *tp = netdev_priv(netdev);
  7548. struct mii_ioctl_data *data = if_mii(rq);
  7549. int res;
  7550. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  7551. return -ENODEV;
  7552. res = usb_autopm_get_interface(tp->intf);
  7553. if (res < 0)
  7554. goto out;
  7555. switch (cmd) {
  7556. case SIOCGMIIPHY:
  7557. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  7558. break;
  7559. case SIOCGMIIREG:
  7560. mutex_lock(&tp->control);
  7561. data->val_out = r8152_mdio_read(tp, data->reg_num);
  7562. mutex_unlock(&tp->control);
  7563. break;
  7564. case SIOCSMIIREG:
  7565. if (!capable(CAP_NET_ADMIN)) {
  7566. res = -EPERM;
  7567. break;
  7568. }
  7569. mutex_lock(&tp->control);
  7570. r8152_mdio_write(tp, data->reg_num, data->val_in);
  7571. mutex_unlock(&tp->control);
  7572. break;
  7573. default:
  7574. res = -EOPNOTSUPP;
  7575. }
  7576. usb_autopm_put_interface(tp->intf);
  7577. out:
  7578. return res;
  7579. }
  7580. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  7581. {
  7582. struct r8152 *tp = netdev_priv(dev);
  7583. int ret;
  7584. switch (tp->version) {
  7585. case RTL_VER_01:
  7586. case RTL_VER_02:
  7587. case RTL_VER_07:
  7588. dev->mtu = new_mtu;
  7589. return 0;
  7590. default:
  7591. break;
  7592. }
  7593. ret = usb_autopm_get_interface(tp->intf);
  7594. if (ret < 0)
  7595. return ret;
  7596. mutex_lock(&tp->control);
  7597. dev->mtu = new_mtu;
  7598. if (netif_running(dev)) {
  7599. if (tp->rtl_ops.change_mtu)
  7600. tp->rtl_ops.change_mtu(tp);
  7601. if (netif_carrier_ok(dev)) {
  7602. netif_stop_queue(dev);
  7603. napi_disable(&tp->napi);
  7604. tasklet_disable(&tp->tx_tl);
  7605. tp->rtl_ops.disable(tp);
  7606. tp->rtl_ops.enable(tp);
  7607. rtl_start_rx(tp);
  7608. tasklet_enable(&tp->tx_tl);
  7609. napi_enable(&tp->napi);
  7610. rtl8152_set_rx_mode(dev);
  7611. netif_wake_queue(dev);
  7612. }
  7613. }
  7614. mutex_unlock(&tp->control);
  7615. usb_autopm_put_interface(tp->intf);
  7616. return ret;
  7617. }
  7618. static const struct net_device_ops rtl8152_netdev_ops = {
  7619. .ndo_open = rtl8152_open,
  7620. .ndo_stop = rtl8152_close,
  7621. .ndo_eth_ioctl = rtl8152_ioctl,
  7622. .ndo_start_xmit = rtl8152_start_xmit,
  7623. .ndo_tx_timeout = rtl8152_tx_timeout,
  7624. .ndo_set_features = rtl8152_set_features,
  7625. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  7626. .ndo_set_mac_address = rtl8152_set_mac_address,
  7627. .ndo_change_mtu = rtl8152_change_mtu,
  7628. .ndo_validate_addr = eth_validate_addr,
  7629. .ndo_features_check = rtl8152_features_check,
  7630. };
  7631. static void rtl8152_unload(struct r8152 *tp)
  7632. {
  7633. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  7634. return;
  7635. if (tp->version != RTL_VER_01)
  7636. r8152_power_cut_en(tp, true);
  7637. }
  7638. static void rtl8153_unload(struct r8152 *tp)
  7639. {
  7640. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  7641. return;
  7642. r8153_power_cut_en(tp, false);
  7643. }
  7644. static void rtl8153b_unload(struct r8152 *tp)
  7645. {
  7646. if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
  7647. return;
  7648. r8153b_power_cut_en(tp, false);
  7649. }
  7650. static int rtl_ops_init(struct r8152 *tp)
  7651. {
  7652. struct rtl_ops *ops = &tp->rtl_ops;
  7653. int ret = 0;
  7654. switch (tp->version) {
  7655. case RTL_VER_01:
  7656. case RTL_VER_02:
  7657. case RTL_VER_07:
  7658. ops->init = r8152b_init;
  7659. ops->enable = rtl8152_enable;
  7660. ops->disable = rtl8152_disable;
  7661. ops->up = rtl8152_up;
  7662. ops->down = rtl8152_down;
  7663. ops->unload = rtl8152_unload;
  7664. ops->eee_get = r8152_get_eee;
  7665. ops->eee_set = r8152_set_eee;
  7666. ops->in_nway = rtl8152_in_nway;
  7667. ops->hw_phy_cfg = r8152b_hw_phy_cfg;
  7668. ops->autosuspend_en = rtl_runtime_suspend_enable;
  7669. tp->rx_buf_sz = 16 * 1024;
  7670. tp->eee_en = true;
  7671. tp->eee_adv = MDIO_EEE_100TX;
  7672. break;
  7673. case RTL_VER_03:
  7674. case RTL_VER_04:
  7675. case RTL_VER_05:
  7676. case RTL_VER_06:
  7677. ops->init = r8153_init;
  7678. ops->enable = rtl8153_enable;
  7679. ops->disable = rtl8153_disable;
  7680. ops->up = rtl8153_up;
  7681. ops->down = rtl8153_down;
  7682. ops->unload = rtl8153_unload;
  7683. ops->eee_get = r8153_get_eee;
  7684. ops->eee_set = r8152_set_eee;
  7685. ops->in_nway = rtl8153_in_nway;
  7686. ops->hw_phy_cfg = r8153_hw_phy_cfg;
  7687. ops->autosuspend_en = rtl8153_runtime_enable;
  7688. ops->change_mtu = rtl8153_change_mtu;
  7689. if (tp->udev->speed < USB_SPEED_SUPER)
  7690. tp->rx_buf_sz = 16 * 1024;
  7691. else
  7692. tp->rx_buf_sz = 32 * 1024;
  7693. tp->eee_en = true;
  7694. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  7695. break;
  7696. case RTL_VER_08:
  7697. case RTL_VER_09:
  7698. ops->init = r8153b_init;
  7699. ops->enable = rtl8153_enable;
  7700. ops->disable = rtl8153_disable;
  7701. ops->up = rtl8153b_up;
  7702. ops->down = rtl8153b_down;
  7703. ops->unload = rtl8153b_unload;
  7704. ops->eee_get = r8153_get_eee;
  7705. ops->eee_set = r8152_set_eee;
  7706. ops->in_nway = rtl8153_in_nway;
  7707. ops->hw_phy_cfg = r8153b_hw_phy_cfg;
  7708. ops->autosuspend_en = rtl8153b_runtime_enable;
  7709. ops->change_mtu = rtl8153_change_mtu;
  7710. tp->rx_buf_sz = 32 * 1024;
  7711. tp->eee_en = true;
  7712. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  7713. break;
  7714. case RTL_VER_11:
  7715. tp->eee_en = true;
  7716. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  7717. fallthrough;
  7718. case RTL_VER_10:
  7719. ops->init = r8156_init;
  7720. ops->enable = rtl8156_enable;
  7721. ops->disable = rtl8156_disable;
  7722. ops->up = rtl8156_up;
  7723. ops->down = rtl8156_down;
  7724. ops->unload = rtl8153_unload;
  7725. ops->eee_get = r8153_get_eee;
  7726. ops->eee_set = r8152_set_eee;
  7727. ops->in_nway = rtl8153_in_nway;
  7728. ops->hw_phy_cfg = r8156_hw_phy_cfg;
  7729. ops->autosuspend_en = rtl8156_runtime_enable;
  7730. ops->change_mtu = rtl8156_change_mtu;
  7731. tp->rx_buf_sz = 48 * 1024;
  7732. tp->support_2500full = 1;
  7733. break;
  7734. case RTL_VER_12:
  7735. case RTL_VER_13:
  7736. tp->support_2500full = 1;
  7737. fallthrough;
  7738. case RTL_VER_15:
  7739. tp->eee_en = true;
  7740. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  7741. ops->init = r8156b_init;
  7742. ops->enable = rtl8156b_enable;
  7743. ops->disable = rtl8153_disable;
  7744. ops->up = rtl8156_up;
  7745. ops->down = rtl8156_down;
  7746. ops->unload = rtl8153_unload;
  7747. ops->eee_get = r8153_get_eee;
  7748. ops->eee_set = r8152_set_eee;
  7749. ops->in_nway = rtl8153_in_nway;
  7750. ops->hw_phy_cfg = r8156b_hw_phy_cfg;
  7751. ops->autosuspend_en = rtl8156_runtime_enable;
  7752. ops->change_mtu = rtl8156_change_mtu;
  7753. tp->rx_buf_sz = 48 * 1024;
  7754. break;
  7755. case RTL_VER_14:
  7756. ops->init = r8153c_init;
  7757. ops->enable = rtl8153_enable;
  7758. ops->disable = rtl8153_disable;
  7759. ops->up = rtl8153c_up;
  7760. ops->down = rtl8153b_down;
  7761. ops->unload = rtl8153_unload;
  7762. ops->eee_get = r8153_get_eee;
  7763. ops->eee_set = r8152_set_eee;
  7764. ops->in_nway = rtl8153_in_nway;
  7765. ops->hw_phy_cfg = r8153c_hw_phy_cfg;
  7766. ops->autosuspend_en = rtl8153c_runtime_enable;
  7767. ops->change_mtu = rtl8153c_change_mtu;
  7768. tp->rx_buf_sz = 32 * 1024;
  7769. tp->eee_en = true;
  7770. tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
  7771. break;
  7772. default:
  7773. ret = -ENODEV;
  7774. dev_err(&tp->intf->dev, "Unknown Device\n");
  7775. break;
  7776. }
  7777. return ret;
  7778. }
  7779. #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
  7780. #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
  7781. #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
  7782. #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
  7783. #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
  7784. #define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
  7785. #define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
  7786. MODULE_FIRMWARE(FIRMWARE_8153A_2);
  7787. MODULE_FIRMWARE(FIRMWARE_8153A_3);
  7788. MODULE_FIRMWARE(FIRMWARE_8153A_4);
  7789. MODULE_FIRMWARE(FIRMWARE_8153B_2);
  7790. MODULE_FIRMWARE(FIRMWARE_8153C_1);
  7791. MODULE_FIRMWARE(FIRMWARE_8156A_2);
  7792. MODULE_FIRMWARE(FIRMWARE_8156B_2);
  7793. static int rtl_fw_init(struct r8152 *tp)
  7794. {
  7795. struct rtl_fw *rtl_fw = &tp->rtl_fw;
  7796. switch (tp->version) {
  7797. case RTL_VER_04:
  7798. rtl_fw->fw_name = FIRMWARE_8153A_2;
  7799. rtl_fw->pre_fw = r8153_pre_firmware_1;
  7800. rtl_fw->post_fw = r8153_post_firmware_1;
  7801. break;
  7802. case RTL_VER_05:
  7803. rtl_fw->fw_name = FIRMWARE_8153A_3;
  7804. rtl_fw->pre_fw = r8153_pre_firmware_2;
  7805. rtl_fw->post_fw = r8153_post_firmware_2;
  7806. break;
  7807. case RTL_VER_06:
  7808. rtl_fw->fw_name = FIRMWARE_8153A_4;
  7809. rtl_fw->post_fw = r8153_post_firmware_3;
  7810. break;
  7811. case RTL_VER_09:
  7812. rtl_fw->fw_name = FIRMWARE_8153B_2;
  7813. rtl_fw->pre_fw = r8153b_pre_firmware_1;
  7814. rtl_fw->post_fw = r8153b_post_firmware_1;
  7815. break;
  7816. case RTL_VER_11:
  7817. rtl_fw->fw_name = FIRMWARE_8156A_2;
  7818. rtl_fw->post_fw = r8156a_post_firmware_1;
  7819. break;
  7820. case RTL_VER_13:
  7821. case RTL_VER_15:
  7822. rtl_fw->fw_name = FIRMWARE_8156B_2;
  7823. break;
  7824. case RTL_VER_14:
  7825. rtl_fw->fw_name = FIRMWARE_8153C_1;
  7826. rtl_fw->pre_fw = r8153b_pre_firmware_1;
  7827. rtl_fw->post_fw = r8153c_post_firmware_1;
  7828. break;
  7829. default:
  7830. break;
  7831. }
  7832. return 0;
  7833. }
  7834. u8 rtl8152_get_version(struct usb_interface *intf)
  7835. {
  7836. struct usb_device *udev = interface_to_usbdev(intf);
  7837. u32 ocp_data = 0;
  7838. __le32 *tmp;
  7839. u8 version;
  7840. int ret;
  7841. tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
  7842. if (!tmp)
  7843. return 0;
  7844. ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
  7845. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  7846. PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp),
  7847. USB_CTRL_GET_TIMEOUT);
  7848. if (ret > 0)
  7849. ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
  7850. kfree(tmp);
  7851. switch (ocp_data) {
  7852. case 0x4c00:
  7853. version = RTL_VER_01;
  7854. break;
  7855. case 0x4c10:
  7856. version = RTL_VER_02;
  7857. break;
  7858. case 0x5c00:
  7859. version = RTL_VER_03;
  7860. break;
  7861. case 0x5c10:
  7862. version = RTL_VER_04;
  7863. break;
  7864. case 0x5c20:
  7865. version = RTL_VER_05;
  7866. break;
  7867. case 0x5c30:
  7868. version = RTL_VER_06;
  7869. break;
  7870. case 0x4800:
  7871. version = RTL_VER_07;
  7872. break;
  7873. case 0x6000:
  7874. version = RTL_VER_08;
  7875. break;
  7876. case 0x6010:
  7877. version = RTL_VER_09;
  7878. break;
  7879. case 0x7010:
  7880. version = RTL_TEST_01;
  7881. break;
  7882. case 0x7020:
  7883. version = RTL_VER_10;
  7884. break;
  7885. case 0x7030:
  7886. version = RTL_VER_11;
  7887. break;
  7888. case 0x7400:
  7889. version = RTL_VER_12;
  7890. break;
  7891. case 0x7410:
  7892. version = RTL_VER_13;
  7893. break;
  7894. case 0x6400:
  7895. version = RTL_VER_14;
  7896. break;
  7897. case 0x7420:
  7898. version = RTL_VER_15;
  7899. break;
  7900. default:
  7901. version = RTL_VER_UNKNOWN;
  7902. dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
  7903. break;
  7904. }
  7905. dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
  7906. return version;
  7907. }
  7908. EXPORT_SYMBOL_GPL(rtl8152_get_version);
  7909. static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
  7910. {
  7911. int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
  7912. int product_id = le16_to_cpu(udev->descriptor.idProduct);
  7913. int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
  7914. if (vendor_id == VENDOR_ID_LENOVO) {
  7915. switch (product_id) {
  7916. case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
  7917. case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
  7918. case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
  7919. case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
  7920. case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
  7921. case DEVICE_ID_THINKPAD_USB_C_DONGLE:
  7922. return 1;
  7923. }
  7924. } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
  7925. switch (product_id) {
  7926. case 0x8153:
  7927. return 1;
  7928. }
  7929. }
  7930. return 0;
  7931. }
  7932. static int rtl8152_probe(struct usb_interface *intf,
  7933. const struct usb_device_id *id)
  7934. {
  7935. struct usb_device *udev = interface_to_usbdev(intf);
  7936. u8 version = rtl8152_get_version(intf);
  7937. struct r8152 *tp;
  7938. struct net_device *netdev;
  7939. int ret;
  7940. if (version == RTL_VER_UNKNOWN)
  7941. return -ENODEV;
  7942. if (!rtl_vendor_mode(intf))
  7943. return -ENODEV;
  7944. usb_reset_device(udev);
  7945. netdev = alloc_etherdev(sizeof(struct r8152));
  7946. if (!netdev) {
  7947. dev_err(&intf->dev, "Out of memory\n");
  7948. return -ENOMEM;
  7949. }
  7950. SET_NETDEV_DEV(netdev, &intf->dev);
  7951. tp = netdev_priv(netdev);
  7952. tp->msg_enable = 0x7FFF;
  7953. tp->udev = udev;
  7954. tp->netdev = netdev;
  7955. tp->intf = intf;
  7956. tp->version = version;
  7957. tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
  7958. tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
  7959. tp->pipe_in = usb_rcvbulkpipe(udev, 1);
  7960. tp->pipe_out = usb_sndbulkpipe(udev, 2);
  7961. tp->pipe_intr = usb_rcvintpipe(udev, 3);
  7962. switch (version) {
  7963. case RTL_VER_01:
  7964. case RTL_VER_02:
  7965. case RTL_VER_07:
  7966. tp->mii.supports_gmii = 0;
  7967. break;
  7968. default:
  7969. tp->mii.supports_gmii = 1;
  7970. break;
  7971. }
  7972. ret = rtl_ops_init(tp);
  7973. if (ret)
  7974. goto out;
  7975. rtl_fw_init(tp);
  7976. mutex_init(&tp->control);
  7977. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  7978. INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
  7979. tasklet_setup(&tp->tx_tl, bottom_half);
  7980. tasklet_disable(&tp->tx_tl);
  7981. netdev->netdev_ops = &rtl8152_netdev_ops;
  7982. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  7983. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  7984. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  7985. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  7986. NETIF_F_HW_VLAN_CTAG_TX;
  7987. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  7988. NETIF_F_TSO | NETIF_F_FRAGLIST |
  7989. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  7990. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  7991. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  7992. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  7993. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  7994. if (tp->version == RTL_VER_01) {
  7995. netdev->features &= ~NETIF_F_RXCSUM;
  7996. netdev->hw_features &= ~NETIF_F_RXCSUM;
  7997. }
  7998. tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
  7999. if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
  8000. (!strcmp(udev->serial, "000001000000") ||
  8001. !strcmp(udev->serial, "000002000000"))) {
  8002. dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
  8003. tp->dell_tb_rx_agg_bug = 1;
  8004. }
  8005. netdev->ethtool_ops = &ops;
  8006. netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  8007. /* MTU range: 68 - 1500 or 9194 */
  8008. netdev->min_mtu = ETH_MIN_MTU;
  8009. switch (tp->version) {
  8010. case RTL_VER_03:
  8011. case RTL_VER_04:
  8012. case RTL_VER_05:
  8013. case RTL_VER_06:
  8014. case RTL_VER_08:
  8015. case RTL_VER_09:
  8016. case RTL_VER_14:
  8017. netdev->max_mtu = size_to_mtu(9 * 1024);
  8018. break;
  8019. case RTL_VER_10:
  8020. case RTL_VER_11:
  8021. netdev->max_mtu = size_to_mtu(15 * 1024);
  8022. break;
  8023. case RTL_VER_12:
  8024. case RTL_VER_13:
  8025. case RTL_VER_15:
  8026. netdev->max_mtu = size_to_mtu(16 * 1024);
  8027. break;
  8028. case RTL_VER_01:
  8029. case RTL_VER_02:
  8030. case RTL_VER_07:
  8031. default:
  8032. netdev->max_mtu = ETH_DATA_LEN;
  8033. break;
  8034. }
  8035. tp->mii.dev = netdev;
  8036. tp->mii.mdio_read = read_mii_word;
  8037. tp->mii.mdio_write = write_mii_word;
  8038. tp->mii.phy_id_mask = 0x3f;
  8039. tp->mii.reg_num_mask = 0x1f;
  8040. tp->mii.phy_id = R8152_PHY_ID;
  8041. tp->autoneg = AUTONEG_ENABLE;
  8042. tp->speed = SPEED_100;
  8043. tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
  8044. RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
  8045. if (tp->mii.supports_gmii) {
  8046. if (tp->support_2500full &&
  8047. tp->udev->speed >= USB_SPEED_SUPER) {
  8048. tp->speed = SPEED_2500;
  8049. tp->advertising |= RTL_ADVERTISED_2500_FULL;
  8050. } else {
  8051. tp->speed = SPEED_1000;
  8052. }
  8053. tp->advertising |= RTL_ADVERTISED_1000_FULL;
  8054. }
  8055. tp->duplex = DUPLEX_FULL;
  8056. tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
  8057. tp->rx_pending = 10 * RTL8152_MAX_RX;
  8058. intf->needs_remote_wakeup = 1;
  8059. if (!rtl_can_wakeup(tp))
  8060. __rtl_set_wol(tp, 0);
  8061. else
  8062. tp->saved_wolopts = __rtl_get_wol(tp);
  8063. tp->rtl_ops.init(tp);
  8064. #if IS_BUILTIN(CONFIG_USB_RTL8152)
  8065. /* Retry in case request_firmware() is not ready yet. */
  8066. tp->rtl_fw.retry = true;
  8067. #endif
  8068. queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
  8069. set_ethernet_addr(tp, false);
  8070. usb_set_intfdata(intf, tp);
  8071. netif_napi_add_weight(netdev, &tp->napi, r8152_poll,
  8072. tp->support_2500full ? 256 : 64);
  8073. ret = register_netdev(netdev);
  8074. if (ret != 0) {
  8075. dev_err(&intf->dev, "couldn't register the device\n");
  8076. goto out1;
  8077. }
  8078. if (tp->saved_wolopts)
  8079. device_set_wakeup_enable(&udev->dev, true);
  8080. else
  8081. device_set_wakeup_enable(&udev->dev, false);
  8082. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  8083. return 0;
  8084. out1:
  8085. tasklet_kill(&tp->tx_tl);
  8086. cancel_delayed_work_sync(&tp->hw_phy_work);
  8087. if (tp->rtl_ops.unload)
  8088. tp->rtl_ops.unload(tp);
  8089. rtl8152_release_firmware(tp);
  8090. usb_set_intfdata(intf, NULL);
  8091. out:
  8092. free_netdev(netdev);
  8093. return ret;
  8094. }
  8095. static void rtl8152_disconnect(struct usb_interface *intf)
  8096. {
  8097. struct r8152 *tp = usb_get_intfdata(intf);
  8098. usb_set_intfdata(intf, NULL);
  8099. if (tp) {
  8100. rtl_set_unplug(tp);
  8101. unregister_netdev(tp->netdev);
  8102. tasklet_kill(&tp->tx_tl);
  8103. cancel_delayed_work_sync(&tp->hw_phy_work);
  8104. if (tp->rtl_ops.unload)
  8105. tp->rtl_ops.unload(tp);
  8106. rtl8152_release_firmware(tp);
  8107. free_netdev(tp->netdev);
  8108. }
  8109. }
  8110. #define REALTEK_USB_DEVICE(vend, prod) { \
  8111. USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
  8112. }, \
  8113. { \
  8114. USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
  8115. USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
  8116. }
  8117. /* table of devices that work with this driver */
  8118. static const struct usb_device_id rtl8152_table[] = {
  8119. /* Realtek */
  8120. REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
  8121. REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
  8122. REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
  8123. REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
  8124. REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
  8125. REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
  8126. /* Microsoft */
  8127. REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
  8128. REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
  8129. REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
  8130. REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e),
  8131. REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
  8132. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
  8133. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3054),
  8134. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
  8135. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
  8136. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
  8137. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
  8138. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
  8139. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
  8140. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
  8141. REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
  8142. REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
  8143. REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
  8144. REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),
  8145. {}
  8146. };
  8147. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  8148. static struct usb_driver rtl8152_driver = {
  8149. .name = MODULENAME,
  8150. .id_table = rtl8152_table,
  8151. .probe = rtl8152_probe,
  8152. .disconnect = rtl8152_disconnect,
  8153. .suspend = rtl8152_suspend,
  8154. .resume = rtl8152_resume,
  8155. .reset_resume = rtl8152_reset_resume,
  8156. .pre_reset = rtl8152_pre_reset,
  8157. .post_reset = rtl8152_post_reset,
  8158. .supports_autosuspend = 1,
  8159. .disable_hub_initiated_lpm = 1,
  8160. };
  8161. module_usb_driver(rtl8152_driver);
  8162. MODULE_AUTHOR(DRIVER_AUTHOR);
  8163. MODULE_DESCRIPTION(DRIVER_DESC);
  8164. MODULE_LICENSE("GPL");
  8165. MODULE_VERSION(DRIVER_VERSION);