asix.h 7.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * ASIX AX8817X based USB 2.0 Ethernet Devices
  4. * Copyright (C) 2003-2006 David Hollis <[email protected]>
  5. * Copyright (C) 2005 Phil Chang <[email protected]>
  6. * Copyright (C) 2006 James Painter <[email protected]>
  7. * Copyright (c) 2002-2003 TiVo Inc.
  8. */
  9. #ifndef _ASIX_H
  10. #define _ASIX_H
  11. // #define DEBUG // error path messages, extra info
  12. // #define VERBOSE // more; success messages
  13. #include <linux/module.h>
  14. #include <linux/kmod.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/etherdevice.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/mii.h>
  20. #include <linux/usb.h>
  21. #include <linux/crc32.h>
  22. #include <linux/usb/usbnet.h>
  23. #include <linux/slab.h>
  24. #include <linux/if_vlan.h>
  25. #include <linux/phy.h>
  26. #include <net/selftests.h>
  27. #include <linux/phylink.h>
  28. #define DRIVER_VERSION "22-Dec-2011"
  29. #define DRIVER_NAME "asix"
  30. /* ASIX AX8817X based USB 2.0 Ethernet Devices */
  31. #define AX_CMD_SET_SW_MII 0x06
  32. #define AX_CMD_READ_MII_REG 0x07
  33. #define AX_CMD_WRITE_MII_REG 0x08
  34. #define AX_CMD_STATMNGSTS_REG 0x09
  35. #define AX_CMD_SET_HW_MII 0x0a
  36. #define AX_CMD_READ_EEPROM 0x0b
  37. #define AX_CMD_WRITE_EEPROM 0x0c
  38. #define AX_CMD_WRITE_ENABLE 0x0d
  39. #define AX_CMD_WRITE_DISABLE 0x0e
  40. #define AX_CMD_READ_RX_CTL 0x0f
  41. #define AX_CMD_WRITE_RX_CTL 0x10
  42. #define AX_CMD_READ_IPG012 0x11
  43. #define AX_CMD_WRITE_IPG0 0x12
  44. #define AX_CMD_WRITE_IPG1 0x13
  45. #define AX_CMD_READ_NODE_ID 0x13
  46. #define AX_CMD_WRITE_NODE_ID 0x14
  47. #define AX_CMD_WRITE_IPG2 0x14
  48. #define AX_CMD_WRITE_MULTI_FILTER 0x16
  49. #define AX88172_CMD_READ_NODE_ID 0x17
  50. #define AX_CMD_READ_PHY_ID 0x19
  51. #define AX_CMD_READ_MEDIUM_STATUS 0x1a
  52. #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
  53. #define AX_CMD_READ_MONITOR_MODE 0x1c
  54. #define AX_CMD_WRITE_MONITOR_MODE 0x1d
  55. #define AX_CMD_READ_GPIOS 0x1e
  56. #define AX_CMD_WRITE_GPIOS 0x1f
  57. #define AX_CMD_SW_RESET 0x20
  58. #define AX_CMD_SW_PHY_STATUS 0x21
  59. #define AX_CMD_SW_PHY_SELECT 0x22
  60. #define AX_QCTCTRL 0x2A
  61. #define AX_CHIPCODE_MASK 0x70
  62. #define AX_AX88772_CHIPCODE 0x00
  63. #define AX_AX88772A_CHIPCODE 0x10
  64. #define AX_AX88772B_CHIPCODE 0x20
  65. #define AX_HOST_EN 0x01
  66. #define AX_PHYSEL_PSEL 0x01
  67. #define AX_PHYSEL_SSMII 0
  68. #define AX_PHYSEL_SSEN 0x10
  69. #define AX_PHY_SELECT_MASK (BIT(3) | BIT(2))
  70. #define AX_PHY_SELECT_INTERNAL 0
  71. #define AX_PHY_SELECT_EXTERNAL BIT(2)
  72. #define AX_MONITOR_MODE 0x01
  73. #define AX_MONITOR_LINK 0x02
  74. #define AX_MONITOR_MAGIC 0x04
  75. #define AX_MONITOR_HSFS 0x10
  76. /* AX88172 Medium Status Register values */
  77. #define AX88172_MEDIUM_FD 0x02
  78. #define AX88172_MEDIUM_TX 0x04
  79. #define AX88172_MEDIUM_FC 0x10
  80. #define AX88172_MEDIUM_DEFAULT \
  81. ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
  82. #define AX_MCAST_FILTER_SIZE 8
  83. #define AX_MAX_MCAST 64
  84. #define AX_SWRESET_CLEAR 0x00
  85. #define AX_SWRESET_RR 0x01
  86. #define AX_SWRESET_RT 0x02
  87. #define AX_SWRESET_PRTE 0x04
  88. #define AX_SWRESET_PRL 0x08
  89. #define AX_SWRESET_BZ 0x10
  90. #define AX_SWRESET_IPRL 0x20
  91. #define AX_SWRESET_IPPD 0x40
  92. #define AX88772_IPG0_DEFAULT 0x15
  93. #define AX88772_IPG1_DEFAULT 0x0c
  94. #define AX88772_IPG2_DEFAULT 0x12
  95. /* AX88772 & AX88178 Medium Mode Register */
  96. #define AX_MEDIUM_PF 0x0080
  97. #define AX_MEDIUM_JFE 0x0040
  98. #define AX_MEDIUM_TFC 0x0020
  99. #define AX_MEDIUM_RFC 0x0010
  100. #define AX_MEDIUM_ENCK 0x0008
  101. #define AX_MEDIUM_AC 0x0004
  102. #define AX_MEDIUM_FD 0x0002
  103. #define AX_MEDIUM_GM 0x0001
  104. #define AX_MEDIUM_SM 0x1000
  105. #define AX_MEDIUM_SBP 0x0800
  106. #define AX_MEDIUM_PS 0x0200
  107. #define AX_MEDIUM_RE 0x0100
  108. #define AX88178_MEDIUM_DEFAULT \
  109. (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
  110. AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
  111. AX_MEDIUM_RE)
  112. #define AX88772_MEDIUM_DEFAULT \
  113. (AX_MEDIUM_FD | AX_MEDIUM_PS | \
  114. AX_MEDIUM_AC | AX_MEDIUM_RE)
  115. /* AX88772 & AX88178 RX_CTL values */
  116. #define AX_RX_CTL_SO 0x0080
  117. #define AX_RX_CTL_AP 0x0020
  118. #define AX_RX_CTL_AM 0x0010
  119. #define AX_RX_CTL_AB 0x0008
  120. #define AX_RX_CTL_SEP 0x0004
  121. #define AX_RX_CTL_AMALL 0x0002
  122. #define AX_RX_CTL_PRO 0x0001
  123. #define AX_RX_CTL_MFB_2048 0x0000
  124. #define AX_RX_CTL_MFB_4096 0x0100
  125. #define AX_RX_CTL_MFB_8192 0x0200
  126. #define AX_RX_CTL_MFB_16384 0x0300
  127. #define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB)
  128. /* GPIO 0 .. 2 toggles */
  129. #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
  130. #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
  131. #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
  132. #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
  133. #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
  134. #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
  135. #define AX_GPIO_RESERVED 0x40 /* Reserved */
  136. #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
  137. #define AX_EEPROM_MAGIC 0xdeadbeef
  138. #define AX_EEPROM_LEN 0x200
  139. #define AX_EMBD_PHY_ADDR 0x10
  140. /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
  141. struct asix_data {
  142. u8 multi_filter[AX_MCAST_FILTER_SIZE];
  143. u8 mac_addr[ETH_ALEN];
  144. u8 phymode;
  145. u8 ledmode;
  146. u8 res;
  147. };
  148. struct asix_rx_fixup_info {
  149. struct sk_buff *ax_skb;
  150. u32 header;
  151. u16 remaining;
  152. bool split_head;
  153. };
  154. struct asix_common_private {
  155. void (*resume)(struct usbnet *dev);
  156. void (*suspend)(struct usbnet *dev);
  157. int (*reset)(struct usbnet *dev, int in_pm);
  158. u16 presvd_phy_advertise;
  159. u16 presvd_phy_bmcr;
  160. struct asix_rx_fixup_info rx_fixup_info;
  161. struct mii_bus *mdio;
  162. struct phy_device *phydev;
  163. struct phy_device *phydev_int;
  164. struct phylink *phylink;
  165. struct phylink_config phylink_config;
  166. u16 phy_addr;
  167. bool embd_phy;
  168. u8 chipcode;
  169. };
  170. extern const struct driver_info ax88172a_info;
  171. /* ASIX specific flags */
  172. #define FLAG_EEPROM_MAC (1UL << 0) /* init device MAC from eeprom */
  173. int __must_check asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  174. u16 size, void *data, int in_pm);
  175. int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  176. u16 size, void *data, int in_pm);
  177. void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
  178. u16 index, u16 size, void *data);
  179. int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb,
  180. struct asix_rx_fixup_info *rx);
  181. int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb);
  182. void asix_rx_fixup_common_free(struct asix_common_private *dp);
  183. struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
  184. gfp_t flags);
  185. int asix_read_phy_addr(struct usbnet *dev, bool internal);
  186. int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);
  187. u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
  188. int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);
  189. u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
  190. int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);
  191. void asix_adjust_link(struct net_device *netdev);
  192. int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);
  193. void asix_set_multicast(struct net_device *net);
  194. int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
  195. void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);
  196. int asix_mdio_bus_read(struct mii_bus *bus, int phy_id, int regnum);
  197. int asix_mdio_bus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
  198. int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
  199. void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
  200. int val);
  201. void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
  202. int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
  203. int asix_get_eeprom_len(struct net_device *net);
  204. int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
  205. u8 *data);
  206. int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
  207. u8 *data);
  208. void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info);
  209. int asix_set_mac_address(struct net_device *net, void *p);
  210. #endif /* _ASIX_H */