sungem_phy.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PHY drivers for the sungem ethernet driver.
  4. *
  5. * This file could be shared with other drivers.
  6. *
  7. * (c) 2002-2007, Benjamin Herrenscmidt ([email protected])
  8. *
  9. * TODO:
  10. * - Add support for PHYs that provide an IRQ line
  11. * - Eventually moved the entire polling state machine in
  12. * there (out of the eth driver), so that it can easily be
  13. * skipped on PHYs that implement it in hardware.
  14. * - On LXT971 & BCM5201, Apple uses some chip specific regs
  15. * to read the link status. Figure out why and if it makes
  16. * sense to do the same (magic aneg ?)
  17. * - Apple has some additional power management code for some
  18. * Broadcom PHYs that they "hide" from the OpenSource version
  19. * of darwin, still need to reverse engineer that
  20. */
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/mii.h>
  27. #include <linux/ethtool.h>
  28. #include <linux/delay.h>
  29. #include <linux/of.h>
  30. #include <linux/sungem_phy.h>
  31. /* Link modes of the BCM5400 PHY */
  32. static const int phy_BCM5400_link_table[8][3] = {
  33. { 0, 0, 0 }, /* No link */
  34. { 0, 0, 0 }, /* 10BT Half Duplex */
  35. { 1, 0, 0 }, /* 10BT Full Duplex */
  36. { 0, 1, 0 }, /* 100BT Half Duplex */
  37. { 0, 1, 0 }, /* 100BT Half Duplex */
  38. { 1, 1, 0 }, /* 100BT Full Duplex*/
  39. { 1, 0, 1 }, /* 1000BT */
  40. { 1, 0, 1 }, /* 1000BT */
  41. };
  42. static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg)
  43. {
  44. return phy->mdio_read(phy->dev, id, reg);
  45. }
  46. static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val)
  47. {
  48. phy->mdio_write(phy->dev, id, reg, val);
  49. }
  50. static inline int sungem_phy_read(struct mii_phy* phy, int reg)
  51. {
  52. return phy->mdio_read(phy->dev, phy->mii_id, reg);
  53. }
  54. static inline void sungem_phy_write(struct mii_phy* phy, int reg, int val)
  55. {
  56. phy->mdio_write(phy->dev, phy->mii_id, reg, val);
  57. }
  58. static int reset_one_mii_phy(struct mii_phy* phy, int phy_id)
  59. {
  60. u16 val;
  61. int limit = 10000;
  62. val = __sungem_phy_read(phy, phy_id, MII_BMCR);
  63. val &= ~(BMCR_ISOLATE | BMCR_PDOWN);
  64. val |= BMCR_RESET;
  65. __sungem_phy_write(phy, phy_id, MII_BMCR, val);
  66. udelay(100);
  67. while (--limit) {
  68. val = __sungem_phy_read(phy, phy_id, MII_BMCR);
  69. if ((val & BMCR_RESET) == 0)
  70. break;
  71. udelay(10);
  72. }
  73. if ((val & BMCR_ISOLATE) && limit > 0)
  74. __sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
  75. return limit <= 0;
  76. }
  77. static int bcm5201_init(struct mii_phy* phy)
  78. {
  79. u16 data;
  80. data = sungem_phy_read(phy, MII_BCM5201_MULTIPHY);
  81. data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
  82. sungem_phy_write(phy, MII_BCM5201_MULTIPHY, data);
  83. sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
  84. return 0;
  85. }
  86. static int bcm5201_suspend(struct mii_phy* phy)
  87. {
  88. sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
  89. sungem_phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
  90. return 0;
  91. }
  92. static int bcm5221_init(struct mii_phy* phy)
  93. {
  94. u16 data;
  95. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  96. sungem_phy_write(phy, MII_BCM5221_TEST,
  97. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  98. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
  99. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
  100. data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
  101. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  102. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  103. data | MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR);
  104. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  105. sungem_phy_write(phy, MII_BCM5221_TEST,
  106. data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
  107. return 0;
  108. }
  109. static int bcm5221_suspend(struct mii_phy* phy)
  110. {
  111. u16 data;
  112. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  113. sungem_phy_write(phy, MII_BCM5221_TEST,
  114. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  115. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  116. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  117. data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
  118. return 0;
  119. }
  120. static int bcm5241_init(struct mii_phy* phy)
  121. {
  122. u16 data;
  123. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  124. sungem_phy_write(phy, MII_BCM5221_TEST,
  125. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  126. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
  127. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
  128. data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
  129. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  130. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  131. data & ~MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
  132. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  133. sungem_phy_write(phy, MII_BCM5221_TEST,
  134. data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
  135. return 0;
  136. }
  137. static int bcm5241_suspend(struct mii_phy* phy)
  138. {
  139. u16 data;
  140. data = sungem_phy_read(phy, MII_BCM5221_TEST);
  141. sungem_phy_write(phy, MII_BCM5221_TEST,
  142. data | MII_BCM5221_TEST_ENABLE_SHADOWS);
  143. data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
  144. sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
  145. data | MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
  146. return 0;
  147. }
  148. static int bcm5400_init(struct mii_phy* phy)
  149. {
  150. u16 data;
  151. /* Configure for gigabit full duplex */
  152. data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
  153. data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
  154. sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
  155. data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
  156. data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
  157. sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
  158. udelay(100);
  159. /* Reset and configure cascaded 10/100 PHY */
  160. (void)reset_one_mii_phy(phy, 0x1f);
  161. data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
  162. data |= MII_BCM5201_MULTIPHY_SERIALMODE;
  163. __sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
  164. data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
  165. data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
  166. sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
  167. return 0;
  168. }
  169. static int bcm5400_suspend(struct mii_phy* phy)
  170. {
  171. #if 0 /* Commented out in Darwin... someone has those dawn docs ? */
  172. sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
  173. #endif
  174. return 0;
  175. }
  176. static int bcm5401_init(struct mii_phy* phy)
  177. {
  178. u16 data;
  179. int rev;
  180. rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
  181. if (rev == 0 || rev == 3) {
  182. /* Some revisions of 5401 appear to need this
  183. * initialisation sequence to disable, according
  184. * to OF, "tap power management"
  185. *
  186. * WARNING ! OF and Darwin don't agree on the
  187. * register addresses. OF seem to interpret the
  188. * register numbers below as decimal
  189. *
  190. * Note: This should (and does) match tg3_init_5401phy_dsp
  191. * in the tg3.c driver. -DaveM
  192. */
  193. sungem_phy_write(phy, 0x18, 0x0c20);
  194. sungem_phy_write(phy, 0x17, 0x0012);
  195. sungem_phy_write(phy, 0x15, 0x1804);
  196. sungem_phy_write(phy, 0x17, 0x0013);
  197. sungem_phy_write(phy, 0x15, 0x1204);
  198. sungem_phy_write(phy, 0x17, 0x8006);
  199. sungem_phy_write(phy, 0x15, 0x0132);
  200. sungem_phy_write(phy, 0x17, 0x8006);
  201. sungem_phy_write(phy, 0x15, 0x0232);
  202. sungem_phy_write(phy, 0x17, 0x201f);
  203. sungem_phy_write(phy, 0x15, 0x0a20);
  204. }
  205. /* Configure for gigabit full duplex */
  206. data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
  207. data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
  208. sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
  209. udelay(10);
  210. /* Reset and configure cascaded 10/100 PHY */
  211. (void)reset_one_mii_phy(phy, 0x1f);
  212. data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
  213. data |= MII_BCM5201_MULTIPHY_SERIALMODE;
  214. __sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
  215. return 0;
  216. }
  217. static int bcm5401_suspend(struct mii_phy* phy)
  218. {
  219. #if 0 /* Commented out in Darwin... someone has those dawn docs ? */
  220. sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
  221. #endif
  222. return 0;
  223. }
  224. static int bcm5411_init(struct mii_phy* phy)
  225. {
  226. u16 data;
  227. /* Here's some more Apple black magic to setup
  228. * some voltage stuffs.
  229. */
  230. sungem_phy_write(phy, 0x1c, 0x8c23);
  231. sungem_phy_write(phy, 0x1c, 0x8ca3);
  232. sungem_phy_write(phy, 0x1c, 0x8c23);
  233. /* Here, Apple seems to want to reset it, do
  234. * it as well
  235. */
  236. sungem_phy_write(phy, MII_BMCR, BMCR_RESET);
  237. sungem_phy_write(phy, MII_BMCR, 0x1340);
  238. data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
  239. data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
  240. sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
  241. udelay(10);
  242. /* Reset and configure cascaded 10/100 PHY */
  243. (void)reset_one_mii_phy(phy, 0x1f);
  244. return 0;
  245. }
  246. static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
  247. {
  248. u16 ctl, adv;
  249. phy->autoneg = 1;
  250. phy->speed = SPEED_10;
  251. phy->duplex = DUPLEX_HALF;
  252. phy->pause = 0;
  253. phy->advertising = advertise;
  254. /* Setup standard advertise */
  255. adv = sungem_phy_read(phy, MII_ADVERTISE);
  256. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  257. if (advertise & ADVERTISED_10baseT_Half)
  258. adv |= ADVERTISE_10HALF;
  259. if (advertise & ADVERTISED_10baseT_Full)
  260. adv |= ADVERTISE_10FULL;
  261. if (advertise & ADVERTISED_100baseT_Half)
  262. adv |= ADVERTISE_100HALF;
  263. if (advertise & ADVERTISED_100baseT_Full)
  264. adv |= ADVERTISE_100FULL;
  265. sungem_phy_write(phy, MII_ADVERTISE, adv);
  266. /* Start/Restart aneg */
  267. ctl = sungem_phy_read(phy, MII_BMCR);
  268. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  269. sungem_phy_write(phy, MII_BMCR, ctl);
  270. return 0;
  271. }
  272. static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
  273. {
  274. u16 ctl;
  275. phy->autoneg = 0;
  276. phy->speed = speed;
  277. phy->duplex = fd;
  278. phy->pause = 0;
  279. ctl = sungem_phy_read(phy, MII_BMCR);
  280. ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE);
  281. /* First reset the PHY */
  282. sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
  283. /* Select speed & duplex */
  284. switch(speed) {
  285. case SPEED_10:
  286. break;
  287. case SPEED_100:
  288. ctl |= BMCR_SPEED100;
  289. break;
  290. case SPEED_1000:
  291. default:
  292. return -EINVAL;
  293. }
  294. if (fd == DUPLEX_FULL)
  295. ctl |= BMCR_FULLDPLX;
  296. sungem_phy_write(phy, MII_BMCR, ctl);
  297. return 0;
  298. }
  299. static int genmii_poll_link(struct mii_phy *phy)
  300. {
  301. u16 status;
  302. (void)sungem_phy_read(phy, MII_BMSR);
  303. status = sungem_phy_read(phy, MII_BMSR);
  304. if ((status & BMSR_LSTATUS) == 0)
  305. return 0;
  306. if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
  307. return 0;
  308. return 1;
  309. }
  310. static int genmii_read_link(struct mii_phy *phy)
  311. {
  312. u16 lpa;
  313. if (phy->autoneg) {
  314. lpa = sungem_phy_read(phy, MII_LPA);
  315. if (lpa & (LPA_10FULL | LPA_100FULL))
  316. phy->duplex = DUPLEX_FULL;
  317. else
  318. phy->duplex = DUPLEX_HALF;
  319. if (lpa & (LPA_100FULL | LPA_100HALF))
  320. phy->speed = SPEED_100;
  321. else
  322. phy->speed = SPEED_10;
  323. phy->pause = 0;
  324. }
  325. /* On non-aneg, we assume what we put in BMCR is the speed,
  326. * though magic-aneg shouldn't prevent this case from occurring
  327. */
  328. return 0;
  329. }
  330. static int generic_suspend(struct mii_phy* phy)
  331. {
  332. sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
  333. return 0;
  334. }
  335. static int bcm5421_init(struct mii_phy* phy)
  336. {
  337. u16 data;
  338. unsigned int id;
  339. id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
  340. /* Revision 0 of 5421 needs some fixups */
  341. if (id == 0x002060e0) {
  342. /* This is borrowed from MacOS
  343. */
  344. sungem_phy_write(phy, 0x18, 0x1007);
  345. data = sungem_phy_read(phy, 0x18);
  346. sungem_phy_write(phy, 0x18, data | 0x0400);
  347. sungem_phy_write(phy, 0x18, 0x0007);
  348. data = sungem_phy_read(phy, 0x18);
  349. sungem_phy_write(phy, 0x18, data | 0x0800);
  350. sungem_phy_write(phy, 0x17, 0x000a);
  351. data = sungem_phy_read(phy, 0x15);
  352. sungem_phy_write(phy, 0x15, data | 0x0200);
  353. }
  354. /* Pick up some init code from OF for K2 version */
  355. if ((id & 0xfffffff0) == 0x002062e0) {
  356. sungem_phy_write(phy, 4, 0x01e1);
  357. sungem_phy_write(phy, 9, 0x0300);
  358. }
  359. /* Check if we can enable automatic low power */
  360. #ifdef CONFIG_PPC_PMAC
  361. if (phy->platform_data) {
  362. struct device_node *np = of_get_parent(phy->platform_data);
  363. int can_low_power = 1;
  364. if (np == NULL || of_get_property(np, "no-autolowpower", NULL))
  365. can_low_power = 0;
  366. of_node_put(np);
  367. if (can_low_power) {
  368. /* Enable automatic low-power */
  369. sungem_phy_write(phy, 0x1c, 0x9002);
  370. sungem_phy_write(phy, 0x1c, 0xa821);
  371. sungem_phy_write(phy, 0x1c, 0x941d);
  372. }
  373. }
  374. #endif /* CONFIG_PPC_PMAC */
  375. return 0;
  376. }
  377. static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
  378. {
  379. u16 ctl, adv;
  380. phy->autoneg = 1;
  381. phy->speed = SPEED_10;
  382. phy->duplex = DUPLEX_HALF;
  383. phy->pause = 0;
  384. phy->advertising = advertise;
  385. /* Setup standard advertise */
  386. adv = sungem_phy_read(phy, MII_ADVERTISE);
  387. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  388. if (advertise & ADVERTISED_10baseT_Half)
  389. adv |= ADVERTISE_10HALF;
  390. if (advertise & ADVERTISED_10baseT_Full)
  391. adv |= ADVERTISE_10FULL;
  392. if (advertise & ADVERTISED_100baseT_Half)
  393. adv |= ADVERTISE_100HALF;
  394. if (advertise & ADVERTISED_100baseT_Full)
  395. adv |= ADVERTISE_100FULL;
  396. if (advertise & ADVERTISED_Pause)
  397. adv |= ADVERTISE_PAUSE_CAP;
  398. if (advertise & ADVERTISED_Asym_Pause)
  399. adv |= ADVERTISE_PAUSE_ASYM;
  400. sungem_phy_write(phy, MII_ADVERTISE, adv);
  401. /* Setup 1000BT advertise */
  402. adv = sungem_phy_read(phy, MII_1000BASETCONTROL);
  403. adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP|MII_1000BASETCONTROL_HALFDUPLEXCAP);
  404. if (advertise & SUPPORTED_1000baseT_Half)
  405. adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
  406. if (advertise & SUPPORTED_1000baseT_Full)
  407. adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
  408. sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
  409. /* Start/Restart aneg */
  410. ctl = sungem_phy_read(phy, MII_BMCR);
  411. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  412. sungem_phy_write(phy, MII_BMCR, ctl);
  413. return 0;
  414. }
  415. static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
  416. {
  417. u16 ctl;
  418. phy->autoneg = 0;
  419. phy->speed = speed;
  420. phy->duplex = fd;
  421. phy->pause = 0;
  422. ctl = sungem_phy_read(phy, MII_BMCR);
  423. ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
  424. /* First reset the PHY */
  425. sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
  426. /* Select speed & duplex */
  427. switch(speed) {
  428. case SPEED_10:
  429. break;
  430. case SPEED_100:
  431. ctl |= BMCR_SPEED100;
  432. break;
  433. case SPEED_1000:
  434. ctl |= BMCR_SPD2;
  435. }
  436. if (fd == DUPLEX_FULL)
  437. ctl |= BMCR_FULLDPLX;
  438. // XXX Should we set the sungem to GII now on 1000BT ?
  439. sungem_phy_write(phy, MII_BMCR, ctl);
  440. return 0;
  441. }
  442. static int bcm54xx_read_link(struct mii_phy *phy)
  443. {
  444. int link_mode;
  445. u16 val;
  446. if (phy->autoneg) {
  447. val = sungem_phy_read(phy, MII_BCM5400_AUXSTATUS);
  448. link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
  449. MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
  450. phy->duplex = phy_BCM5400_link_table[link_mode][0] ?
  451. DUPLEX_FULL : DUPLEX_HALF;
  452. phy->speed = phy_BCM5400_link_table[link_mode][2] ?
  453. SPEED_1000 :
  454. (phy_BCM5400_link_table[link_mode][1] ?
  455. SPEED_100 : SPEED_10);
  456. val = sungem_phy_read(phy, MII_LPA);
  457. phy->pause = (phy->duplex == DUPLEX_FULL) &&
  458. ((val & LPA_PAUSE) != 0);
  459. }
  460. /* On non-aneg, we assume what we put in BMCR is the speed,
  461. * though magic-aneg shouldn't prevent this case from occurring
  462. */
  463. return 0;
  464. }
  465. static int marvell88e1111_init(struct mii_phy* phy)
  466. {
  467. u16 rev;
  468. /* magic init sequence for rev 0 */
  469. rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
  470. if (rev == 0) {
  471. sungem_phy_write(phy, 0x1d, 0x000a);
  472. sungem_phy_write(phy, 0x1e, 0x0821);
  473. sungem_phy_write(phy, 0x1d, 0x0006);
  474. sungem_phy_write(phy, 0x1e, 0x8600);
  475. sungem_phy_write(phy, 0x1d, 0x000b);
  476. sungem_phy_write(phy, 0x1e, 0x0100);
  477. sungem_phy_write(phy, 0x1d, 0x0004);
  478. sungem_phy_write(phy, 0x1e, 0x4850);
  479. }
  480. return 0;
  481. }
  482. #define BCM5421_MODE_MASK (1 << 5)
  483. static int bcm5421_poll_link(struct mii_phy* phy)
  484. {
  485. u32 phy_reg;
  486. int mode;
  487. /* find out in what mode we are */
  488. sungem_phy_write(phy, MII_NCONFIG, 0x1000);
  489. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  490. mode = (phy_reg & BCM5421_MODE_MASK) >> 5;
  491. if ( mode == BCM54XX_COPPER)
  492. return genmii_poll_link(phy);
  493. /* try to find out whether we have a link */
  494. sungem_phy_write(phy, MII_NCONFIG, 0x2000);
  495. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  496. if (phy_reg & 0x0020)
  497. return 0;
  498. else
  499. return 1;
  500. }
  501. static int bcm5421_read_link(struct mii_phy* phy)
  502. {
  503. u32 phy_reg;
  504. int mode;
  505. /* find out in what mode we are */
  506. sungem_phy_write(phy, MII_NCONFIG, 0x1000);
  507. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  508. mode = (phy_reg & BCM5421_MODE_MASK ) >> 5;
  509. if ( mode == BCM54XX_COPPER)
  510. return bcm54xx_read_link(phy);
  511. phy->speed = SPEED_1000;
  512. /* find out whether we are running half- or full duplex */
  513. sungem_phy_write(phy, MII_NCONFIG, 0x2000);
  514. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  515. if ( (phy_reg & 0x0080) >> 7)
  516. phy->duplex |= DUPLEX_HALF;
  517. else
  518. phy->duplex |= DUPLEX_FULL;
  519. return 0;
  520. }
  521. static int bcm5421_enable_fiber(struct mii_phy* phy, int autoneg)
  522. {
  523. /* enable fiber mode */
  524. sungem_phy_write(phy, MII_NCONFIG, 0x9020);
  525. /* LEDs active in both modes, autosense prio = fiber */
  526. sungem_phy_write(phy, MII_NCONFIG, 0x945f);
  527. if (!autoneg) {
  528. /* switch off fibre autoneg */
  529. sungem_phy_write(phy, MII_NCONFIG, 0xfc01);
  530. sungem_phy_write(phy, 0x0b, 0x0004);
  531. }
  532. phy->autoneg = autoneg;
  533. return 0;
  534. }
  535. #define BCM5461_FIBER_LINK (1 << 2)
  536. #define BCM5461_MODE_MASK (3 << 1)
  537. static int bcm5461_poll_link(struct mii_phy* phy)
  538. {
  539. u32 phy_reg;
  540. int mode;
  541. /* find out in what mode we are */
  542. sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
  543. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  544. mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
  545. if ( mode == BCM54XX_COPPER)
  546. return genmii_poll_link(phy);
  547. /* find out whether we have a link */
  548. sungem_phy_write(phy, MII_NCONFIG, 0x7000);
  549. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  550. if (phy_reg & BCM5461_FIBER_LINK)
  551. return 1;
  552. else
  553. return 0;
  554. }
  555. #define BCM5461_FIBER_DUPLEX (1 << 3)
  556. static int bcm5461_read_link(struct mii_phy* phy)
  557. {
  558. u32 phy_reg;
  559. int mode;
  560. /* find out in what mode we are */
  561. sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
  562. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  563. mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
  564. if ( mode == BCM54XX_COPPER) {
  565. return bcm54xx_read_link(phy);
  566. }
  567. phy->speed = SPEED_1000;
  568. /* find out whether we are running half- or full duplex */
  569. sungem_phy_write(phy, MII_NCONFIG, 0x7000);
  570. phy_reg = sungem_phy_read(phy, MII_NCONFIG);
  571. if (phy_reg & BCM5461_FIBER_DUPLEX)
  572. phy->duplex |= DUPLEX_FULL;
  573. else
  574. phy->duplex |= DUPLEX_HALF;
  575. return 0;
  576. }
  577. static int bcm5461_enable_fiber(struct mii_phy* phy, int autoneg)
  578. {
  579. /* select fiber mode, enable 1000 base-X registers */
  580. sungem_phy_write(phy, MII_NCONFIG, 0xfc0b);
  581. if (autoneg) {
  582. /* enable fiber with no autonegotiation */
  583. sungem_phy_write(phy, MII_ADVERTISE, 0x01e0);
  584. sungem_phy_write(phy, MII_BMCR, 0x1140);
  585. } else {
  586. /* enable fiber with autonegotiation */
  587. sungem_phy_write(phy, MII_BMCR, 0x0140);
  588. }
  589. phy->autoneg = autoneg;
  590. return 0;
  591. }
  592. static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
  593. {
  594. u16 ctl, adv;
  595. phy->autoneg = 1;
  596. phy->speed = SPEED_10;
  597. phy->duplex = DUPLEX_HALF;
  598. phy->pause = 0;
  599. phy->advertising = advertise;
  600. /* Setup standard advertise */
  601. adv = sungem_phy_read(phy, MII_ADVERTISE);
  602. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  603. if (advertise & ADVERTISED_10baseT_Half)
  604. adv |= ADVERTISE_10HALF;
  605. if (advertise & ADVERTISED_10baseT_Full)
  606. adv |= ADVERTISE_10FULL;
  607. if (advertise & ADVERTISED_100baseT_Half)
  608. adv |= ADVERTISE_100HALF;
  609. if (advertise & ADVERTISED_100baseT_Full)
  610. adv |= ADVERTISE_100FULL;
  611. if (advertise & ADVERTISED_Pause)
  612. adv |= ADVERTISE_PAUSE_CAP;
  613. if (advertise & ADVERTISED_Asym_Pause)
  614. adv |= ADVERTISE_PAUSE_ASYM;
  615. sungem_phy_write(phy, MII_ADVERTISE, adv);
  616. /* Setup 1000BT advertise & enable crossover detect
  617. * XXX How do we advertise 1000BT ? Darwin source is
  618. * confusing here, they read from specific control and
  619. * write to control... Someone has specs for those
  620. * beasts ?
  621. */
  622. adv = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
  623. adv |= MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX;
  624. adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
  625. MII_1000BASETCONTROL_HALFDUPLEXCAP);
  626. if (advertise & SUPPORTED_1000baseT_Half)
  627. adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
  628. if (advertise & SUPPORTED_1000baseT_Full)
  629. adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
  630. sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
  631. /* Start/Restart aneg */
  632. ctl = sungem_phy_read(phy, MII_BMCR);
  633. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  634. sungem_phy_write(phy, MII_BMCR, ctl);
  635. return 0;
  636. }
  637. static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
  638. {
  639. u16 ctl, ctl2;
  640. phy->autoneg = 0;
  641. phy->speed = speed;
  642. phy->duplex = fd;
  643. phy->pause = 0;
  644. ctl = sungem_phy_read(phy, MII_BMCR);
  645. ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
  646. ctl |= BMCR_RESET;
  647. /* Select speed & duplex */
  648. switch(speed) {
  649. case SPEED_10:
  650. break;
  651. case SPEED_100:
  652. ctl |= BMCR_SPEED100;
  653. break;
  654. /* I'm not sure about the one below, again, Darwin source is
  655. * quite confusing and I lack chip specs
  656. */
  657. case SPEED_1000:
  658. ctl |= BMCR_SPD2;
  659. }
  660. if (fd == DUPLEX_FULL)
  661. ctl |= BMCR_FULLDPLX;
  662. /* Disable crossover. Again, the way Apple does it is strange,
  663. * though I don't assume they are wrong ;)
  664. */
  665. ctl2 = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
  666. ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX |
  667. MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX |
  668. MII_1000BASETCONTROL_FULLDUPLEXCAP |
  669. MII_1000BASETCONTROL_HALFDUPLEXCAP);
  670. if (speed == SPEED_1000)
  671. ctl2 |= (fd == DUPLEX_FULL) ?
  672. MII_1000BASETCONTROL_FULLDUPLEXCAP :
  673. MII_1000BASETCONTROL_HALFDUPLEXCAP;
  674. sungem_phy_write(phy, MII_1000BASETCONTROL, ctl2);
  675. // XXX Should we set the sungem to GII now on 1000BT ?
  676. sungem_phy_write(phy, MII_BMCR, ctl);
  677. return 0;
  678. }
  679. static int marvell_read_link(struct mii_phy *phy)
  680. {
  681. u16 status, pmask;
  682. if (phy->autoneg) {
  683. status = sungem_phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
  684. if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
  685. return -EAGAIN;
  686. if (status & MII_M1011_PHY_SPEC_STATUS_1000)
  687. phy->speed = SPEED_1000;
  688. else if (status & MII_M1011_PHY_SPEC_STATUS_100)
  689. phy->speed = SPEED_100;
  690. else
  691. phy->speed = SPEED_10;
  692. if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
  693. phy->duplex = DUPLEX_FULL;
  694. else
  695. phy->duplex = DUPLEX_HALF;
  696. pmask = MII_M1011_PHY_SPEC_STATUS_TX_PAUSE |
  697. MII_M1011_PHY_SPEC_STATUS_RX_PAUSE;
  698. phy->pause = (status & pmask) == pmask;
  699. }
  700. /* On non-aneg, we assume what we put in BMCR is the speed,
  701. * though magic-aneg shouldn't prevent this case from occurring
  702. */
  703. return 0;
  704. }
  705. #define MII_BASIC_FEATURES \
  706. (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  707. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  708. SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | \
  709. SUPPORTED_Pause)
  710. /* On gigabit capable PHYs, we advertise Pause support but not asym pause
  711. * support for now as I'm not sure it's supported and Darwin doesn't do
  712. * it neither. --BenH.
  713. */
  714. #define MII_GBIT_FEATURES \
  715. (MII_BASIC_FEATURES | \
  716. SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
  717. /* Broadcom BCM 5201 */
  718. static const struct mii_phy_ops bcm5201_phy_ops = {
  719. .init = bcm5201_init,
  720. .suspend = bcm5201_suspend,
  721. .setup_aneg = genmii_setup_aneg,
  722. .setup_forced = genmii_setup_forced,
  723. .poll_link = genmii_poll_link,
  724. .read_link = genmii_read_link,
  725. };
  726. static struct mii_phy_def bcm5201_phy_def = {
  727. .phy_id = 0x00406210,
  728. .phy_id_mask = 0xfffffff0,
  729. .name = "BCM5201",
  730. .features = MII_BASIC_FEATURES,
  731. .magic_aneg = 1,
  732. .ops = &bcm5201_phy_ops
  733. };
  734. /* Broadcom BCM 5221 */
  735. static const struct mii_phy_ops bcm5221_phy_ops = {
  736. .suspend = bcm5221_suspend,
  737. .init = bcm5221_init,
  738. .setup_aneg = genmii_setup_aneg,
  739. .setup_forced = genmii_setup_forced,
  740. .poll_link = genmii_poll_link,
  741. .read_link = genmii_read_link,
  742. };
  743. static struct mii_phy_def bcm5221_phy_def = {
  744. .phy_id = 0x004061e0,
  745. .phy_id_mask = 0xfffffff0,
  746. .name = "BCM5221",
  747. .features = MII_BASIC_FEATURES,
  748. .magic_aneg = 1,
  749. .ops = &bcm5221_phy_ops
  750. };
  751. /* Broadcom BCM 5241 */
  752. static const struct mii_phy_ops bcm5241_phy_ops = {
  753. .suspend = bcm5241_suspend,
  754. .init = bcm5241_init,
  755. .setup_aneg = genmii_setup_aneg,
  756. .setup_forced = genmii_setup_forced,
  757. .poll_link = genmii_poll_link,
  758. .read_link = genmii_read_link,
  759. };
  760. static struct mii_phy_def bcm5241_phy_def = {
  761. .phy_id = 0x0143bc30,
  762. .phy_id_mask = 0xfffffff0,
  763. .name = "BCM5241",
  764. .features = MII_BASIC_FEATURES,
  765. .magic_aneg = 1,
  766. .ops = &bcm5241_phy_ops
  767. };
  768. /* Broadcom BCM 5400 */
  769. static const struct mii_phy_ops bcm5400_phy_ops = {
  770. .init = bcm5400_init,
  771. .suspend = bcm5400_suspend,
  772. .setup_aneg = bcm54xx_setup_aneg,
  773. .setup_forced = bcm54xx_setup_forced,
  774. .poll_link = genmii_poll_link,
  775. .read_link = bcm54xx_read_link,
  776. };
  777. static struct mii_phy_def bcm5400_phy_def = {
  778. .phy_id = 0x00206040,
  779. .phy_id_mask = 0xfffffff0,
  780. .name = "BCM5400",
  781. .features = MII_GBIT_FEATURES,
  782. .magic_aneg = 1,
  783. .ops = &bcm5400_phy_ops
  784. };
  785. /* Broadcom BCM 5401 */
  786. static const struct mii_phy_ops bcm5401_phy_ops = {
  787. .init = bcm5401_init,
  788. .suspend = bcm5401_suspend,
  789. .setup_aneg = bcm54xx_setup_aneg,
  790. .setup_forced = bcm54xx_setup_forced,
  791. .poll_link = genmii_poll_link,
  792. .read_link = bcm54xx_read_link,
  793. };
  794. static struct mii_phy_def bcm5401_phy_def = {
  795. .phy_id = 0x00206050,
  796. .phy_id_mask = 0xfffffff0,
  797. .name = "BCM5401",
  798. .features = MII_GBIT_FEATURES,
  799. .magic_aneg = 1,
  800. .ops = &bcm5401_phy_ops
  801. };
  802. /* Broadcom BCM 5411 */
  803. static const struct mii_phy_ops bcm5411_phy_ops = {
  804. .init = bcm5411_init,
  805. .suspend = generic_suspend,
  806. .setup_aneg = bcm54xx_setup_aneg,
  807. .setup_forced = bcm54xx_setup_forced,
  808. .poll_link = genmii_poll_link,
  809. .read_link = bcm54xx_read_link,
  810. };
  811. static struct mii_phy_def bcm5411_phy_def = {
  812. .phy_id = 0x00206070,
  813. .phy_id_mask = 0xfffffff0,
  814. .name = "BCM5411",
  815. .features = MII_GBIT_FEATURES,
  816. .magic_aneg = 1,
  817. .ops = &bcm5411_phy_ops
  818. };
  819. /* Broadcom BCM 5421 */
  820. static const struct mii_phy_ops bcm5421_phy_ops = {
  821. .init = bcm5421_init,
  822. .suspend = generic_suspend,
  823. .setup_aneg = bcm54xx_setup_aneg,
  824. .setup_forced = bcm54xx_setup_forced,
  825. .poll_link = bcm5421_poll_link,
  826. .read_link = bcm5421_read_link,
  827. .enable_fiber = bcm5421_enable_fiber,
  828. };
  829. static struct mii_phy_def bcm5421_phy_def = {
  830. .phy_id = 0x002060e0,
  831. .phy_id_mask = 0xfffffff0,
  832. .name = "BCM5421",
  833. .features = MII_GBIT_FEATURES,
  834. .magic_aneg = 1,
  835. .ops = &bcm5421_phy_ops
  836. };
  837. /* Broadcom BCM 5421 built-in K2 */
  838. static const struct mii_phy_ops bcm5421k2_phy_ops = {
  839. .init = bcm5421_init,
  840. .suspend = generic_suspend,
  841. .setup_aneg = bcm54xx_setup_aneg,
  842. .setup_forced = bcm54xx_setup_forced,
  843. .poll_link = genmii_poll_link,
  844. .read_link = bcm54xx_read_link,
  845. };
  846. static struct mii_phy_def bcm5421k2_phy_def = {
  847. .phy_id = 0x002062e0,
  848. .phy_id_mask = 0xfffffff0,
  849. .name = "BCM5421-K2",
  850. .features = MII_GBIT_FEATURES,
  851. .magic_aneg = 1,
  852. .ops = &bcm5421k2_phy_ops
  853. };
  854. static const struct mii_phy_ops bcm5461_phy_ops = {
  855. .init = bcm5421_init,
  856. .suspend = generic_suspend,
  857. .setup_aneg = bcm54xx_setup_aneg,
  858. .setup_forced = bcm54xx_setup_forced,
  859. .poll_link = bcm5461_poll_link,
  860. .read_link = bcm5461_read_link,
  861. .enable_fiber = bcm5461_enable_fiber,
  862. };
  863. static struct mii_phy_def bcm5461_phy_def = {
  864. .phy_id = 0x002060c0,
  865. .phy_id_mask = 0xfffffff0,
  866. .name = "BCM5461",
  867. .features = MII_GBIT_FEATURES,
  868. .magic_aneg = 1,
  869. .ops = &bcm5461_phy_ops
  870. };
  871. /* Broadcom BCM 5462 built-in Vesta */
  872. static const struct mii_phy_ops bcm5462V_phy_ops = {
  873. .init = bcm5421_init,
  874. .suspend = generic_suspend,
  875. .setup_aneg = bcm54xx_setup_aneg,
  876. .setup_forced = bcm54xx_setup_forced,
  877. .poll_link = genmii_poll_link,
  878. .read_link = bcm54xx_read_link,
  879. };
  880. static struct mii_phy_def bcm5462V_phy_def = {
  881. .phy_id = 0x002060d0,
  882. .phy_id_mask = 0xfffffff0,
  883. .name = "BCM5462-Vesta",
  884. .features = MII_GBIT_FEATURES,
  885. .magic_aneg = 1,
  886. .ops = &bcm5462V_phy_ops
  887. };
  888. /* Marvell 88E1101 amd 88E1111 */
  889. static const struct mii_phy_ops marvell88e1101_phy_ops = {
  890. .suspend = generic_suspend,
  891. .setup_aneg = marvell_setup_aneg,
  892. .setup_forced = marvell_setup_forced,
  893. .poll_link = genmii_poll_link,
  894. .read_link = marvell_read_link
  895. };
  896. static const struct mii_phy_ops marvell88e1111_phy_ops = {
  897. .init = marvell88e1111_init,
  898. .suspend = generic_suspend,
  899. .setup_aneg = marvell_setup_aneg,
  900. .setup_forced = marvell_setup_forced,
  901. .poll_link = genmii_poll_link,
  902. .read_link = marvell_read_link
  903. };
  904. /* two revs in darwin for the 88e1101 ... I could use a datasheet
  905. * to get the proper names...
  906. */
  907. static struct mii_phy_def marvell88e1101v1_phy_def = {
  908. .phy_id = 0x01410c20,
  909. .phy_id_mask = 0xfffffff0,
  910. .name = "Marvell 88E1101v1",
  911. .features = MII_GBIT_FEATURES,
  912. .magic_aneg = 1,
  913. .ops = &marvell88e1101_phy_ops
  914. };
  915. static struct mii_phy_def marvell88e1101v2_phy_def = {
  916. .phy_id = 0x01410c60,
  917. .phy_id_mask = 0xfffffff0,
  918. .name = "Marvell 88E1101v2",
  919. .features = MII_GBIT_FEATURES,
  920. .magic_aneg = 1,
  921. .ops = &marvell88e1101_phy_ops
  922. };
  923. static struct mii_phy_def marvell88e1111_phy_def = {
  924. .phy_id = 0x01410cc0,
  925. .phy_id_mask = 0xfffffff0,
  926. .name = "Marvell 88E1111",
  927. .features = MII_GBIT_FEATURES,
  928. .magic_aneg = 1,
  929. .ops = &marvell88e1111_phy_ops
  930. };
  931. /* Generic implementation for most 10/100 PHYs */
  932. static const struct mii_phy_ops generic_phy_ops = {
  933. .setup_aneg = genmii_setup_aneg,
  934. .setup_forced = genmii_setup_forced,
  935. .poll_link = genmii_poll_link,
  936. .read_link = genmii_read_link
  937. };
  938. static struct mii_phy_def genmii_phy_def = {
  939. .phy_id = 0x00000000,
  940. .phy_id_mask = 0x00000000,
  941. .name = "Generic MII",
  942. .features = MII_BASIC_FEATURES,
  943. .magic_aneg = 0,
  944. .ops = &generic_phy_ops
  945. };
  946. static struct mii_phy_def* mii_phy_table[] = {
  947. &bcm5201_phy_def,
  948. &bcm5221_phy_def,
  949. &bcm5241_phy_def,
  950. &bcm5400_phy_def,
  951. &bcm5401_phy_def,
  952. &bcm5411_phy_def,
  953. &bcm5421_phy_def,
  954. &bcm5421k2_phy_def,
  955. &bcm5461_phy_def,
  956. &bcm5462V_phy_def,
  957. &marvell88e1101v1_phy_def,
  958. &marvell88e1101v2_phy_def,
  959. &marvell88e1111_phy_def,
  960. &genmii_phy_def,
  961. NULL
  962. };
  963. int sungem_phy_probe(struct mii_phy *phy, int mii_id)
  964. {
  965. int rc;
  966. u32 id;
  967. struct mii_phy_def* def;
  968. int i;
  969. /* We do not reset the mii_phy structure as the driver
  970. * may re-probe the PHY regulary
  971. */
  972. phy->mii_id = mii_id;
  973. /* Take PHY out of isloate mode and reset it. */
  974. rc = reset_one_mii_phy(phy, mii_id);
  975. if (rc)
  976. goto fail;
  977. /* Read ID and find matching entry */
  978. id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
  979. printk(KERN_DEBUG KBUILD_MODNAME ": " "PHY ID: %x, addr: %x\n",
  980. id, mii_id);
  981. for (i=0; (def = mii_phy_table[i]) != NULL; i++)
  982. if ((id & def->phy_id_mask) == def->phy_id)
  983. break;
  984. /* Should never be NULL (we have a generic entry), but... */
  985. if (def == NULL)
  986. goto fail;
  987. phy->def = def;
  988. return 0;
  989. fail:
  990. phy->speed = 0;
  991. phy->duplex = 0;
  992. phy->pause = 0;
  993. phy->advertising = 0;
  994. return -ENODEV;
  995. }
  996. EXPORT_SYMBOL(sungem_phy_probe);
  997. MODULE_LICENSE("GPL");