national.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/phy/national.c
  4. *
  5. * Driver for National Semiconductor PHYs
  6. *
  7. * Author: Stuart Menefy <[email protected]>
  8. * Maintainer: Giuseppe Cavallaro <[email protected]>
  9. *
  10. * Copyright (c) 2008 STMicroelectronics Limited
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/phy.h>
  18. #include <linux/netdevice.h>
  19. /* DP83865 phy identifier values */
  20. #define DP83865_PHY_ID 0x20005c7a
  21. #define DP83865_INT_STATUS 0x14
  22. #define DP83865_INT_MASK 0x15
  23. #define DP83865_INT_CLEAR 0x17
  24. #define DP83865_INT_REMOTE_FAULT 0x0008
  25. #define DP83865_INT_ANE_COMPLETED 0x0010
  26. #define DP83865_INT_LINK_CHANGE 0xe000
  27. #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
  28. DP83865_INT_ANE_COMPLETED | \
  29. DP83865_INT_LINK_CHANGE)
  30. /* Advanced proprietary configuration */
  31. #define NS_EXP_MEM_CTL 0x16
  32. #define NS_EXP_MEM_DATA 0x1d
  33. #define NS_EXP_MEM_ADD 0x1e
  34. #define LED_CTRL_REG 0x13
  35. #define AN_FALLBACK_AN 0x0001
  36. #define AN_FALLBACK_CRC 0x0002
  37. #define AN_FALLBACK_IE 0x0004
  38. #define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
  39. enum hdx_loopback {
  40. hdx_loopback_on = 0,
  41. hdx_loopback_off = 1,
  42. };
  43. static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
  44. {
  45. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  46. return phy_read(phydev, NS_EXP_MEM_DATA);
  47. }
  48. static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
  49. {
  50. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  51. phy_write(phydev, NS_EXP_MEM_DATA, data);
  52. }
  53. static int ns_ack_interrupt(struct phy_device *phydev)
  54. {
  55. int ret = phy_read(phydev, DP83865_INT_STATUS);
  56. if (ret < 0)
  57. return ret;
  58. /* Clear the interrupt status bit by writing a “1”
  59. * to the corresponding bit in INT_CLEAR (2:0 are reserved)
  60. */
  61. ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
  62. return ret;
  63. }
  64. static irqreturn_t ns_handle_interrupt(struct phy_device *phydev)
  65. {
  66. int irq_status;
  67. irq_status = phy_read(phydev, DP83865_INT_STATUS);
  68. if (irq_status < 0) {
  69. phy_error(phydev);
  70. return IRQ_NONE;
  71. }
  72. if (!(irq_status & DP83865_INT_MASK_DEFAULT))
  73. return IRQ_NONE;
  74. /* clear the interrupt */
  75. phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7);
  76. phy_trigger_machine(phydev);
  77. return IRQ_HANDLED;
  78. }
  79. static int ns_config_intr(struct phy_device *phydev)
  80. {
  81. int err;
  82. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  83. err = ns_ack_interrupt(phydev);
  84. if (err)
  85. return err;
  86. err = phy_write(phydev, DP83865_INT_MASK,
  87. DP83865_INT_MASK_DEFAULT);
  88. } else {
  89. err = phy_write(phydev, DP83865_INT_MASK, 0);
  90. if (err)
  91. return err;
  92. err = ns_ack_interrupt(phydev);
  93. }
  94. return err;
  95. }
  96. static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
  97. {
  98. int bmcr = phy_read(phydev, MII_BMCR);
  99. phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
  100. /* Enable 8 bit expended memory read/write (no auto increment) */
  101. phy_write(phydev, NS_EXP_MEM_CTL, 0);
  102. phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
  103. phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
  104. phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
  105. phy_write(phydev, LED_CTRL_REG, mode);
  106. }
  107. static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
  108. {
  109. u16 lb_dis = BIT(1);
  110. if (disable)
  111. ns_exp_write(phydev, 0x1c0,
  112. ns_exp_read(phydev, 0x1c0) | lb_dis);
  113. else
  114. ns_exp_write(phydev, 0x1c0,
  115. ns_exp_read(phydev, 0x1c0) & ~lb_dis);
  116. pr_debug("10BASE-T HDX loopback %s\n",
  117. (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on");
  118. }
  119. static int ns_config_init(struct phy_device *phydev)
  120. {
  121. ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
  122. /* In the latest MAC or switches design, the 10 Mbps loopback
  123. * is desired to be turned off.
  124. */
  125. ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
  126. return ns_ack_interrupt(phydev);
  127. }
  128. static struct phy_driver dp83865_driver[] = { {
  129. .phy_id = DP83865_PHY_ID,
  130. .phy_id_mask = 0xfffffff0,
  131. .name = "NatSemi DP83865",
  132. /* PHY_GBIT_FEATURES */
  133. .config_init = ns_config_init,
  134. .config_intr = ns_config_intr,
  135. .handle_interrupt = ns_handle_interrupt,
  136. } };
  137. module_phy_driver(dp83865_driver);
  138. MODULE_DESCRIPTION("NatSemi PHY driver");
  139. MODULE_AUTHOR("Stuart Menefy");
  140. MODULE_LICENSE("GPL");
  141. static struct mdio_device_id __maybe_unused ns_tbl[] = {
  142. { DP83865_PHY_ID, 0xfffffff0 },
  143. { }
  144. };
  145. MODULE_DEVICE_TABLE(mdio, ns_tbl);