mediatek-ge.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <linux/bitfield.h>
  3. #include <linux/module.h>
  4. #include <linux/phy.h>
  5. #define MTK_EXT_PAGE_ACCESS 0x1f
  6. #define MTK_PHY_PAGE_STANDARD 0x0000
  7. #define MTK_PHY_PAGE_EXTENDED 0x0001
  8. #define MTK_PHY_PAGE_EXTENDED_2 0x0002
  9. #define MTK_PHY_PAGE_EXTENDED_3 0x0003
  10. #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
  11. #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
  12. static int mtk_gephy_read_page(struct phy_device *phydev)
  13. {
  14. return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
  15. }
  16. static int mtk_gephy_write_page(struct phy_device *phydev, int page)
  17. {
  18. return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
  19. }
  20. static void mtk_gephy_config_init(struct phy_device *phydev)
  21. {
  22. /* Disable EEE */
  23. phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
  24. /* Enable HW auto downshift */
  25. phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
  26. /* Increase SlvDPSready time */
  27. phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
  28. __phy_write(phydev, 0x10, 0xafae);
  29. __phy_write(phydev, 0x12, 0x2f);
  30. __phy_write(phydev, 0x10, 0x8fae);
  31. phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
  32. /* Adjust 100_mse_threshold */
  33. phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
  34. /* Disable mcc */
  35. phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
  36. }
  37. static int mt7530_phy_config_init(struct phy_device *phydev)
  38. {
  39. mtk_gephy_config_init(phydev);
  40. /* Increase post_update_timer */
  41. phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
  42. return 0;
  43. }
  44. static int mt7531_phy_config_init(struct phy_device *phydev)
  45. {
  46. mtk_gephy_config_init(phydev);
  47. /* PHY link down power saving enable */
  48. phy_set_bits(phydev, 0x17, BIT(4));
  49. phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
  50. /* Set TX Pair delay selection */
  51. phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
  52. phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
  53. return 0;
  54. }
  55. static struct phy_driver mtk_gephy_driver[] = {
  56. {
  57. PHY_ID_MATCH_EXACT(0x03a29412),
  58. .name = "MediaTek MT7530 PHY",
  59. .config_init = mt7530_phy_config_init,
  60. /* Interrupts are handled by the switch, not the PHY
  61. * itself.
  62. */
  63. .config_intr = genphy_no_config_intr,
  64. .handle_interrupt = genphy_handle_interrupt_no_ack,
  65. .suspend = genphy_suspend,
  66. .resume = genphy_resume,
  67. .read_page = mtk_gephy_read_page,
  68. .write_page = mtk_gephy_write_page,
  69. },
  70. {
  71. PHY_ID_MATCH_EXACT(0x03a29441),
  72. .name = "MediaTek MT7531 PHY",
  73. .config_init = mt7531_phy_config_init,
  74. /* Interrupts are handled by the switch, not the PHY
  75. * itself.
  76. */
  77. .config_intr = genphy_no_config_intr,
  78. .handle_interrupt = genphy_handle_interrupt_no_ack,
  79. .suspend = genphy_suspend,
  80. .resume = genphy_resume,
  81. .read_page = mtk_gephy_read_page,
  82. .write_page = mtk_gephy_write_page,
  83. },
  84. };
  85. module_phy_driver(mtk_gephy_driver);
  86. static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
  87. { PHY_ID_MATCH_VENDOR(0x03a29400) },
  88. { }
  89. };
  90. MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
  91. MODULE_AUTHOR("DENG, Qingfang <[email protected]>");
  92. MODULE_LICENSE("GPL");
  93. MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);