lxt.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/phy/lxt.c
  4. *
  5. * Driver for Intel LXT PHYs
  6. *
  7. * Author: Andy Fleming
  8. *
  9. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/unistd.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/skbuff.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/mm.h>
  23. #include <linux/module.h>
  24. #include <linux/mii.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/phy.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. #include <linux/uaccess.h>
  30. /* The Level one LXT970 is used by many boards */
  31. #define MII_LXT970_IER 17 /* Interrupt Enable Register */
  32. #define MII_LXT970_IER_IEN 0x0002
  33. #define MII_LXT970_ISR 18 /* Interrupt Status Register */
  34. #define MII_LXT970_IRS_MINT BIT(15)
  35. #define MII_LXT970_CONFIG 19 /* Configuration Register */
  36. /* ------------------------------------------------------------------------- */
  37. /* The Level one LXT971 is used on some of my custom boards */
  38. /* register definitions for the 971 */
  39. #define MII_LXT971_IER 18 /* Interrupt Enable Register */
  40. #define MII_LXT971_IER_IEN 0x00f2
  41. #define MII_LXT971_ISR 19 /* Interrupt Status Register */
  42. #define MII_LXT971_ISR_MASK 0x00f0
  43. /* register definitions for the 973 */
  44. #define MII_LXT973_PCR 16 /* Port Configuration Register */
  45. #define PCR_FIBER_SELECT 1
  46. MODULE_DESCRIPTION("Intel LXT PHY driver");
  47. MODULE_AUTHOR("Andy Fleming");
  48. MODULE_LICENSE("GPL");
  49. static int lxt970_ack_interrupt(struct phy_device *phydev)
  50. {
  51. int err;
  52. err = phy_read(phydev, MII_BMSR);
  53. if (err < 0)
  54. return err;
  55. err = phy_read(phydev, MII_LXT970_ISR);
  56. if (err < 0)
  57. return err;
  58. return 0;
  59. }
  60. static int lxt970_config_intr(struct phy_device *phydev)
  61. {
  62. int err;
  63. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  64. err = lxt970_ack_interrupt(phydev);
  65. if (err)
  66. return err;
  67. err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
  68. } else {
  69. err = phy_write(phydev, MII_LXT970_IER, 0);
  70. if (err)
  71. return err;
  72. err = lxt970_ack_interrupt(phydev);
  73. }
  74. return err;
  75. }
  76. static irqreturn_t lxt970_handle_interrupt(struct phy_device *phydev)
  77. {
  78. int irq_status;
  79. /* The interrupt status register is cleared by reading BMSR
  80. * followed by MII_LXT970_ISR
  81. */
  82. irq_status = phy_read(phydev, MII_BMSR);
  83. if (irq_status < 0) {
  84. phy_error(phydev);
  85. return IRQ_NONE;
  86. }
  87. irq_status = phy_read(phydev, MII_LXT970_ISR);
  88. if (irq_status < 0) {
  89. phy_error(phydev);
  90. return IRQ_NONE;
  91. }
  92. if (!(irq_status & MII_LXT970_IRS_MINT))
  93. return IRQ_NONE;
  94. phy_trigger_machine(phydev);
  95. return IRQ_HANDLED;
  96. }
  97. static int lxt970_config_init(struct phy_device *phydev)
  98. {
  99. return phy_write(phydev, MII_LXT970_CONFIG, 0);
  100. }
  101. static int lxt971_ack_interrupt(struct phy_device *phydev)
  102. {
  103. int err = phy_read(phydev, MII_LXT971_ISR);
  104. if (err < 0)
  105. return err;
  106. return 0;
  107. }
  108. static int lxt971_config_intr(struct phy_device *phydev)
  109. {
  110. int err;
  111. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  112. err = lxt971_ack_interrupt(phydev);
  113. if (err)
  114. return err;
  115. err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
  116. } else {
  117. err = phy_write(phydev, MII_LXT971_IER, 0);
  118. if (err)
  119. return err;
  120. err = lxt971_ack_interrupt(phydev);
  121. }
  122. return err;
  123. }
  124. static irqreturn_t lxt971_handle_interrupt(struct phy_device *phydev)
  125. {
  126. int irq_status;
  127. irq_status = phy_read(phydev, MII_LXT971_ISR);
  128. if (irq_status < 0) {
  129. phy_error(phydev);
  130. return IRQ_NONE;
  131. }
  132. if (!(irq_status & MII_LXT971_ISR_MASK))
  133. return IRQ_NONE;
  134. phy_trigger_machine(phydev);
  135. return IRQ_HANDLED;
  136. }
  137. /*
  138. * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
  139. * of the previous even register when you read a odd register regularly
  140. */
  141. static int lxt973a2_update_link(struct phy_device *phydev)
  142. {
  143. int status;
  144. int control;
  145. int retry = 8; /* we try 8 times */
  146. /* Do a fake read */
  147. status = phy_read(phydev, MII_BMSR);
  148. if (status < 0)
  149. return status;
  150. control = phy_read(phydev, MII_BMCR);
  151. if (control < 0)
  152. return control;
  153. do {
  154. /* Read link and autonegotiation status */
  155. status = phy_read(phydev, MII_BMSR);
  156. } while (status >= 0 && retry-- && status == control);
  157. if (status < 0)
  158. return status;
  159. if ((status & BMSR_LSTATUS) == 0)
  160. phydev->link = 0;
  161. else
  162. phydev->link = 1;
  163. return 0;
  164. }
  165. static int lxt973a2_read_status(struct phy_device *phydev)
  166. {
  167. int adv;
  168. int err;
  169. int lpa;
  170. /* Update the link, but return if there was an error */
  171. err = lxt973a2_update_link(phydev);
  172. if (err)
  173. return err;
  174. if (AUTONEG_ENABLE == phydev->autoneg) {
  175. int retry = 1;
  176. adv = phy_read(phydev, MII_ADVERTISE);
  177. if (adv < 0)
  178. return adv;
  179. do {
  180. lpa = phy_read(phydev, MII_LPA);
  181. if (lpa < 0)
  182. return lpa;
  183. /* If both registers are equal, it is suspect but not
  184. * impossible, hence a new try
  185. */
  186. } while (lpa == adv && retry--);
  187. mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa);
  188. lpa &= adv;
  189. phydev->speed = SPEED_10;
  190. phydev->duplex = DUPLEX_HALF;
  191. phydev->pause = phydev->asym_pause = 0;
  192. if (lpa & (LPA_100FULL | LPA_100HALF)) {
  193. phydev->speed = SPEED_100;
  194. if (lpa & LPA_100FULL)
  195. phydev->duplex = DUPLEX_FULL;
  196. } else {
  197. if (lpa & LPA_10FULL)
  198. phydev->duplex = DUPLEX_FULL;
  199. }
  200. phy_resolve_aneg_pause(phydev);
  201. } else {
  202. err = genphy_read_status_fixed(phydev);
  203. if (err < 0)
  204. return err;
  205. phydev->pause = phydev->asym_pause = 0;
  206. linkmode_zero(phydev->lp_advertising);
  207. }
  208. return 0;
  209. }
  210. static int lxt973_probe(struct phy_device *phydev)
  211. {
  212. int val = phy_read(phydev, MII_LXT973_PCR);
  213. if (val & PCR_FIBER_SELECT) {
  214. /*
  215. * If fiber is selected, then the only correct setting
  216. * is 100Mbps, full duplex, and auto negotiation off.
  217. */
  218. val = phy_read(phydev, MII_BMCR);
  219. val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
  220. val &= ~BMCR_ANENABLE;
  221. phy_write(phydev, MII_BMCR, val);
  222. /* Remember that the port is in fiber mode. */
  223. phydev->priv = lxt973_probe;
  224. phydev->port = PORT_FIBRE;
  225. } else {
  226. phydev->priv = NULL;
  227. }
  228. return 0;
  229. }
  230. static int lxt973_config_aneg(struct phy_device *phydev)
  231. {
  232. /* Do nothing if port is in fiber mode. */
  233. return phydev->priv ? 0 : genphy_config_aneg(phydev);
  234. }
  235. static struct phy_driver lxt97x_driver[] = {
  236. {
  237. .phy_id = 0x78100000,
  238. .name = "LXT970",
  239. .phy_id_mask = 0xfffffff0,
  240. /* PHY_BASIC_FEATURES */
  241. .config_init = lxt970_config_init,
  242. .config_intr = lxt970_config_intr,
  243. .handle_interrupt = lxt970_handle_interrupt,
  244. }, {
  245. .phy_id = 0x001378e0,
  246. .name = "LXT971",
  247. .phy_id_mask = 0xfffffff0,
  248. /* PHY_BASIC_FEATURES */
  249. .config_intr = lxt971_config_intr,
  250. .handle_interrupt = lxt971_handle_interrupt,
  251. .suspend = genphy_suspend,
  252. .resume = genphy_resume,
  253. }, {
  254. .phy_id = 0x00137a10,
  255. .name = "LXT973-A2",
  256. .phy_id_mask = 0xffffffff,
  257. /* PHY_BASIC_FEATURES */
  258. .flags = 0,
  259. .probe = lxt973_probe,
  260. .config_aneg = lxt973_config_aneg,
  261. .read_status = lxt973a2_read_status,
  262. .suspend = genphy_suspend,
  263. .resume = genphy_resume,
  264. }, {
  265. .phy_id = 0x00137a10,
  266. .name = "LXT973",
  267. .phy_id_mask = 0xfffffff0,
  268. /* PHY_BASIC_FEATURES */
  269. .flags = 0,
  270. .probe = lxt973_probe,
  271. .config_aneg = lxt973_config_aneg,
  272. .suspend = genphy_suspend,
  273. .resume = genphy_resume,
  274. } };
  275. module_phy_driver(lxt97x_driver);
  276. static struct mdio_device_id __maybe_unused lxt_tbl[] = {
  277. { 0x78100000, 0xfffffff0 },
  278. { 0x001378e0, 0xfffffff0 },
  279. { 0x00137a10, 0xfffffff0 },
  280. { }
  281. };
  282. MODULE_DEVICE_TABLE(mdio, lxt_tbl);