davicom.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/phy/davicom.c
  4. *
  5. * Driver for Davicom PHYs
  6. *
  7. * Author: Andy Fleming
  8. *
  9. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/unistd.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/skbuff.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/mm.h>
  23. #include <linux/module.h>
  24. #include <linux/mii.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/phy.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. #include <linux/uaccess.h>
  30. #define MII_DM9161_SCR 0x10
  31. #define MII_DM9161_SCR_INIT 0x0610
  32. #define MII_DM9161_SCR_RMII 0x0100
  33. /* DM9161 Interrupt Register */
  34. #define MII_DM9161_INTR 0x15
  35. #define MII_DM9161_INTR_PEND 0x8000
  36. #define MII_DM9161_INTR_DPLX_MASK 0x0800
  37. #define MII_DM9161_INTR_SPD_MASK 0x0400
  38. #define MII_DM9161_INTR_LINK_MASK 0x0200
  39. #define MII_DM9161_INTR_MASK 0x0100
  40. #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
  41. #define MII_DM9161_INTR_SPD_CHANGE 0x0008
  42. #define MII_DM9161_INTR_LINK_CHANGE 0x0004
  43. #define MII_DM9161_INTR_INIT 0x0000
  44. #define MII_DM9161_INTR_STOP \
  45. (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
  46. MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
  47. #define MII_DM9161_INTR_CHANGE \
  48. (MII_DM9161_INTR_DPLX_CHANGE | \
  49. MII_DM9161_INTR_SPD_CHANGE | \
  50. MII_DM9161_INTR_LINK_CHANGE)
  51. /* DM9161 10BT Configuration/Status */
  52. #define MII_DM9161_10BTCSR 0x12
  53. #define MII_DM9161_10BTCSR_INIT 0x7800
  54. MODULE_DESCRIPTION("Davicom PHY driver");
  55. MODULE_AUTHOR("Andy Fleming");
  56. MODULE_LICENSE("GPL");
  57. static int dm9161_ack_interrupt(struct phy_device *phydev)
  58. {
  59. int err = phy_read(phydev, MII_DM9161_INTR);
  60. return (err < 0) ? err : 0;
  61. }
  62. #define DM9161_DELAY 1
  63. static int dm9161_config_intr(struct phy_device *phydev)
  64. {
  65. int temp, err;
  66. temp = phy_read(phydev, MII_DM9161_INTR);
  67. if (temp < 0)
  68. return temp;
  69. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  70. err = dm9161_ack_interrupt(phydev);
  71. if (err)
  72. return err;
  73. temp &= ~(MII_DM9161_INTR_STOP);
  74. err = phy_write(phydev, MII_DM9161_INTR, temp);
  75. } else {
  76. temp |= MII_DM9161_INTR_STOP;
  77. err = phy_write(phydev, MII_DM9161_INTR, temp);
  78. if (err)
  79. return err;
  80. err = dm9161_ack_interrupt(phydev);
  81. }
  82. return err;
  83. }
  84. static irqreturn_t dm9161_handle_interrupt(struct phy_device *phydev)
  85. {
  86. int irq_status;
  87. irq_status = phy_read(phydev, MII_DM9161_INTR);
  88. if (irq_status < 0) {
  89. phy_error(phydev);
  90. return IRQ_NONE;
  91. }
  92. if (!(irq_status & MII_DM9161_INTR_CHANGE))
  93. return IRQ_NONE;
  94. phy_trigger_machine(phydev);
  95. return IRQ_HANDLED;
  96. }
  97. static int dm9161_config_aneg(struct phy_device *phydev)
  98. {
  99. int err;
  100. /* Isolate the PHY */
  101. err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
  102. if (err < 0)
  103. return err;
  104. /* Configure the new settings */
  105. err = genphy_config_aneg(phydev);
  106. if (err < 0)
  107. return err;
  108. return 0;
  109. }
  110. static int dm9161_config_init(struct phy_device *phydev)
  111. {
  112. int err, temp;
  113. /* Isolate the PHY */
  114. err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
  115. if (err < 0)
  116. return err;
  117. switch (phydev->interface) {
  118. case PHY_INTERFACE_MODE_MII:
  119. temp = MII_DM9161_SCR_INIT;
  120. break;
  121. case PHY_INTERFACE_MODE_RMII:
  122. temp = MII_DM9161_SCR_INIT | MII_DM9161_SCR_RMII;
  123. break;
  124. default:
  125. return -EINVAL;
  126. }
  127. /* Do not bypass the scrambler/descrambler */
  128. err = phy_write(phydev, MII_DM9161_SCR, temp);
  129. if (err < 0)
  130. return err;
  131. /* Clear 10BTCSR to default */
  132. err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
  133. if (err < 0)
  134. return err;
  135. /* Reconnect the PHY, and enable Autonegotiation */
  136. return phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
  137. }
  138. static struct phy_driver dm91xx_driver[] = {
  139. {
  140. .phy_id = 0x0181b880,
  141. .name = "Davicom DM9161E",
  142. .phy_id_mask = 0x0ffffff0,
  143. /* PHY_BASIC_FEATURES */
  144. .config_init = dm9161_config_init,
  145. .config_aneg = dm9161_config_aneg,
  146. .config_intr = dm9161_config_intr,
  147. .handle_interrupt = dm9161_handle_interrupt,
  148. }, {
  149. .phy_id = 0x0181b8b0,
  150. .name = "Davicom DM9161B/C",
  151. .phy_id_mask = 0x0ffffff0,
  152. /* PHY_BASIC_FEATURES */
  153. .config_init = dm9161_config_init,
  154. .config_aneg = dm9161_config_aneg,
  155. .config_intr = dm9161_config_intr,
  156. .handle_interrupt = dm9161_handle_interrupt,
  157. }, {
  158. .phy_id = 0x0181b8a0,
  159. .name = "Davicom DM9161A",
  160. .phy_id_mask = 0x0ffffff0,
  161. /* PHY_BASIC_FEATURES */
  162. .config_init = dm9161_config_init,
  163. .config_aneg = dm9161_config_aneg,
  164. .config_intr = dm9161_config_intr,
  165. .handle_interrupt = dm9161_handle_interrupt,
  166. }, {
  167. .phy_id = 0x00181b80,
  168. .name = "Davicom DM9131",
  169. .phy_id_mask = 0x0ffffff0,
  170. /* PHY_BASIC_FEATURES */
  171. .config_intr = dm9161_config_intr,
  172. .handle_interrupt = dm9161_handle_interrupt,
  173. } };
  174. module_phy_driver(dm91xx_driver);
  175. static struct mdio_device_id __maybe_unused davicom_tbl[] = {
  176. { 0x0181b880, 0x0ffffff0 },
  177. { 0x0181b8b0, 0x0ffffff0 },
  178. { 0x0181b8a0, 0x0ffffff0 },
  179. { 0x00181b80, 0x0ffffff0 },
  180. { }
  181. };
  182. MODULE_DEVICE_TABLE(mdio, davicom_tbl);