ipa_data-v4.5.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (C) 2021 Linaro Ltd. */
  3. #include <linux/log2.h>
  4. #include "../gsi.h"
  5. #include "../ipa_data.h"
  6. #include "../ipa_endpoint.h"
  7. #include "../ipa_mem.h"
  8. /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */
  9. enum ipa_resource_type {
  10. /* Source resource types; first must have value 0 */
  11. IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
  12. IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
  13. IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
  14. IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
  15. IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
  16. /* Destination resource types; first must have value 0 */
  17. IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
  18. IPA_RESOURCE_TYPE_DST_DPS_DMARS,
  19. };
  20. /* Resource groups used for an SoC having IPA v4.5 */
  21. enum ipa_rsrc_group_id {
  22. /* Source resource group identifiers */
  23. IPA_RSRC_GROUP_SRC_UNUSED_0 = 0,
  24. IPA_RSRC_GROUP_SRC_UL_DL,
  25. IPA_RSRC_GROUP_SRC_UNUSED_2,
  26. IPA_RSRC_GROUP_SRC_UNUSED_3,
  27. IPA_RSRC_GROUP_SRC_UC_RX_Q,
  28. IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
  29. /* Destination resource group identifiers */
  30. IPA_RSRC_GROUP_DST_UNUSED_0 = 0,
  31. IPA_RSRC_GROUP_DST_UL_DL_DPL,
  32. IPA_RSRC_GROUP_DST_UNUSED_2,
  33. IPA_RSRC_GROUP_DST_UNUSED_3,
  34. IPA_RSRC_GROUP_DST_UC,
  35. IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
  36. };
  37. /* QSB configuration data for an SoC having IPA v4.5 */
  38. static const struct ipa_qsb_data ipa_qsb_data[] = {
  39. [IPA_QSB_MASTER_DDR] = {
  40. .max_writes = 8,
  41. .max_reads = 0, /* no limit (hardware max) */
  42. .max_reads_beats = 120,
  43. },
  44. [IPA_QSB_MASTER_PCIE] = {
  45. .max_writes = 8,
  46. .max_reads = 12,
  47. /* no outstanding read byte (beat) limit */
  48. },
  49. };
  50. /* Endpoint configuration data for an SoC having IPA v4.5 */
  51. static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
  52. [IPA_ENDPOINT_AP_COMMAND_TX] = {
  53. .ee_id = GSI_EE_AP,
  54. .channel_id = 9,
  55. .endpoint_id = 7,
  56. .toward_ipa = true,
  57. .channel = {
  58. .tre_count = 256,
  59. .event_count = 256,
  60. .tlv_count = 20,
  61. },
  62. .endpoint = {
  63. .config = {
  64. .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
  65. .dma_mode = true,
  66. .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
  67. .tx = {
  68. .seq_type = IPA_SEQ_DMA,
  69. },
  70. },
  71. },
  72. },
  73. [IPA_ENDPOINT_AP_LAN_RX] = {
  74. .ee_id = GSI_EE_AP,
  75. .channel_id = 10,
  76. .endpoint_id = 16,
  77. .toward_ipa = false,
  78. .channel = {
  79. .tre_count = 256,
  80. .event_count = 256,
  81. .tlv_count = 9,
  82. },
  83. .endpoint = {
  84. .config = {
  85. .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
  86. .aggregation = true,
  87. .status_enable = true,
  88. .rx = {
  89. .buffer_size = 8192,
  90. .pad_align = ilog2(sizeof(u32)),
  91. .aggr_time_limit = 500,
  92. },
  93. },
  94. },
  95. },
  96. [IPA_ENDPOINT_AP_MODEM_TX] = {
  97. .ee_id = GSI_EE_AP,
  98. .channel_id = 7,
  99. .endpoint_id = 2,
  100. .toward_ipa = true,
  101. .channel = {
  102. .tre_count = 512,
  103. .event_count = 512,
  104. .tlv_count = 16,
  105. },
  106. .endpoint = {
  107. .filter_support = true,
  108. .config = {
  109. .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
  110. .checksum = true,
  111. .qmap = true,
  112. .status_enable = true,
  113. .tx = {
  114. .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
  115. .status_endpoint =
  116. IPA_ENDPOINT_MODEM_AP_RX,
  117. },
  118. },
  119. },
  120. },
  121. [IPA_ENDPOINT_AP_MODEM_RX] = {
  122. .ee_id = GSI_EE_AP,
  123. .channel_id = 1,
  124. .endpoint_id = 14,
  125. .toward_ipa = false,
  126. .channel = {
  127. .tre_count = 256,
  128. .event_count = 256,
  129. .tlv_count = 9,
  130. },
  131. .endpoint = {
  132. .config = {
  133. .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
  134. .checksum = true,
  135. .qmap = true,
  136. .aggregation = true,
  137. .rx = {
  138. .buffer_size = 8192,
  139. .aggr_time_limit = 500,
  140. .aggr_close_eof = true,
  141. },
  142. },
  143. },
  144. },
  145. [IPA_ENDPOINT_MODEM_AP_TX] = {
  146. .ee_id = GSI_EE_MODEM,
  147. .channel_id = 0,
  148. .endpoint_id = 5,
  149. .toward_ipa = true,
  150. .endpoint = {
  151. .filter_support = true,
  152. },
  153. },
  154. [IPA_ENDPOINT_MODEM_AP_RX] = {
  155. .ee_id = GSI_EE_MODEM,
  156. .channel_id = 7,
  157. .endpoint_id = 21,
  158. .toward_ipa = false,
  159. },
  160. [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
  161. .ee_id = GSI_EE_MODEM,
  162. .channel_id = 2,
  163. .endpoint_id = 8,
  164. .toward_ipa = true,
  165. .endpoint = {
  166. .filter_support = true,
  167. },
  168. },
  169. };
  170. /* Source resource configuration data for an SoC having IPA v4.5 */
  171. static const struct ipa_resource ipa_resource_src[] = {
  172. [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
  173. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  174. .min = 1, .max = 11,
  175. },
  176. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  177. .min = 1, .max = 63,
  178. },
  179. },
  180. [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
  181. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  182. .min = 14, .max = 14,
  183. },
  184. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  185. .min = 3, .max = 3,
  186. },
  187. },
  188. [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
  189. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  190. .min = 18, .max = 18,
  191. },
  192. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  193. .min = 8, .max = 8,
  194. },
  195. },
  196. [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
  197. .limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {
  198. .min = 0, .max = 63,
  199. },
  200. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  201. .min = 0, .max = 63,
  202. },
  203. .limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {
  204. .min = 0, .max = 63,
  205. },
  206. .limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {
  207. .min = 0, .max = 63,
  208. },
  209. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  210. .min = 0, .max = 63,
  211. },
  212. },
  213. [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
  214. .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
  215. .min = 24, .max = 24,
  216. },
  217. .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
  218. .min = 8, .max = 8,
  219. },
  220. },
  221. };
  222. /* Destination resource configuration data for an SoC having IPA v4.5 */
  223. static const struct ipa_resource ipa_resource_dst[] = {
  224. [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
  225. .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
  226. .min = 16, .max = 16,
  227. },
  228. .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
  229. .min = 2, .max = 2,
  230. },
  231. .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
  232. .min = 2, .max = 2,
  233. },
  234. },
  235. [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
  236. .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
  237. .min = 2, .max = 63,
  238. },
  239. .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
  240. .min = 1, .max = 2,
  241. },
  242. .limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
  243. .min = 1, .max = 2,
  244. },
  245. .limits[IPA_RSRC_GROUP_DST_UC] = {
  246. .min = 0, .max = 2,
  247. },
  248. },
  249. };
  250. /* Resource configuration data for an SoC having IPA v4.5 */
  251. static const struct ipa_resource_data ipa_resource_data = {
  252. .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
  253. .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
  254. .resource_src_count = ARRAY_SIZE(ipa_resource_src),
  255. .resource_src = ipa_resource_src,
  256. .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
  257. .resource_dst = ipa_resource_dst,
  258. };
  259. /* IPA-resident memory region data for an SoC having IPA v4.5 */
  260. static const struct ipa_mem ipa_mem_local_data[] = {
  261. {
  262. .id = IPA_MEM_UC_SHARED,
  263. .offset = 0x0000,
  264. .size = 0x0080,
  265. .canary_count = 0,
  266. },
  267. {
  268. .id = IPA_MEM_UC_INFO,
  269. .offset = 0x0080,
  270. .size = 0x0200,
  271. .canary_count = 0,
  272. },
  273. {
  274. .id = IPA_MEM_V4_FILTER_HASHED,
  275. .offset = 0x0288,
  276. .size = 0x0078,
  277. .canary_count = 2,
  278. },
  279. {
  280. .id = IPA_MEM_V4_FILTER,
  281. .offset = 0x0308,
  282. .size = 0x0078,
  283. .canary_count = 2,
  284. },
  285. {
  286. .id = IPA_MEM_V6_FILTER_HASHED,
  287. .offset = 0x0388,
  288. .size = 0x0078,
  289. .canary_count = 2,
  290. },
  291. {
  292. .id = IPA_MEM_V6_FILTER,
  293. .offset = 0x0408,
  294. .size = 0x0078,
  295. .canary_count = 2,
  296. },
  297. {
  298. .id = IPA_MEM_V4_ROUTE_HASHED,
  299. .offset = 0x0488,
  300. .size = 0x0078,
  301. .canary_count = 2,
  302. },
  303. {
  304. .id = IPA_MEM_V4_ROUTE,
  305. .offset = 0x0508,
  306. .size = 0x0078,
  307. .canary_count = 2,
  308. },
  309. {
  310. .id = IPA_MEM_V6_ROUTE_HASHED,
  311. .offset = 0x0588,
  312. .size = 0x0078,
  313. .canary_count = 2,
  314. },
  315. {
  316. .id = IPA_MEM_V6_ROUTE,
  317. .offset = 0x0608,
  318. .size = 0x0078,
  319. .canary_count = 2,
  320. },
  321. {
  322. .id = IPA_MEM_MODEM_HEADER,
  323. .offset = 0x0688,
  324. .size = 0x0240,
  325. .canary_count = 2,
  326. },
  327. {
  328. .id = IPA_MEM_AP_HEADER,
  329. .offset = 0x08c8,
  330. .size = 0x0200,
  331. .canary_count = 0,
  332. },
  333. {
  334. .id = IPA_MEM_MODEM_PROC_CTX,
  335. .offset = 0x0ad0,
  336. .size = 0x0b20,
  337. .canary_count = 2,
  338. },
  339. {
  340. .id = IPA_MEM_AP_PROC_CTX,
  341. .offset = 0x15f0,
  342. .size = 0x0200,
  343. .canary_count = 0,
  344. },
  345. {
  346. .id = IPA_MEM_NAT_TABLE,
  347. .offset = 0x1800,
  348. .size = 0x0d00,
  349. .canary_count = 4,
  350. },
  351. {
  352. .id = IPA_MEM_STATS_QUOTA_MODEM,
  353. .offset = 0x2510,
  354. .size = 0x0030,
  355. .canary_count = 4,
  356. },
  357. {
  358. .id = IPA_MEM_STATS_QUOTA_AP,
  359. .offset = 0x2540,
  360. .size = 0x0048,
  361. .canary_count = 0,
  362. },
  363. {
  364. .id = IPA_MEM_STATS_TETHERING,
  365. .offset = 0x2588,
  366. .size = 0x0238,
  367. .canary_count = 0,
  368. },
  369. {
  370. .id = IPA_MEM_STATS_FILTER_ROUTE,
  371. .offset = 0x27c0,
  372. .size = 0x0800,
  373. .canary_count = 0,
  374. },
  375. {
  376. .id = IPA_MEM_STATS_DROP,
  377. .offset = 0x2fc0,
  378. .size = 0x0020,
  379. .canary_count = 0,
  380. },
  381. {
  382. .id = IPA_MEM_MODEM,
  383. .offset = 0x2fe8,
  384. .size = 0x0800,
  385. .canary_count = 2,
  386. },
  387. {
  388. .id = IPA_MEM_UC_EVENT_RING,
  389. .offset = 0x3800,
  390. .size = 0x1000,
  391. .canary_count = 1,
  392. },
  393. {
  394. .id = IPA_MEM_PDN_CONFIG,
  395. .offset = 0x4800,
  396. .size = 0x0050,
  397. .canary_count = 0,
  398. },
  399. };
  400. /* Memory configuration data for an SoC having IPA v4.5 */
  401. static const struct ipa_mem_data ipa_mem_data = {
  402. .local_count = ARRAY_SIZE(ipa_mem_local_data),
  403. .local = ipa_mem_local_data,
  404. .imem_addr = 0x14688000,
  405. .imem_size = 0x00003000,
  406. .smem_id = 497,
  407. .smem_size = 0x00009000,
  408. };
  409. /* Interconnect rates are in 1000 byte/second units */
  410. static const struct ipa_interconnect_data ipa_interconnect_data[] = {
  411. {
  412. .name = "memory",
  413. .peak_bandwidth = 600000, /* 600 MBps */
  414. .average_bandwidth = 150000, /* 150 MBps */
  415. },
  416. /* Average rate is unused for the next two interconnects */
  417. {
  418. .name = "imem",
  419. .peak_bandwidth = 450000, /* 450 MBps */
  420. .average_bandwidth = 75000, /* 75 MBps (unused?) */
  421. },
  422. {
  423. .name = "config",
  424. .peak_bandwidth = 171400, /* 171.4 MBps */
  425. .average_bandwidth = 0, /* unused */
  426. },
  427. };
  428. /* Clock and interconnect configuration data for an SoC having IPA v4.5 */
  429. static const struct ipa_power_data ipa_power_data = {
  430. .core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */
  431. .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
  432. .interconnect_data = ipa_interconnect_data,
  433. };
  434. /* Configuration data for an SoC having IPA v4.5 */
  435. const struct ipa_data ipa_data_v4_5 = {
  436. .version = IPA_VERSION_4_5,
  437. .qsb_count = ARRAY_SIZE(ipa_qsb_data),
  438. .qsb_data = ipa_qsb_data,
  439. .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
  440. .endpoint_data = ipa_gsi_endpoint_data,
  441. .resource_data = &ipa_resource_data,
  442. .mem_data = &ipa_mem_data,
  443. .power_data = &ipa_power_data,
  444. };