fjes_hw.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * FUJITSU Extended Socket Network Device driver
  4. * Copyright (c) 2015 FUJITSU LIMITED
  5. */
  6. #include "fjes_hw.h"
  7. #include "fjes.h"
  8. #include "fjes_trace.h"
  9. static void fjes_hw_update_zone_task(struct work_struct *);
  10. static void fjes_hw_epstop_task(struct work_struct *);
  11. /* supported MTU list */
  12. const u32 fjes_support_mtu[] = {
  13. FJES_MTU_DEFINE(8 * 1024),
  14. FJES_MTU_DEFINE(16 * 1024),
  15. FJES_MTU_DEFINE(32 * 1024),
  16. FJES_MTU_DEFINE(64 * 1024),
  17. 0
  18. };
  19. u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg)
  20. {
  21. u8 *base = hw->base;
  22. u32 value = 0;
  23. value = readl(&base[reg]);
  24. return value;
  25. }
  26. static u8 *fjes_hw_iomap(struct fjes_hw *hw)
  27. {
  28. u8 *base;
  29. if (!request_mem_region(hw->hw_res.start, hw->hw_res.size,
  30. fjes_driver_name)) {
  31. pr_err("request_mem_region failed\n");
  32. return NULL;
  33. }
  34. base = (u8 *)ioremap(hw->hw_res.start, hw->hw_res.size);
  35. return base;
  36. }
  37. static void fjes_hw_iounmap(struct fjes_hw *hw)
  38. {
  39. iounmap(hw->base);
  40. release_mem_region(hw->hw_res.start, hw->hw_res.size);
  41. }
  42. int fjes_hw_reset(struct fjes_hw *hw)
  43. {
  44. union REG_DCTL dctl;
  45. int timeout;
  46. dctl.reg = 0;
  47. dctl.bits.reset = 1;
  48. wr32(XSCT_DCTL, dctl.reg);
  49. timeout = FJES_DEVICE_RESET_TIMEOUT * 1000;
  50. dctl.reg = rd32(XSCT_DCTL);
  51. while ((dctl.bits.reset == 1) && (timeout > 0)) {
  52. msleep(1000);
  53. dctl.reg = rd32(XSCT_DCTL);
  54. timeout -= 1000;
  55. }
  56. return timeout > 0 ? 0 : -EIO;
  57. }
  58. static int fjes_hw_get_max_epid(struct fjes_hw *hw)
  59. {
  60. union REG_MAX_EP info;
  61. info.reg = rd32(XSCT_MAX_EP);
  62. return info.bits.maxep;
  63. }
  64. static int fjes_hw_get_my_epid(struct fjes_hw *hw)
  65. {
  66. union REG_OWNER_EPID info;
  67. info.reg = rd32(XSCT_OWNER_EPID);
  68. return info.bits.epid;
  69. }
  70. static int fjes_hw_alloc_shared_status_region(struct fjes_hw *hw)
  71. {
  72. size_t size;
  73. size = sizeof(struct fjes_device_shared_info) +
  74. (sizeof(u8) * hw->max_epid);
  75. hw->hw_info.share = kzalloc(size, GFP_KERNEL);
  76. if (!hw->hw_info.share)
  77. return -ENOMEM;
  78. hw->hw_info.share->epnum = hw->max_epid;
  79. return 0;
  80. }
  81. static void fjes_hw_free_shared_status_region(struct fjes_hw *hw)
  82. {
  83. kfree(hw->hw_info.share);
  84. hw->hw_info.share = NULL;
  85. }
  86. static int fjes_hw_alloc_epbuf(struct epbuf_handler *epbh)
  87. {
  88. void *mem;
  89. mem = vzalloc(EP_BUFFER_SIZE);
  90. if (!mem)
  91. return -ENOMEM;
  92. epbh->buffer = mem;
  93. epbh->size = EP_BUFFER_SIZE;
  94. epbh->info = (union ep_buffer_info *)mem;
  95. epbh->ring = (u8 *)(mem + sizeof(union ep_buffer_info));
  96. return 0;
  97. }
  98. static void fjes_hw_free_epbuf(struct epbuf_handler *epbh)
  99. {
  100. vfree(epbh->buffer);
  101. epbh->buffer = NULL;
  102. epbh->size = 0;
  103. epbh->info = NULL;
  104. epbh->ring = NULL;
  105. }
  106. void fjes_hw_setup_epbuf(struct epbuf_handler *epbh, const u8 *mac_addr,
  107. u32 mtu)
  108. {
  109. union ep_buffer_info *info = epbh->info;
  110. u16 vlan_id[EP_BUFFER_SUPPORT_VLAN_MAX];
  111. int i;
  112. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
  113. vlan_id[i] = info->v1i.vlan_id[i];
  114. memset(info, 0, sizeof(union ep_buffer_info));
  115. info->v1i.version = 0; /* version 0 */
  116. for (i = 0; i < ETH_ALEN; i++)
  117. info->v1i.mac_addr[i] = mac_addr[i];
  118. info->v1i.head = 0;
  119. info->v1i.tail = 1;
  120. info->v1i.info_size = sizeof(union ep_buffer_info);
  121. info->v1i.buffer_size = epbh->size - info->v1i.info_size;
  122. info->v1i.frame_max = FJES_MTU_TO_FRAME_SIZE(mtu);
  123. info->v1i.count_max =
  124. EP_RING_NUM(info->v1i.buffer_size, info->v1i.frame_max);
  125. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
  126. info->v1i.vlan_id[i] = vlan_id[i];
  127. info->v1i.rx_status |= FJES_RX_MTU_CHANGING_DONE;
  128. }
  129. void
  130. fjes_hw_init_command_registers(struct fjes_hw *hw,
  131. struct fjes_device_command_param *param)
  132. {
  133. /* Request Buffer length */
  134. wr32(XSCT_REQBL, (__le32)(param->req_len));
  135. /* Response Buffer Length */
  136. wr32(XSCT_RESPBL, (__le32)(param->res_len));
  137. /* Request Buffer Address */
  138. wr32(XSCT_REQBAL,
  139. (__le32)(param->req_start & GENMASK_ULL(31, 0)));
  140. wr32(XSCT_REQBAH,
  141. (__le32)((param->req_start & GENMASK_ULL(63, 32)) >> 32));
  142. /* Response Buffer Address */
  143. wr32(XSCT_RESPBAL,
  144. (__le32)(param->res_start & GENMASK_ULL(31, 0)));
  145. wr32(XSCT_RESPBAH,
  146. (__le32)((param->res_start & GENMASK_ULL(63, 32)) >> 32));
  147. /* Share status address */
  148. wr32(XSCT_SHSTSAL,
  149. (__le32)(param->share_start & GENMASK_ULL(31, 0)));
  150. wr32(XSCT_SHSTSAH,
  151. (__le32)((param->share_start & GENMASK_ULL(63, 32)) >> 32));
  152. }
  153. static int fjes_hw_setup(struct fjes_hw *hw)
  154. {
  155. u8 mac[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
  156. struct fjes_device_command_param param;
  157. struct ep_share_mem_info *buf_pair;
  158. unsigned long flags;
  159. size_t mem_size;
  160. int result;
  161. int epidx;
  162. void *buf;
  163. hw->hw_info.max_epid = &hw->max_epid;
  164. hw->hw_info.my_epid = &hw->my_epid;
  165. buf = kcalloc(hw->max_epid, sizeof(struct ep_share_mem_info),
  166. GFP_KERNEL);
  167. if (!buf)
  168. return -ENOMEM;
  169. hw->ep_shm_info = (struct ep_share_mem_info *)buf;
  170. mem_size = FJES_DEV_REQ_BUF_SIZE(hw->max_epid);
  171. hw->hw_info.req_buf = kzalloc(mem_size, GFP_KERNEL);
  172. if (!(hw->hw_info.req_buf))
  173. return -ENOMEM;
  174. hw->hw_info.req_buf_size = mem_size;
  175. mem_size = FJES_DEV_RES_BUF_SIZE(hw->max_epid);
  176. hw->hw_info.res_buf = kzalloc(mem_size, GFP_KERNEL);
  177. if (!(hw->hw_info.res_buf))
  178. return -ENOMEM;
  179. hw->hw_info.res_buf_size = mem_size;
  180. result = fjes_hw_alloc_shared_status_region(hw);
  181. if (result)
  182. return result;
  183. hw->hw_info.buffer_share_bit = 0;
  184. hw->hw_info.buffer_unshare_reserve_bit = 0;
  185. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  186. if (epidx != hw->my_epid) {
  187. buf_pair = &hw->ep_shm_info[epidx];
  188. result = fjes_hw_alloc_epbuf(&buf_pair->tx);
  189. if (result)
  190. return result;
  191. result = fjes_hw_alloc_epbuf(&buf_pair->rx);
  192. if (result)
  193. return result;
  194. spin_lock_irqsave(&hw->rx_status_lock, flags);
  195. fjes_hw_setup_epbuf(&buf_pair->tx, mac,
  196. fjes_support_mtu[0]);
  197. fjes_hw_setup_epbuf(&buf_pair->rx, mac,
  198. fjes_support_mtu[0]);
  199. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  200. }
  201. }
  202. memset(&param, 0, sizeof(param));
  203. param.req_len = hw->hw_info.req_buf_size;
  204. param.req_start = __pa(hw->hw_info.req_buf);
  205. param.res_len = hw->hw_info.res_buf_size;
  206. param.res_start = __pa(hw->hw_info.res_buf);
  207. param.share_start = __pa(hw->hw_info.share->ep_status);
  208. fjes_hw_init_command_registers(hw, &param);
  209. return 0;
  210. }
  211. static void fjes_hw_cleanup(struct fjes_hw *hw)
  212. {
  213. int epidx;
  214. if (!hw->ep_shm_info)
  215. return;
  216. fjes_hw_free_shared_status_region(hw);
  217. kfree(hw->hw_info.req_buf);
  218. hw->hw_info.req_buf = NULL;
  219. kfree(hw->hw_info.res_buf);
  220. hw->hw_info.res_buf = NULL;
  221. for (epidx = 0; epidx < hw->max_epid ; epidx++) {
  222. if (epidx == hw->my_epid)
  223. continue;
  224. fjes_hw_free_epbuf(&hw->ep_shm_info[epidx].tx);
  225. fjes_hw_free_epbuf(&hw->ep_shm_info[epidx].rx);
  226. }
  227. kfree(hw->ep_shm_info);
  228. hw->ep_shm_info = NULL;
  229. }
  230. int fjes_hw_init(struct fjes_hw *hw)
  231. {
  232. int ret;
  233. hw->base = fjes_hw_iomap(hw);
  234. if (!hw->base)
  235. return -EIO;
  236. ret = fjes_hw_reset(hw);
  237. if (ret)
  238. return ret;
  239. fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, true);
  240. INIT_WORK(&hw->update_zone_task, fjes_hw_update_zone_task);
  241. INIT_WORK(&hw->epstop_task, fjes_hw_epstop_task);
  242. mutex_init(&hw->hw_info.lock);
  243. spin_lock_init(&hw->rx_status_lock);
  244. hw->max_epid = fjes_hw_get_max_epid(hw);
  245. hw->my_epid = fjes_hw_get_my_epid(hw);
  246. if ((hw->max_epid == 0) || (hw->my_epid >= hw->max_epid))
  247. return -ENXIO;
  248. ret = fjes_hw_setup(hw);
  249. hw->hw_info.trace = vzalloc(FJES_DEBUG_BUFFER_SIZE);
  250. hw->hw_info.trace_size = FJES_DEBUG_BUFFER_SIZE;
  251. return ret;
  252. }
  253. void fjes_hw_exit(struct fjes_hw *hw)
  254. {
  255. int ret;
  256. if (hw->base) {
  257. if (hw->debug_mode) {
  258. /* disable debug mode */
  259. mutex_lock(&hw->hw_info.lock);
  260. fjes_hw_stop_debug(hw);
  261. mutex_unlock(&hw->hw_info.lock);
  262. }
  263. vfree(hw->hw_info.trace);
  264. hw->hw_info.trace = NULL;
  265. hw->hw_info.trace_size = 0;
  266. hw->debug_mode = 0;
  267. ret = fjes_hw_reset(hw);
  268. if (ret)
  269. pr_err("%s: reset error", __func__);
  270. fjes_hw_iounmap(hw);
  271. hw->base = NULL;
  272. }
  273. fjes_hw_cleanup(hw);
  274. cancel_work_sync(&hw->update_zone_task);
  275. cancel_work_sync(&hw->epstop_task);
  276. }
  277. static enum fjes_dev_command_response_e
  278. fjes_hw_issue_request_command(struct fjes_hw *hw,
  279. enum fjes_dev_command_request_type type)
  280. {
  281. enum fjes_dev_command_response_e ret = FJES_CMD_STATUS_UNKNOWN;
  282. union REG_CR cr;
  283. union REG_CS cs;
  284. int timeout = FJES_COMMAND_REQ_TIMEOUT * 1000;
  285. cr.reg = 0;
  286. cr.bits.req_start = 1;
  287. cr.bits.req_code = type;
  288. wr32(XSCT_CR, cr.reg);
  289. cr.reg = rd32(XSCT_CR);
  290. if (cr.bits.error == 0) {
  291. timeout = FJES_COMMAND_REQ_TIMEOUT * 1000;
  292. cs.reg = rd32(XSCT_CS);
  293. while ((cs.bits.complete != 1) && timeout > 0) {
  294. msleep(1000);
  295. cs.reg = rd32(XSCT_CS);
  296. timeout -= 1000;
  297. }
  298. if (cs.bits.complete == 1)
  299. ret = FJES_CMD_STATUS_NORMAL;
  300. else if (timeout <= 0)
  301. ret = FJES_CMD_STATUS_TIMEOUT;
  302. } else {
  303. switch (cr.bits.err_info) {
  304. case FJES_CMD_REQ_ERR_INFO_PARAM:
  305. ret = FJES_CMD_STATUS_ERROR_PARAM;
  306. break;
  307. case FJES_CMD_REQ_ERR_INFO_STATUS:
  308. ret = FJES_CMD_STATUS_ERROR_STATUS;
  309. break;
  310. default:
  311. ret = FJES_CMD_STATUS_UNKNOWN;
  312. break;
  313. }
  314. }
  315. trace_fjes_hw_issue_request_command(&cr, &cs, timeout, ret);
  316. return ret;
  317. }
  318. int fjes_hw_request_info(struct fjes_hw *hw)
  319. {
  320. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  321. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  322. enum fjes_dev_command_response_e ret;
  323. int result;
  324. memset(req_buf, 0, hw->hw_info.req_buf_size);
  325. memset(res_buf, 0, hw->hw_info.res_buf_size);
  326. req_buf->info.length = FJES_DEV_COMMAND_INFO_REQ_LEN;
  327. res_buf->info.length = 0;
  328. res_buf->info.code = 0;
  329. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_INFO);
  330. trace_fjes_hw_request_info(hw, res_buf);
  331. result = 0;
  332. if (FJES_DEV_COMMAND_INFO_RES_LEN((*hw->hw_info.max_epid)) !=
  333. res_buf->info.length) {
  334. trace_fjes_hw_request_info_err("Invalid res_buf");
  335. result = -ENOMSG;
  336. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  337. switch (res_buf->info.code) {
  338. case FJES_CMD_REQ_RES_CODE_NORMAL:
  339. result = 0;
  340. break;
  341. default:
  342. result = -EPERM;
  343. break;
  344. }
  345. } else {
  346. switch (ret) {
  347. case FJES_CMD_STATUS_UNKNOWN:
  348. result = -EPERM;
  349. break;
  350. case FJES_CMD_STATUS_TIMEOUT:
  351. trace_fjes_hw_request_info_err("Timeout");
  352. result = -EBUSY;
  353. break;
  354. case FJES_CMD_STATUS_ERROR_PARAM:
  355. result = -EPERM;
  356. break;
  357. case FJES_CMD_STATUS_ERROR_STATUS:
  358. result = -EPERM;
  359. break;
  360. default:
  361. result = -EPERM;
  362. break;
  363. }
  364. }
  365. return result;
  366. }
  367. int fjes_hw_register_buff_addr(struct fjes_hw *hw, int dest_epid,
  368. struct ep_share_mem_info *buf_pair)
  369. {
  370. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  371. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  372. enum fjes_dev_command_response_e ret;
  373. int page_count;
  374. int timeout;
  375. int i, idx;
  376. void *addr;
  377. int result;
  378. if (test_bit(dest_epid, &hw->hw_info.buffer_share_bit))
  379. return 0;
  380. memset(req_buf, 0, hw->hw_info.req_buf_size);
  381. memset(res_buf, 0, hw->hw_info.res_buf_size);
  382. req_buf->share_buffer.length = FJES_DEV_COMMAND_SHARE_BUFFER_REQ_LEN(
  383. buf_pair->tx.size,
  384. buf_pair->rx.size);
  385. req_buf->share_buffer.epid = dest_epid;
  386. idx = 0;
  387. req_buf->share_buffer.buffer[idx++] = buf_pair->tx.size;
  388. page_count = buf_pair->tx.size / EP_BUFFER_INFO_SIZE;
  389. for (i = 0; i < page_count; i++) {
  390. addr = ((u8 *)(buf_pair->tx.buffer)) +
  391. (i * EP_BUFFER_INFO_SIZE);
  392. req_buf->share_buffer.buffer[idx++] =
  393. (__le64)(page_to_phys(vmalloc_to_page(addr)) +
  394. offset_in_page(addr));
  395. }
  396. req_buf->share_buffer.buffer[idx++] = buf_pair->rx.size;
  397. page_count = buf_pair->rx.size / EP_BUFFER_INFO_SIZE;
  398. for (i = 0; i < page_count; i++) {
  399. addr = ((u8 *)(buf_pair->rx.buffer)) +
  400. (i * EP_BUFFER_INFO_SIZE);
  401. req_buf->share_buffer.buffer[idx++] =
  402. (__le64)(page_to_phys(vmalloc_to_page(addr)) +
  403. offset_in_page(addr));
  404. }
  405. res_buf->share_buffer.length = 0;
  406. res_buf->share_buffer.code = 0;
  407. trace_fjes_hw_register_buff_addr_req(req_buf, buf_pair);
  408. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_SHARE_BUFFER);
  409. timeout = FJES_COMMAND_REQ_BUFF_TIMEOUT * 1000;
  410. while ((ret == FJES_CMD_STATUS_NORMAL) &&
  411. (res_buf->share_buffer.length ==
  412. FJES_DEV_COMMAND_SHARE_BUFFER_RES_LEN) &&
  413. (res_buf->share_buffer.code == FJES_CMD_REQ_RES_CODE_BUSY) &&
  414. (timeout > 0)) {
  415. msleep(200 + hw->my_epid * 20);
  416. timeout -= (200 + hw->my_epid * 20);
  417. res_buf->share_buffer.length = 0;
  418. res_buf->share_buffer.code = 0;
  419. ret = fjes_hw_issue_request_command(
  420. hw, FJES_CMD_REQ_SHARE_BUFFER);
  421. }
  422. result = 0;
  423. trace_fjes_hw_register_buff_addr(res_buf, timeout);
  424. if (res_buf->share_buffer.length !=
  425. FJES_DEV_COMMAND_SHARE_BUFFER_RES_LEN) {
  426. trace_fjes_hw_register_buff_addr_err("Invalid res_buf");
  427. result = -ENOMSG;
  428. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  429. switch (res_buf->share_buffer.code) {
  430. case FJES_CMD_REQ_RES_CODE_NORMAL:
  431. result = 0;
  432. set_bit(dest_epid, &hw->hw_info.buffer_share_bit);
  433. break;
  434. case FJES_CMD_REQ_RES_CODE_BUSY:
  435. trace_fjes_hw_register_buff_addr_err("Busy Timeout");
  436. result = -EBUSY;
  437. break;
  438. default:
  439. result = -EPERM;
  440. break;
  441. }
  442. } else {
  443. switch (ret) {
  444. case FJES_CMD_STATUS_UNKNOWN:
  445. result = -EPERM;
  446. break;
  447. case FJES_CMD_STATUS_TIMEOUT:
  448. trace_fjes_hw_register_buff_addr_err("Timeout");
  449. result = -EBUSY;
  450. break;
  451. case FJES_CMD_STATUS_ERROR_PARAM:
  452. case FJES_CMD_STATUS_ERROR_STATUS:
  453. default:
  454. result = -EPERM;
  455. break;
  456. }
  457. }
  458. return result;
  459. }
  460. int fjes_hw_unregister_buff_addr(struct fjes_hw *hw, int dest_epid)
  461. {
  462. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  463. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  464. struct fjes_device_shared_info *share = hw->hw_info.share;
  465. enum fjes_dev_command_response_e ret;
  466. int timeout;
  467. int result;
  468. if (!hw->base)
  469. return -EPERM;
  470. if (!req_buf || !res_buf || !share)
  471. return -EPERM;
  472. if (!test_bit(dest_epid, &hw->hw_info.buffer_share_bit))
  473. return 0;
  474. memset(req_buf, 0, hw->hw_info.req_buf_size);
  475. memset(res_buf, 0, hw->hw_info.res_buf_size);
  476. req_buf->unshare_buffer.length =
  477. FJES_DEV_COMMAND_UNSHARE_BUFFER_REQ_LEN;
  478. req_buf->unshare_buffer.epid = dest_epid;
  479. res_buf->unshare_buffer.length = 0;
  480. res_buf->unshare_buffer.code = 0;
  481. trace_fjes_hw_unregister_buff_addr_req(req_buf);
  482. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_UNSHARE_BUFFER);
  483. timeout = FJES_COMMAND_REQ_BUFF_TIMEOUT * 1000;
  484. while ((ret == FJES_CMD_STATUS_NORMAL) &&
  485. (res_buf->unshare_buffer.length ==
  486. FJES_DEV_COMMAND_UNSHARE_BUFFER_RES_LEN) &&
  487. (res_buf->unshare_buffer.code ==
  488. FJES_CMD_REQ_RES_CODE_BUSY) &&
  489. (timeout > 0)) {
  490. msleep(200 + hw->my_epid * 20);
  491. timeout -= (200 + hw->my_epid * 20);
  492. res_buf->unshare_buffer.length = 0;
  493. res_buf->unshare_buffer.code = 0;
  494. ret =
  495. fjes_hw_issue_request_command(hw, FJES_CMD_REQ_UNSHARE_BUFFER);
  496. }
  497. result = 0;
  498. trace_fjes_hw_unregister_buff_addr(res_buf, timeout);
  499. if (res_buf->unshare_buffer.length !=
  500. FJES_DEV_COMMAND_UNSHARE_BUFFER_RES_LEN) {
  501. trace_fjes_hw_unregister_buff_addr_err("Invalid res_buf");
  502. result = -ENOMSG;
  503. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  504. switch (res_buf->unshare_buffer.code) {
  505. case FJES_CMD_REQ_RES_CODE_NORMAL:
  506. result = 0;
  507. clear_bit(dest_epid, &hw->hw_info.buffer_share_bit);
  508. break;
  509. case FJES_CMD_REQ_RES_CODE_BUSY:
  510. trace_fjes_hw_unregister_buff_addr_err("Busy Timeout");
  511. result = -EBUSY;
  512. break;
  513. default:
  514. result = -EPERM;
  515. break;
  516. }
  517. } else {
  518. switch (ret) {
  519. case FJES_CMD_STATUS_UNKNOWN:
  520. result = -EPERM;
  521. break;
  522. case FJES_CMD_STATUS_TIMEOUT:
  523. trace_fjes_hw_unregister_buff_addr_err("Timeout");
  524. result = -EBUSY;
  525. break;
  526. case FJES_CMD_STATUS_ERROR_PARAM:
  527. case FJES_CMD_STATUS_ERROR_STATUS:
  528. default:
  529. result = -EPERM;
  530. break;
  531. }
  532. }
  533. return result;
  534. }
  535. int fjes_hw_raise_interrupt(struct fjes_hw *hw, int dest_epid,
  536. enum REG_ICTL_MASK mask)
  537. {
  538. u32 ig = mask | dest_epid;
  539. wr32(XSCT_IG, cpu_to_le32(ig));
  540. return 0;
  541. }
  542. u32 fjes_hw_capture_interrupt_status(struct fjes_hw *hw)
  543. {
  544. u32 cur_is;
  545. cur_is = rd32(XSCT_IS);
  546. return cur_is;
  547. }
  548. void fjes_hw_set_irqmask(struct fjes_hw *hw,
  549. enum REG_ICTL_MASK intr_mask, bool mask)
  550. {
  551. if (mask)
  552. wr32(XSCT_IMS, intr_mask);
  553. else
  554. wr32(XSCT_IMC, intr_mask);
  555. }
  556. bool fjes_hw_epid_is_same_zone(struct fjes_hw *hw, int epid)
  557. {
  558. if (epid >= hw->max_epid)
  559. return false;
  560. if ((hw->ep_shm_info[epid].es_status !=
  561. FJES_ZONING_STATUS_ENABLE) ||
  562. (hw->ep_shm_info[hw->my_epid].zone ==
  563. FJES_ZONING_ZONE_TYPE_NONE))
  564. return false;
  565. else
  566. return (hw->ep_shm_info[epid].zone ==
  567. hw->ep_shm_info[hw->my_epid].zone);
  568. }
  569. int fjes_hw_epid_is_shared(struct fjes_device_shared_info *share,
  570. int dest_epid)
  571. {
  572. int value = false;
  573. if (dest_epid < share->epnum)
  574. value = share->ep_status[dest_epid];
  575. return value;
  576. }
  577. static bool fjes_hw_epid_is_stop_requested(struct fjes_hw *hw, int src_epid)
  578. {
  579. return test_bit(src_epid, &hw->txrx_stop_req_bit);
  580. }
  581. static bool fjes_hw_epid_is_stop_process_done(struct fjes_hw *hw, int src_epid)
  582. {
  583. return (hw->ep_shm_info[src_epid].tx.info->v1i.rx_status &
  584. FJES_RX_STOP_REQ_DONE);
  585. }
  586. enum ep_partner_status
  587. fjes_hw_get_partner_ep_status(struct fjes_hw *hw, int epid)
  588. {
  589. enum ep_partner_status status;
  590. if (fjes_hw_epid_is_shared(hw->hw_info.share, epid)) {
  591. if (fjes_hw_epid_is_stop_requested(hw, epid)) {
  592. status = EP_PARTNER_WAITING;
  593. } else {
  594. if (fjes_hw_epid_is_stop_process_done(hw, epid))
  595. status = EP_PARTNER_COMPLETE;
  596. else
  597. status = EP_PARTNER_SHARED;
  598. }
  599. } else {
  600. status = EP_PARTNER_UNSHARE;
  601. }
  602. return status;
  603. }
  604. void fjes_hw_raise_epstop(struct fjes_hw *hw)
  605. {
  606. enum ep_partner_status status;
  607. unsigned long flags;
  608. int epidx;
  609. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  610. if (epidx == hw->my_epid)
  611. continue;
  612. status = fjes_hw_get_partner_ep_status(hw, epidx);
  613. switch (status) {
  614. case EP_PARTNER_SHARED:
  615. fjes_hw_raise_interrupt(hw, epidx,
  616. REG_ICTL_MASK_TXRX_STOP_REQ);
  617. hw->ep_shm_info[epidx].ep_stats.send_intr_unshare += 1;
  618. break;
  619. default:
  620. break;
  621. }
  622. set_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit);
  623. set_bit(epidx, &hw->txrx_stop_req_bit);
  624. spin_lock_irqsave(&hw->rx_status_lock, flags);
  625. hw->ep_shm_info[epidx].tx.info->v1i.rx_status |=
  626. FJES_RX_STOP_REQ_REQUEST;
  627. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  628. }
  629. }
  630. int fjes_hw_wait_epstop(struct fjes_hw *hw)
  631. {
  632. enum ep_partner_status status;
  633. union ep_buffer_info *info;
  634. int wait_time = 0;
  635. int epidx;
  636. while (hw->hw_info.buffer_unshare_reserve_bit &&
  637. (wait_time < FJES_COMMAND_EPSTOP_WAIT_TIMEOUT * 1000)) {
  638. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  639. if (epidx == hw->my_epid)
  640. continue;
  641. status = fjes_hw_epid_is_shared(hw->hw_info.share,
  642. epidx);
  643. info = hw->ep_shm_info[epidx].rx.info;
  644. if ((!status ||
  645. (info->v1i.rx_status &
  646. FJES_RX_STOP_REQ_DONE)) &&
  647. test_bit(epidx,
  648. &hw->hw_info.buffer_unshare_reserve_bit)) {
  649. clear_bit(epidx,
  650. &hw->hw_info.buffer_unshare_reserve_bit);
  651. }
  652. }
  653. msleep(100);
  654. wait_time += 100;
  655. }
  656. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  657. if (epidx == hw->my_epid)
  658. continue;
  659. if (test_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit))
  660. clear_bit(epidx,
  661. &hw->hw_info.buffer_unshare_reserve_bit);
  662. }
  663. return (wait_time < FJES_COMMAND_EPSTOP_WAIT_TIMEOUT * 1000)
  664. ? 0 : -EBUSY;
  665. }
  666. bool fjes_hw_check_epbuf_version(struct epbuf_handler *epbh, u32 version)
  667. {
  668. union ep_buffer_info *info = epbh->info;
  669. return (info->common.version == version);
  670. }
  671. bool fjes_hw_check_mtu(struct epbuf_handler *epbh, u32 mtu)
  672. {
  673. union ep_buffer_info *info = epbh->info;
  674. return ((info->v1i.frame_max == FJES_MTU_TO_FRAME_SIZE(mtu)) &&
  675. info->v1i.rx_status & FJES_RX_MTU_CHANGING_DONE);
  676. }
  677. bool fjes_hw_check_vlan_id(struct epbuf_handler *epbh, u16 vlan_id)
  678. {
  679. union ep_buffer_info *info = epbh->info;
  680. bool ret = false;
  681. int i;
  682. if (vlan_id == 0) {
  683. ret = true;
  684. } else {
  685. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++) {
  686. if (vlan_id == info->v1i.vlan_id[i]) {
  687. ret = true;
  688. break;
  689. }
  690. }
  691. }
  692. return ret;
  693. }
  694. bool fjes_hw_set_vlan_id(struct epbuf_handler *epbh, u16 vlan_id)
  695. {
  696. union ep_buffer_info *info = epbh->info;
  697. int i;
  698. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++) {
  699. if (info->v1i.vlan_id[i] == 0) {
  700. info->v1i.vlan_id[i] = vlan_id;
  701. return true;
  702. }
  703. }
  704. return false;
  705. }
  706. void fjes_hw_del_vlan_id(struct epbuf_handler *epbh, u16 vlan_id)
  707. {
  708. union ep_buffer_info *info = epbh->info;
  709. int i;
  710. if (0 != vlan_id) {
  711. for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++) {
  712. if (vlan_id == info->v1i.vlan_id[i])
  713. info->v1i.vlan_id[i] = 0;
  714. }
  715. }
  716. }
  717. bool fjes_hw_epbuf_rx_is_empty(struct epbuf_handler *epbh)
  718. {
  719. union ep_buffer_info *info = epbh->info;
  720. if (!(info->v1i.rx_status & FJES_RX_MTU_CHANGING_DONE))
  721. return true;
  722. if (info->v1i.count_max == 0)
  723. return true;
  724. return EP_RING_EMPTY(info->v1i.head, info->v1i.tail,
  725. info->v1i.count_max);
  726. }
  727. void *fjes_hw_epbuf_rx_curpkt_get_addr(struct epbuf_handler *epbh,
  728. size_t *psize)
  729. {
  730. union ep_buffer_info *info = epbh->info;
  731. struct esmem_frame *ring_frame;
  732. void *frame;
  733. ring_frame = (struct esmem_frame *)&(epbh->ring[EP_RING_INDEX
  734. (info->v1i.head,
  735. info->v1i.count_max) *
  736. info->v1i.frame_max]);
  737. *psize = (size_t)ring_frame->frame_size;
  738. frame = ring_frame->frame_data;
  739. return frame;
  740. }
  741. void fjes_hw_epbuf_rx_curpkt_drop(struct epbuf_handler *epbh)
  742. {
  743. union ep_buffer_info *info = epbh->info;
  744. if (fjes_hw_epbuf_rx_is_empty(epbh))
  745. return;
  746. EP_RING_INDEX_INC(epbh->info->v1i.head, info->v1i.count_max);
  747. }
  748. int fjes_hw_epbuf_tx_pkt_send(struct epbuf_handler *epbh,
  749. void *frame, size_t size)
  750. {
  751. union ep_buffer_info *info = epbh->info;
  752. struct esmem_frame *ring_frame;
  753. if (EP_RING_FULL(info->v1i.head, info->v1i.tail, info->v1i.count_max))
  754. return -ENOBUFS;
  755. ring_frame = (struct esmem_frame *)&(epbh->ring[EP_RING_INDEX
  756. (info->v1i.tail - 1,
  757. info->v1i.count_max) *
  758. info->v1i.frame_max]);
  759. ring_frame->frame_size = size;
  760. memcpy((void *)(ring_frame->frame_data), (void *)frame, size);
  761. EP_RING_INDEX_INC(epbh->info->v1i.tail, info->v1i.count_max);
  762. return 0;
  763. }
  764. static void fjes_hw_update_zone_task(struct work_struct *work)
  765. {
  766. struct fjes_hw *hw = container_of(work,
  767. struct fjes_hw, update_zone_task);
  768. struct my_s {u8 es_status; u8 zone; } *info;
  769. union fjes_device_command_res *res_buf;
  770. enum ep_partner_status pstatus;
  771. struct fjes_adapter *adapter;
  772. struct net_device *netdev;
  773. unsigned long flags;
  774. ulong unshare_bit = 0;
  775. ulong share_bit = 0;
  776. ulong irq_bit = 0;
  777. int epidx;
  778. int ret;
  779. adapter = (struct fjes_adapter *)hw->back;
  780. netdev = adapter->netdev;
  781. res_buf = hw->hw_info.res_buf;
  782. info = (struct my_s *)&res_buf->info.info;
  783. mutex_lock(&hw->hw_info.lock);
  784. ret = fjes_hw_request_info(hw);
  785. switch (ret) {
  786. case -ENOMSG:
  787. case -EBUSY:
  788. default:
  789. if (!work_pending(&adapter->force_close_task)) {
  790. adapter->force_reset = true;
  791. schedule_work(&adapter->force_close_task);
  792. }
  793. break;
  794. case 0:
  795. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  796. if (epidx == hw->my_epid) {
  797. hw->ep_shm_info[epidx].es_status =
  798. info[epidx].es_status;
  799. hw->ep_shm_info[epidx].zone =
  800. info[epidx].zone;
  801. continue;
  802. }
  803. pstatus = fjes_hw_get_partner_ep_status(hw, epidx);
  804. switch (pstatus) {
  805. case EP_PARTNER_UNSHARE:
  806. default:
  807. if ((info[epidx].zone !=
  808. FJES_ZONING_ZONE_TYPE_NONE) &&
  809. (info[epidx].es_status ==
  810. FJES_ZONING_STATUS_ENABLE) &&
  811. (info[epidx].zone ==
  812. info[hw->my_epid].zone))
  813. set_bit(epidx, &share_bit);
  814. else
  815. set_bit(epidx, &unshare_bit);
  816. break;
  817. case EP_PARTNER_COMPLETE:
  818. case EP_PARTNER_WAITING:
  819. if ((info[epidx].zone ==
  820. FJES_ZONING_ZONE_TYPE_NONE) ||
  821. (info[epidx].es_status !=
  822. FJES_ZONING_STATUS_ENABLE) ||
  823. (info[epidx].zone !=
  824. info[hw->my_epid].zone)) {
  825. set_bit(epidx,
  826. &adapter->unshare_watch_bitmask);
  827. set_bit(epidx,
  828. &hw->hw_info.buffer_unshare_reserve_bit);
  829. }
  830. break;
  831. case EP_PARTNER_SHARED:
  832. if ((info[epidx].zone ==
  833. FJES_ZONING_ZONE_TYPE_NONE) ||
  834. (info[epidx].es_status !=
  835. FJES_ZONING_STATUS_ENABLE) ||
  836. (info[epidx].zone !=
  837. info[hw->my_epid].zone))
  838. set_bit(epidx, &irq_bit);
  839. break;
  840. }
  841. hw->ep_shm_info[epidx].es_status =
  842. info[epidx].es_status;
  843. hw->ep_shm_info[epidx].zone = info[epidx].zone;
  844. }
  845. break;
  846. }
  847. mutex_unlock(&hw->hw_info.lock);
  848. for (epidx = 0; epidx < hw->max_epid; epidx++) {
  849. if (epidx == hw->my_epid)
  850. continue;
  851. if (test_bit(epidx, &share_bit)) {
  852. spin_lock_irqsave(&hw->rx_status_lock, flags);
  853. fjes_hw_setup_epbuf(&hw->ep_shm_info[epidx].tx,
  854. netdev->dev_addr, netdev->mtu);
  855. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  856. mutex_lock(&hw->hw_info.lock);
  857. ret = fjes_hw_register_buff_addr(
  858. hw, epidx, &hw->ep_shm_info[epidx]);
  859. switch (ret) {
  860. case 0:
  861. break;
  862. case -ENOMSG:
  863. case -EBUSY:
  864. default:
  865. if (!work_pending(&adapter->force_close_task)) {
  866. adapter->force_reset = true;
  867. schedule_work(
  868. &adapter->force_close_task);
  869. }
  870. break;
  871. }
  872. mutex_unlock(&hw->hw_info.lock);
  873. hw->ep_shm_info[epidx].ep_stats
  874. .com_regist_buf_exec += 1;
  875. }
  876. if (test_bit(epidx, &unshare_bit)) {
  877. mutex_lock(&hw->hw_info.lock);
  878. ret = fjes_hw_unregister_buff_addr(hw, epidx);
  879. switch (ret) {
  880. case 0:
  881. break;
  882. case -ENOMSG:
  883. case -EBUSY:
  884. default:
  885. if (!work_pending(&adapter->force_close_task)) {
  886. adapter->force_reset = true;
  887. schedule_work(
  888. &adapter->force_close_task);
  889. }
  890. break;
  891. }
  892. mutex_unlock(&hw->hw_info.lock);
  893. hw->ep_shm_info[epidx].ep_stats
  894. .com_unregist_buf_exec += 1;
  895. if (ret == 0) {
  896. spin_lock_irqsave(&hw->rx_status_lock, flags);
  897. fjes_hw_setup_epbuf(
  898. &hw->ep_shm_info[epidx].tx,
  899. netdev->dev_addr, netdev->mtu);
  900. spin_unlock_irqrestore(&hw->rx_status_lock,
  901. flags);
  902. }
  903. }
  904. if (test_bit(epidx, &irq_bit)) {
  905. fjes_hw_raise_interrupt(hw, epidx,
  906. REG_ICTL_MASK_TXRX_STOP_REQ);
  907. hw->ep_shm_info[epidx].ep_stats.send_intr_unshare += 1;
  908. set_bit(epidx, &hw->txrx_stop_req_bit);
  909. spin_lock_irqsave(&hw->rx_status_lock, flags);
  910. hw->ep_shm_info[epidx].tx.
  911. info->v1i.rx_status |=
  912. FJES_RX_STOP_REQ_REQUEST;
  913. spin_unlock_irqrestore(&hw->rx_status_lock, flags);
  914. set_bit(epidx, &hw->hw_info.buffer_unshare_reserve_bit);
  915. }
  916. }
  917. if (irq_bit || adapter->unshare_watch_bitmask) {
  918. if (!work_pending(&adapter->unshare_watch_task))
  919. queue_work(adapter->control_wq,
  920. &adapter->unshare_watch_task);
  921. }
  922. }
  923. static void fjes_hw_epstop_task(struct work_struct *work)
  924. {
  925. struct fjes_hw *hw = container_of(work, struct fjes_hw, epstop_task);
  926. struct fjes_adapter *adapter = (struct fjes_adapter *)hw->back;
  927. unsigned long flags;
  928. ulong remain_bit;
  929. int epid_bit;
  930. while ((remain_bit = hw->epstop_req_bit)) {
  931. for (epid_bit = 0; remain_bit; remain_bit >>= 1, epid_bit++) {
  932. if (remain_bit & 1) {
  933. spin_lock_irqsave(&hw->rx_status_lock, flags);
  934. hw->ep_shm_info[epid_bit].
  935. tx.info->v1i.rx_status |=
  936. FJES_RX_STOP_REQ_DONE;
  937. spin_unlock_irqrestore(&hw->rx_status_lock,
  938. flags);
  939. clear_bit(epid_bit, &hw->epstop_req_bit);
  940. set_bit(epid_bit,
  941. &adapter->unshare_watch_bitmask);
  942. if (!work_pending(&adapter->unshare_watch_task))
  943. queue_work(
  944. adapter->control_wq,
  945. &adapter->unshare_watch_task);
  946. }
  947. }
  948. }
  949. }
  950. int fjes_hw_start_debug(struct fjes_hw *hw)
  951. {
  952. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  953. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  954. enum fjes_dev_command_response_e ret;
  955. int page_count;
  956. int result = 0;
  957. void *addr;
  958. int i;
  959. if (!hw->hw_info.trace)
  960. return -EPERM;
  961. memset(hw->hw_info.trace, 0, FJES_DEBUG_BUFFER_SIZE);
  962. memset(req_buf, 0, hw->hw_info.req_buf_size);
  963. memset(res_buf, 0, hw->hw_info.res_buf_size);
  964. req_buf->start_trace.length =
  965. FJES_DEV_COMMAND_START_DBG_REQ_LEN(hw->hw_info.trace_size);
  966. req_buf->start_trace.mode = hw->debug_mode;
  967. req_buf->start_trace.buffer_len = hw->hw_info.trace_size;
  968. page_count = hw->hw_info.trace_size / FJES_DEBUG_PAGE_SIZE;
  969. for (i = 0; i < page_count; i++) {
  970. addr = ((u8 *)hw->hw_info.trace) + i * FJES_DEBUG_PAGE_SIZE;
  971. req_buf->start_trace.buffer[i] =
  972. (__le64)(page_to_phys(vmalloc_to_page(addr)) +
  973. offset_in_page(addr));
  974. }
  975. res_buf->start_trace.length = 0;
  976. res_buf->start_trace.code = 0;
  977. trace_fjes_hw_start_debug_req(req_buf);
  978. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_START_DEBUG);
  979. trace_fjes_hw_start_debug(res_buf);
  980. if (res_buf->start_trace.length !=
  981. FJES_DEV_COMMAND_START_DBG_RES_LEN) {
  982. result = -ENOMSG;
  983. trace_fjes_hw_start_debug_err("Invalid res_buf");
  984. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  985. switch (res_buf->start_trace.code) {
  986. case FJES_CMD_REQ_RES_CODE_NORMAL:
  987. result = 0;
  988. break;
  989. default:
  990. result = -EPERM;
  991. break;
  992. }
  993. } else {
  994. switch (ret) {
  995. case FJES_CMD_STATUS_UNKNOWN:
  996. result = -EPERM;
  997. break;
  998. case FJES_CMD_STATUS_TIMEOUT:
  999. trace_fjes_hw_start_debug_err("Busy Timeout");
  1000. result = -EBUSY;
  1001. break;
  1002. case FJES_CMD_STATUS_ERROR_PARAM:
  1003. case FJES_CMD_STATUS_ERROR_STATUS:
  1004. default:
  1005. result = -EPERM;
  1006. break;
  1007. }
  1008. }
  1009. return result;
  1010. }
  1011. int fjes_hw_stop_debug(struct fjes_hw *hw)
  1012. {
  1013. union fjes_device_command_req *req_buf = hw->hw_info.req_buf;
  1014. union fjes_device_command_res *res_buf = hw->hw_info.res_buf;
  1015. enum fjes_dev_command_response_e ret;
  1016. int result = 0;
  1017. if (!hw->hw_info.trace)
  1018. return -EPERM;
  1019. memset(req_buf, 0, hw->hw_info.req_buf_size);
  1020. memset(res_buf, 0, hw->hw_info.res_buf_size);
  1021. req_buf->stop_trace.length = FJES_DEV_COMMAND_STOP_DBG_REQ_LEN;
  1022. res_buf->stop_trace.length = 0;
  1023. res_buf->stop_trace.code = 0;
  1024. ret = fjes_hw_issue_request_command(hw, FJES_CMD_REQ_STOP_DEBUG);
  1025. trace_fjes_hw_stop_debug(res_buf);
  1026. if (res_buf->stop_trace.length != FJES_DEV_COMMAND_STOP_DBG_RES_LEN) {
  1027. trace_fjes_hw_stop_debug_err("Invalid res_buf");
  1028. result = -ENOMSG;
  1029. } else if (ret == FJES_CMD_STATUS_NORMAL) {
  1030. switch (res_buf->stop_trace.code) {
  1031. case FJES_CMD_REQ_RES_CODE_NORMAL:
  1032. result = 0;
  1033. hw->debug_mode = 0;
  1034. break;
  1035. default:
  1036. result = -EPERM;
  1037. break;
  1038. }
  1039. } else {
  1040. switch (ret) {
  1041. case FJES_CMD_STATUS_UNKNOWN:
  1042. result = -EPERM;
  1043. break;
  1044. case FJES_CMD_STATUS_TIMEOUT:
  1045. result = -EBUSY;
  1046. trace_fjes_hw_stop_debug_err("Busy Timeout");
  1047. break;
  1048. case FJES_CMD_STATUS_ERROR_PARAM:
  1049. case FJES_CMD_STATUS_ERROR_STATUS:
  1050. default:
  1051. result = -EPERM;
  1052. break;
  1053. }
  1054. }
  1055. return result;
  1056. }