cpsw_ethtool.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments Ethernet Switch Driver ethtool intf
  4. *
  5. * Copyright (C) 2019 Texas Instruments
  6. */
  7. #include <linux/if_ether.h>
  8. #include <linux/if_vlan.h>
  9. #include <linux/kmemleak.h>
  10. #include <linux/module.h>
  11. #include <linux/netdevice.h>
  12. #include <linux/net_tstamp.h>
  13. #include <linux/phy.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/skbuff.h>
  16. #include "cpsw.h"
  17. #include "cpts.h"
  18. #include "cpsw_ale.h"
  19. #include "cpsw_priv.h"
  20. #include "davinci_cpdma.h"
  21. struct cpsw_hw_stats {
  22. u32 rxgoodframes;
  23. u32 rxbroadcastframes;
  24. u32 rxmulticastframes;
  25. u32 rxpauseframes;
  26. u32 rxcrcerrors;
  27. u32 rxaligncodeerrors;
  28. u32 rxoversizedframes;
  29. u32 rxjabberframes;
  30. u32 rxundersizedframes;
  31. u32 rxfragments;
  32. u32 __pad_0[2];
  33. u32 rxoctets;
  34. u32 txgoodframes;
  35. u32 txbroadcastframes;
  36. u32 txmulticastframes;
  37. u32 txpauseframes;
  38. u32 txdeferredframes;
  39. u32 txcollisionframes;
  40. u32 txsinglecollframes;
  41. u32 txmultcollframes;
  42. u32 txexcessivecollisions;
  43. u32 txlatecollisions;
  44. u32 txunderrun;
  45. u32 txcarriersenseerrors;
  46. u32 txoctets;
  47. u32 octetframes64;
  48. u32 octetframes65t127;
  49. u32 octetframes128t255;
  50. u32 octetframes256t511;
  51. u32 octetframes512t1023;
  52. u32 octetframes1024tup;
  53. u32 netoctets;
  54. u32 rxsofoverruns;
  55. u32 rxmofoverruns;
  56. u32 rxdmaoverruns;
  57. };
  58. struct cpsw_stats {
  59. char stat_string[ETH_GSTRING_LEN];
  60. int type;
  61. int sizeof_stat;
  62. int stat_offset;
  63. };
  64. enum {
  65. CPSW_STATS,
  66. CPDMA_RX_STATS,
  67. CPDMA_TX_STATS,
  68. };
  69. #define CPSW_STAT(m) CPSW_STATS, \
  70. sizeof_field(struct cpsw_hw_stats, m), \
  71. offsetof(struct cpsw_hw_stats, m)
  72. #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
  73. sizeof_field(struct cpdma_chan_stats, m), \
  74. offsetof(struct cpdma_chan_stats, m)
  75. #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
  76. sizeof_field(struct cpdma_chan_stats, m), \
  77. offsetof(struct cpdma_chan_stats, m)
  78. static const struct cpsw_stats cpsw_gstrings_stats[] = {
  79. { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
  80. { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
  81. { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
  82. { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
  83. { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
  84. { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
  85. { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
  86. { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
  87. { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
  88. { "Rx Fragments", CPSW_STAT(rxfragments) },
  89. { "Rx Octets", CPSW_STAT(rxoctets) },
  90. { "Good Tx Frames", CPSW_STAT(txgoodframes) },
  91. { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
  92. { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
  93. { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
  94. { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
  95. { "Collisions", CPSW_STAT(txcollisionframes) },
  96. { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
  97. { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
  98. { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
  99. { "Late Collisions", CPSW_STAT(txlatecollisions) },
  100. { "Tx Underrun", CPSW_STAT(txunderrun) },
  101. { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
  102. { "Tx Octets", CPSW_STAT(txoctets) },
  103. { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
  104. { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
  105. { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
  106. { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
  107. { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
  108. { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
  109. { "Net Octets", CPSW_STAT(netoctets) },
  110. { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
  111. { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
  112. { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
  113. };
  114. static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
  115. { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
  116. { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
  117. { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
  118. { "misqueued", CPDMA_RX_STAT(misqueued) },
  119. { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
  120. { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
  121. { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
  122. { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
  123. { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
  124. { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
  125. { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
  126. { "requeue", CPDMA_RX_STAT(requeue) },
  127. { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
  128. };
  129. #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
  130. #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
  131. u32 cpsw_get_msglevel(struct net_device *ndev)
  132. {
  133. struct cpsw_priv *priv = netdev_priv(ndev);
  134. return priv->msg_enable;
  135. }
  136. void cpsw_set_msglevel(struct net_device *ndev, u32 value)
  137. {
  138. struct cpsw_priv *priv = netdev_priv(ndev);
  139. priv->msg_enable = value;
  140. }
  141. int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
  142. struct kernel_ethtool_coalesce *kernel_coal,
  143. struct netlink_ext_ack *extack)
  144. {
  145. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  146. coal->rx_coalesce_usecs = cpsw->coal_intvl;
  147. return 0;
  148. }
  149. int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
  150. struct kernel_ethtool_coalesce *kernel_coal,
  151. struct netlink_ext_ack *extack)
  152. {
  153. struct cpsw_priv *priv = netdev_priv(ndev);
  154. u32 int_ctrl;
  155. u32 num_interrupts = 0;
  156. u32 prescale = 0;
  157. u32 addnl_dvdr = 1;
  158. u32 coal_intvl = 0;
  159. struct cpsw_common *cpsw = priv->cpsw;
  160. coal_intvl = coal->rx_coalesce_usecs;
  161. int_ctrl = readl(&cpsw->wr_regs->int_control);
  162. prescale = cpsw->bus_freq_mhz * 4;
  163. if (!coal->rx_coalesce_usecs) {
  164. int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
  165. goto update_return;
  166. }
  167. if (coal_intvl < CPSW_CMINTMIN_INTVL)
  168. coal_intvl = CPSW_CMINTMIN_INTVL;
  169. if (coal_intvl > CPSW_CMINTMAX_INTVL) {
  170. /* Interrupt pacer works with 4us Pulse, we can
  171. * throttle further by dilating the 4us pulse.
  172. */
  173. addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
  174. if (addnl_dvdr > 1) {
  175. prescale *= addnl_dvdr;
  176. if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
  177. coal_intvl = (CPSW_CMINTMAX_INTVL
  178. * addnl_dvdr);
  179. } else {
  180. addnl_dvdr = 1;
  181. coal_intvl = CPSW_CMINTMAX_INTVL;
  182. }
  183. }
  184. num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
  185. writel(num_interrupts, &cpsw->wr_regs->rx_imax);
  186. writel(num_interrupts, &cpsw->wr_regs->tx_imax);
  187. int_ctrl |= CPSW_INTPACEEN;
  188. int_ctrl &= (~CPSW_INTPRESCALE_MASK);
  189. int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
  190. update_return:
  191. writel(int_ctrl, &cpsw->wr_regs->int_control);
  192. cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
  193. cpsw->coal_intvl = coal_intvl;
  194. return 0;
  195. }
  196. int cpsw_get_sset_count(struct net_device *ndev, int sset)
  197. {
  198. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  199. switch (sset) {
  200. case ETH_SS_STATS:
  201. return (CPSW_STATS_COMMON_LEN +
  202. (cpsw->rx_ch_num + cpsw->tx_ch_num) *
  203. CPSW_STATS_CH_LEN);
  204. default:
  205. return -EOPNOTSUPP;
  206. }
  207. }
  208. static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
  209. {
  210. int ch_stats_len;
  211. int line;
  212. int i;
  213. ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
  214. for (i = 0; i < ch_stats_len; i++) {
  215. line = i % CPSW_STATS_CH_LEN;
  216. snprintf(*p, ETH_GSTRING_LEN,
  217. "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
  218. (long)(i / CPSW_STATS_CH_LEN),
  219. cpsw_gstrings_ch_stats[line].stat_string);
  220. *p += ETH_GSTRING_LEN;
  221. }
  222. }
  223. void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
  224. {
  225. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  226. u8 *p = data;
  227. int i;
  228. switch (stringset) {
  229. case ETH_SS_STATS:
  230. for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
  231. memcpy(p, cpsw_gstrings_stats[i].stat_string,
  232. ETH_GSTRING_LEN);
  233. p += ETH_GSTRING_LEN;
  234. }
  235. cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
  236. cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
  237. break;
  238. }
  239. }
  240. void cpsw_get_ethtool_stats(struct net_device *ndev,
  241. struct ethtool_stats *stats, u64 *data)
  242. {
  243. u8 *p;
  244. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  245. struct cpdma_chan_stats ch_stats;
  246. int i, l, ch;
  247. /* Collect Davinci CPDMA stats for Rx and Tx Channel */
  248. for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
  249. data[l] = readl(cpsw->hw_stats +
  250. cpsw_gstrings_stats[l].stat_offset);
  251. for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
  252. cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
  253. for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
  254. p = (u8 *)&ch_stats +
  255. cpsw_gstrings_ch_stats[i].stat_offset;
  256. data[l] = *(u32 *)p;
  257. }
  258. }
  259. for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
  260. cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
  261. for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
  262. p = (u8 *)&ch_stats +
  263. cpsw_gstrings_ch_stats[i].stat_offset;
  264. data[l] = *(u32 *)p;
  265. }
  266. }
  267. }
  268. void cpsw_get_pauseparam(struct net_device *ndev,
  269. struct ethtool_pauseparam *pause)
  270. {
  271. struct cpsw_priv *priv = netdev_priv(ndev);
  272. pause->autoneg = AUTONEG_DISABLE;
  273. pause->rx_pause = priv->rx_pause ? true : false;
  274. pause->tx_pause = priv->tx_pause ? true : false;
  275. }
  276. void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
  277. {
  278. struct cpsw_priv *priv = netdev_priv(ndev);
  279. struct cpsw_common *cpsw = priv->cpsw;
  280. int slave_no = cpsw_slave_index(cpsw, priv);
  281. wol->supported = 0;
  282. wol->wolopts = 0;
  283. if (cpsw->slaves[slave_no].phy)
  284. phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
  285. }
  286. int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
  287. {
  288. struct cpsw_priv *priv = netdev_priv(ndev);
  289. struct cpsw_common *cpsw = priv->cpsw;
  290. int slave_no = cpsw_slave_index(cpsw, priv);
  291. if (cpsw->slaves[slave_no].phy)
  292. return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
  293. else
  294. return -EOPNOTSUPP;
  295. }
  296. int cpsw_get_regs_len(struct net_device *ndev)
  297. {
  298. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  299. return cpsw_ale_get_num_entries(cpsw->ale) *
  300. ALE_ENTRY_WORDS * sizeof(u32);
  301. }
  302. void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p)
  303. {
  304. u32 *reg = p;
  305. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  306. /* update CPSW IP version */
  307. regs->version = cpsw->version;
  308. cpsw_ale_dump(cpsw->ale, reg);
  309. }
  310. int cpsw_ethtool_op_begin(struct net_device *ndev)
  311. {
  312. struct cpsw_priv *priv = netdev_priv(ndev);
  313. struct cpsw_common *cpsw = priv->cpsw;
  314. int ret;
  315. ret = pm_runtime_resume_and_get(cpsw->dev);
  316. if (ret < 0)
  317. cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
  318. return ret;
  319. }
  320. void cpsw_ethtool_op_complete(struct net_device *ndev)
  321. {
  322. struct cpsw_priv *priv = netdev_priv(ndev);
  323. int ret;
  324. ret = pm_runtime_put(priv->cpsw->dev);
  325. if (ret < 0)
  326. cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
  327. }
  328. void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch)
  329. {
  330. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  331. ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
  332. ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
  333. ch->max_combined = 0;
  334. ch->max_other = 0;
  335. ch->other_count = 0;
  336. ch->rx_count = cpsw->rx_ch_num;
  337. ch->tx_count = cpsw->tx_ch_num;
  338. ch->combined_count = 0;
  339. }
  340. int cpsw_get_link_ksettings(struct net_device *ndev,
  341. struct ethtool_link_ksettings *ecmd)
  342. {
  343. struct cpsw_priv *priv = netdev_priv(ndev);
  344. struct cpsw_common *cpsw = priv->cpsw;
  345. int slave_no = cpsw_slave_index(cpsw, priv);
  346. if (!cpsw->slaves[slave_no].phy)
  347. return -EOPNOTSUPP;
  348. phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
  349. return 0;
  350. }
  351. int cpsw_set_link_ksettings(struct net_device *ndev,
  352. const struct ethtool_link_ksettings *ecmd)
  353. {
  354. struct cpsw_priv *priv = netdev_priv(ndev);
  355. struct cpsw_common *cpsw = priv->cpsw;
  356. int slave_no = cpsw_slave_index(cpsw, priv);
  357. if (!cpsw->slaves[slave_no].phy)
  358. return -EOPNOTSUPP;
  359. return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, ecmd);
  360. }
  361. int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
  362. {
  363. struct cpsw_priv *priv = netdev_priv(ndev);
  364. struct cpsw_common *cpsw = priv->cpsw;
  365. int slave_no = cpsw_slave_index(cpsw, priv);
  366. if (cpsw->slaves[slave_no].phy)
  367. return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
  368. else
  369. return -EOPNOTSUPP;
  370. }
  371. int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
  372. {
  373. struct cpsw_priv *priv = netdev_priv(ndev);
  374. struct cpsw_common *cpsw = priv->cpsw;
  375. int slave_no = cpsw_slave_index(cpsw, priv);
  376. if (cpsw->slaves[slave_no].phy)
  377. return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
  378. else
  379. return -EOPNOTSUPP;
  380. }
  381. int cpsw_nway_reset(struct net_device *ndev)
  382. {
  383. struct cpsw_priv *priv = netdev_priv(ndev);
  384. struct cpsw_common *cpsw = priv->cpsw;
  385. int slave_no = cpsw_slave_index(cpsw, priv);
  386. if (cpsw->slaves[slave_no].phy)
  387. return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
  388. else
  389. return -EOPNOTSUPP;
  390. }
  391. static void cpsw_suspend_data_pass(struct net_device *ndev)
  392. {
  393. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  394. int i;
  395. /* Disable NAPI scheduling */
  396. cpsw_intr_disable(cpsw);
  397. /* Stop all transmit queues for every network device.
  398. */
  399. for (i = 0; i < cpsw->data.slaves; i++) {
  400. ndev = cpsw->slaves[i].ndev;
  401. if (!(ndev && netif_running(ndev)))
  402. continue;
  403. netif_tx_stop_all_queues(ndev);
  404. /* Barrier, so that stop_queue visible to other cpus */
  405. smp_mb__after_atomic();
  406. }
  407. /* Handle rest of tx packets and stop cpdma channels */
  408. cpdma_ctlr_stop(cpsw->dma);
  409. }
  410. static int cpsw_resume_data_pass(struct net_device *ndev)
  411. {
  412. struct cpsw_priv *priv = netdev_priv(ndev);
  413. struct cpsw_common *cpsw = priv->cpsw;
  414. int i, ret;
  415. /* After this receive is started */
  416. if (cpsw->usage_count) {
  417. ret = cpsw_fill_rx_channels(priv);
  418. if (ret)
  419. return ret;
  420. cpdma_ctlr_start(cpsw->dma);
  421. cpsw_intr_enable(cpsw);
  422. }
  423. /* Resume transmit for every affected interface */
  424. for (i = 0; i < cpsw->data.slaves; i++) {
  425. ndev = cpsw->slaves[i].ndev;
  426. if (ndev && netif_running(ndev))
  427. netif_tx_start_all_queues(ndev);
  428. }
  429. return 0;
  430. }
  431. static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
  432. struct ethtool_channels *ch)
  433. {
  434. if (cpsw->quirk_irq) {
  435. dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
  436. return -EOPNOTSUPP;
  437. }
  438. if (ch->combined_count)
  439. return -EINVAL;
  440. /* verify we have at least one channel in each direction */
  441. if (!ch->rx_count || !ch->tx_count)
  442. return -EINVAL;
  443. if (ch->rx_count > cpsw->data.channels ||
  444. ch->tx_count > cpsw->data.channels)
  445. return -EINVAL;
  446. return 0;
  447. }
  448. static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx,
  449. cpdma_handler_fn rx_handler)
  450. {
  451. struct cpsw_common *cpsw = priv->cpsw;
  452. void (*handler)(void *, int, int);
  453. struct netdev_queue *queue;
  454. struct cpsw_vector *vec;
  455. int ret, *ch, vch;
  456. if (rx) {
  457. ch = &cpsw->rx_ch_num;
  458. vec = cpsw->rxv;
  459. handler = rx_handler;
  460. } else {
  461. ch = &cpsw->tx_ch_num;
  462. vec = cpsw->txv;
  463. handler = cpsw_tx_handler;
  464. }
  465. while (*ch < ch_num) {
  466. vch = rx ? *ch : 7 - *ch;
  467. vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
  468. queue = netdev_get_tx_queue(priv->ndev, *ch);
  469. queue->tx_maxrate = 0;
  470. if (IS_ERR(vec[*ch].ch))
  471. return PTR_ERR(vec[*ch].ch);
  472. if (!vec[*ch].ch)
  473. return -EINVAL;
  474. cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
  475. (rx ? "rx" : "tx"));
  476. (*ch)++;
  477. }
  478. while (*ch > ch_num) {
  479. (*ch)--;
  480. ret = cpdma_chan_destroy(vec[*ch].ch);
  481. if (ret)
  482. return ret;
  483. cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
  484. (rx ? "rx" : "tx"));
  485. }
  486. return 0;
  487. }
  488. static void cpsw_fail(struct cpsw_common *cpsw)
  489. {
  490. struct net_device *ndev;
  491. int i;
  492. for (i = 0; i < cpsw->data.slaves; i++) {
  493. ndev = cpsw->slaves[i].ndev;
  494. if (ndev)
  495. dev_close(ndev);
  496. }
  497. }
  498. int cpsw_set_channels_common(struct net_device *ndev,
  499. struct ethtool_channels *chs,
  500. cpdma_handler_fn rx_handler)
  501. {
  502. struct cpsw_priv *priv = netdev_priv(ndev);
  503. struct cpsw_common *cpsw = priv->cpsw;
  504. struct net_device *sl_ndev;
  505. int i, new_pools, ret;
  506. ret = cpsw_check_ch_settings(cpsw, chs);
  507. if (ret < 0)
  508. return ret;
  509. cpsw_suspend_data_pass(ndev);
  510. new_pools = (chs->rx_count != cpsw->rx_ch_num) && cpsw->usage_count;
  511. ret = cpsw_update_channels_res(priv, chs->rx_count, 1, rx_handler);
  512. if (ret)
  513. goto err;
  514. ret = cpsw_update_channels_res(priv, chs->tx_count, 0, rx_handler);
  515. if (ret)
  516. goto err;
  517. for (i = 0; i < cpsw->data.slaves; i++) {
  518. sl_ndev = cpsw->slaves[i].ndev;
  519. if (!(sl_ndev && netif_running(sl_ndev)))
  520. continue;
  521. /* Inform stack about new count of queues */
  522. ret = netif_set_real_num_tx_queues(sl_ndev, cpsw->tx_ch_num);
  523. if (ret) {
  524. dev_err(priv->dev, "cannot set real number of tx queues\n");
  525. goto err;
  526. }
  527. ret = netif_set_real_num_rx_queues(sl_ndev, cpsw->rx_ch_num);
  528. if (ret) {
  529. dev_err(priv->dev, "cannot set real number of rx queues\n");
  530. goto err;
  531. }
  532. }
  533. cpsw_split_res(cpsw);
  534. if (new_pools) {
  535. cpsw_destroy_xdp_rxqs(cpsw);
  536. ret = cpsw_create_xdp_rxqs(cpsw);
  537. if (ret)
  538. goto err;
  539. }
  540. ret = cpsw_resume_data_pass(ndev);
  541. if (!ret)
  542. return 0;
  543. err:
  544. dev_err(priv->dev, "cannot update channels number, closing device\n");
  545. cpsw_fail(cpsw);
  546. return ret;
  547. }
  548. void cpsw_get_ringparam(struct net_device *ndev,
  549. struct ethtool_ringparam *ering,
  550. struct kernel_ethtool_ringparam *kernel_ering,
  551. struct netlink_ext_ack *extack)
  552. {
  553. struct cpsw_priv *priv = netdev_priv(ndev);
  554. struct cpsw_common *cpsw = priv->cpsw;
  555. /* not supported */
  556. ering->tx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES;
  557. ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
  558. ering->rx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES;
  559. ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
  560. }
  561. int cpsw_set_ringparam(struct net_device *ndev,
  562. struct ethtool_ringparam *ering,
  563. struct kernel_ethtool_ringparam *kernel_ering,
  564. struct netlink_ext_ack *extack)
  565. {
  566. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  567. int descs_num, ret;
  568. /* ignore ering->tx_pending - only rx_pending adjustment is supported */
  569. if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
  570. ering->rx_pending < CPSW_MAX_QUEUES ||
  571. ering->rx_pending > (cpsw->descs_pool_size - CPSW_MAX_QUEUES))
  572. return -EINVAL;
  573. descs_num = cpdma_get_num_rx_descs(cpsw->dma);
  574. if (ering->rx_pending == descs_num)
  575. return 0;
  576. cpsw_suspend_data_pass(ndev);
  577. ret = cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
  578. if (ret) {
  579. if (cpsw_resume_data_pass(ndev))
  580. goto err;
  581. return ret;
  582. }
  583. if (cpsw->usage_count) {
  584. cpsw_destroy_xdp_rxqs(cpsw);
  585. ret = cpsw_create_xdp_rxqs(cpsw);
  586. if (ret)
  587. goto err;
  588. }
  589. ret = cpsw_resume_data_pass(ndev);
  590. if (!ret)
  591. return 0;
  592. err:
  593. cpdma_set_num_rx_descs(cpsw->dma, descs_num);
  594. dev_err(cpsw->dev, "cannot set ring params, closing device\n");
  595. cpsw_fail(cpsw);
  596. return ret;
  597. }
  598. #if IS_ENABLED(CONFIG_TI_CPTS)
  599. int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info)
  600. {
  601. struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
  602. info->so_timestamping =
  603. SOF_TIMESTAMPING_TX_HARDWARE |
  604. SOF_TIMESTAMPING_TX_SOFTWARE |
  605. SOF_TIMESTAMPING_RX_HARDWARE |
  606. SOF_TIMESTAMPING_RX_SOFTWARE |
  607. SOF_TIMESTAMPING_SOFTWARE |
  608. SOF_TIMESTAMPING_RAW_HARDWARE;
  609. info->phc_index = cpsw->cpts->phc_index;
  610. info->tx_types =
  611. (1 << HWTSTAMP_TX_OFF) |
  612. (1 << HWTSTAMP_TX_ON);
  613. info->rx_filters =
  614. (1 << HWTSTAMP_FILTER_NONE) |
  615. (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
  616. return 0;
  617. }
  618. #else
  619. int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info)
  620. {
  621. info->so_timestamping =
  622. SOF_TIMESTAMPING_TX_SOFTWARE |
  623. SOF_TIMESTAMPING_RX_SOFTWARE |
  624. SOF_TIMESTAMPING_SOFTWARE;
  625. info->phc_index = -1;
  626. info->tx_types = 0;
  627. info->rx_filters = 0;
  628. return 0;
  629. }
  630. #endif