android_kernel_samsung_sm8650_ksu/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-serdes.h

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */

#ifndef	_DWMAC_QCOM_SERDES_H
#define	_DWMAC_QCOM_SERDES_H

#include <linux/ipc_logging.h>
#include <net/addrconf.h>
#include <linux/uaccess.h>

#include "stmmac.h"
#include "dwmac-qcom-ethqos.h"

#define QSERDES_QMP_PLL	0x0
#define QSERDES_COM_ATB_SEL1	(QSERDES_QMP_PLL + 0x0)
#define QSERDES_COM_ATB_SEL2	(QSERDES_QMP_PLL + 0x4)
#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN	(QSERDES_QMP_PLL + 0x44)
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM	(QSERDES_QMP_PLL + 0x90)
#define SGMII_PHY_0_QSERDES_COM_BG_TIMER	(QSERDES_QMP_PLL + 0xBC)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	(QSERDES_QMP_PLL + 0x58)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	(QSERDES_QMP_PLL + 0x1B4)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	(QSERDES_QMP_PLL + 0x5C)
#define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	(QSERDES_QMP_PLL + 0x1B8)
#define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL_1	(QSERDES_QMP_PLL + 0x19C)
#define QSERDES_COM_C_READY_STATUS	(QSERDES_QMP_PLL + 0x1F8)
#define QSERDES_COM_CLK_ENABLE1	(QSERDES_QMP_PLL + 0x48)
#define QSERDES_COM_CLK_EP_DIV_MODE0	(QSERDES_QMP_PLL + 0x6C)
#define QSERDES_COM_CLK_EP_DIV_MODE1	(QSERDES_QMP_PLL + 0x70)
#define QSERDES_COM_CLK_SELECT	(QSERDES_QMP_PLL + 0x154)
#define QSERDES_COM_CML_SYSCLK_SEL	(QSERDES_QMP_PLL + 0x98)
#define QSERDES_COM_CMN_CONFIG_1	(QSERDES_QMP_PLL + 0x174)
#define QSERDES_COM_CMN_IETRIM	(QSERDES_QMP_PLL + 0x5C)
#define QSERDES_COM_CMN_IPTRIM	(QSERDES_QMP_PLL + 0x60)
#define QSERDES_COM_CMN_MISC1	(QSERDES_QMP_PLL + 0x19C)
#define QSERDES_COM_CMN_MODE	(QSERDES_QMP_PLL + 0x1A0)
#define QSERDES_COM_CMN_MODE_CONTD	(QSERDES_QMP_PLL + 0x1A4)
#define QSERDES_COM_CMN_RATE_OVERRIDE	(QSERDES_QMP_PLL + 0x180)
#define QSERDES_COM_CMN_STATUS	(QSERDES_QMP_PLL + 0x1D0)
#define QSERDES_COM_CORE_CLK_EN	(QSERDES_QMP_PLL + 0x170)
#define QSERDES_COM_CORECLK_DIV_MODE0	(QSERDES_QMP_PLL + 0x07C)
#define QSERDES_COM_CORECLK_DIV_MODE1	(QSERDES_QMP_PLL + 0x16C)
#define QSERDES_COM_CP_CTRL_MODE0	(QSERDES_QMP_PLL + 0x70)
#define QSERDES_COM_CP_CTRL_MODE1	(QSERDES_QMP_PLL + 0x78)
#define QSERDES_COM_DEBUG_BUS0	(QSERDES_QMP_PLL + 0x188)
#define QSERDES_COM_DEBUG_BUS1	(QSERDES_QMP_PLL + 0x18C)
#define QSERDES_COM_DEBUG_BUS2	(QSERDES_QMP_PLL + 0x190)
#define QSERDES_COM_DEBUG_BUS3	(QSERDES_QMP_PLL + 0x194)
#define QSERDES_COM_DEBUG_BUS_SEL	(QSERDES_QMP_PLL + 0x198)
#define QSERDES_COM_DEC_START_MODE0	(QSERDES_QMP_PLL + 0x88)
#define QSERDES_COM_DEC_START_MODE1	(QSERDES_QMP_PLL + 0xC4)
#define QSERDES_COM_DEC_START_MSB_MODE0	(QSERDES_QMP_PLL + 0xC0)
#define QSERDES_COM_DEC_START_MSB_MODE1	(QSERDES_QMP_PLL + 0xC8)
#define QSERDES_COM_DIV_FRAC_START1_MODE0	(QSERDES_QMP_PLL + 0x90)
#define QSERDES_COM_DIV_FRAC_START1_MODE1	(QSERDES_QMP_PLL + 0xD8)
#define QSERDES_COM_DIV_FRAC_START2_MODE0	(QSERDES_QMP_PLL + 0x94)
#define QSERDES_COM_DIV_FRAC_START2_MODE1	(QSERDES_QMP_PLL + 0xDC)
#define QSERDES_COM_DIV_FRAC_START3_MODE0	(QSERDES_QMP_PLL + 0x98)
#define QSERDES_COM_DIV_FRAC_START3_MODE1	(QSERDES_QMP_PLL + 0xE0)
#define QSERDES_COM_EP_CLOCK_DETECT_CTRL	(QSERDES_QMP_PLL + 0x64)
#define QSERDES_COM_FREQ_UPDATE	(QSERDES_QMP_PLL + 0x8)
#define QSERDES_COM_HSCLK_SEL_1	(QSERDES_QMP_PLL + 0x3C)
#define QSERDES_COM_HSCLK_HS_SWITCH_SEL_1 (QSERDES_QMP_PLL + 0x9C)
#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS	(QSERDES_QMP_PLL + 0x160)
#define QSERDES_COM_INTEGLOOP_EN	(QSERDES_QMP_PLL + 0xE8)
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0	(QSERDES_QMP_PLL + 0xEC)
#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1	(QSERDES_QMP_PLL + 0xF4)
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0	(QSERDES_QMP_PLL + 0xF0)
#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1	(QSERDES_QMP_PLL + 0xF8)
#define QSERDES_COM_INTEGLOOP_INITVAL	(QSERDES_QMP_PLL + 0xE4)
#define QSERDES_COM_INTEGLOOP_P_PATH_GAIN0	(QSERDES_QMP_PLL + 0xFC)
#define QSERDES_COM_INTEGLOOP_P_PATH_GAIN1	(QSERDES_QMP_PLL + 0x100)
#define QSERDES_COM_LOCK_CMP1_MODE0	(QSERDES_QMP_PLL + 0x80)
#define QSERDES_COM_LOCK_CMP1_MODE1	(QSERDES_QMP_PLL + 0xB4)
#define QSERDES_COM_LOCK_CMP2_MODE0	(QSERDES_QMP_PLL + 0x84)
#define QSERDES_COM_LOCK_CMP2_MODE1	(QSERDES_QMP_PLL + 0xB8)
#define QSERDES_COM_LOCK_CMP_CFG	(QSERDES_QMP_PLL + 0xA8)
#define QSERDES_COM_LOCK_CMP_EN	(QSERDES_QMP_PLL + 0xA4)
#define QSERDES_COM_MODE_OPERATION_STATUS	(QSERDES_QMP_PLL + 0x1C4)
#define QSERDES_COM_PLL_ANALOG	(QSERDES_QMP_PLL + 0x164)
#define QSERDES_COM_PLL_CCTRL_MODE0	(QSERDES_QMP_PLL + 0x78)
#define QSERDES_COM_PLL_CCTRL_MODE1	(QSERDES_QMP_PLL + 0x88)
#define QSERDES_COM_PLL_CNTRL	(QSERDES_QMP_PLL + 0x8C)
#define QSERDES_COM_PLL_EN	(QSERDES_QMP_PLL + 0x54)
#define SGMII_PHY_0_QSERDES_COM_PLL_IVCO	(QSERDES_QMP_PLL + 0xF4)
#define QSERDES_COM_PLL_RCTRL_MODE0	(QSERDES_QMP_PLL + 0x74)
#define QSERDES_COM_PLL_RCTRL_MODE1	(QSERDES_QMP_PLL + 0x80)
#define QSERDES_COM_PLLCAL_CODE1_STATUS	(QSERDES_QMP_PLL + 0x14C)
#define QSERDES_COM_PLLCAL_CODE2_STATUS	(QSERDES_QMP_PLL + 0x150)
#define QSERDES_COM_POST_DIV	(QSERDES_QMP_PLL + 0x3C)
#define QSERDES_COM_POST_DIV_MUX	(QSERDES_QMP_PLL + 0x40)
#define QSERDES_COM_RESERVED_1	(QSERDES_QMP_PLL + 0x1C0)
#define QSERDES_COM_RESET_SM_STATUS	(QSERDES_QMP_PLL + 0x144)
#define QSERDES_COM_RESETSM_CNTRL	(QSERDES_QMP_PLL + 0x9C)
#define QSERDES_COM_RESETSM_CNTRL2	(QSERDES_QMP_PLL + 0xA0)
#define QSERDES_COM_RESTRIM_CODE_STATUS	(QSERDES_QMP_PLL + 0x148)
#define QSERDES_COM_SSC_ADJ_PER1	(QSERDES_QMP_PLL + 0x14)
#define QSERDES_COM_SSC_ADJ_PER2	(QSERDES_QMP_PLL + 0x18)
#define QSERDES_COM_SSC_EN_CENTER	(QSERDES_QMP_PLL + 0x10)
#define QSERDES_COM_SSC_PER1	(QSERDES_QMP_PLL + 0x1C)
#define QSERDES_COM_SSC_PER2	(QSERDES_QMP_PLL + 0x20)
#define QSERDES_COM_SSC_STEP_SIZE1_MODE0	(QSERDES_QMP_PLL + 0x24)
#define QSERDES_COM_SSC_STEP_SIZE1_MODE1	(QSERDES_QMP_PLL + 0x30)
#define QSERDES_COM_SSC_STEP_SIZE2_MODE0	(QSERDES_QMP_PLL + 0x28)
#define QSERDES_COM_SSC_STEP_SIZE2_MODE1	(QSERDES_QMP_PLL + 0x34)
#define QSERDES_COM_SSC_STEP_SIZE3_MODE0	(QSERDES_QMP_PLL + 0x2C)
#define QSERDES_COM_SSC_STEP_SIZE3_MODE1	(QSERDES_QMP_PLL + 0x38)
#define QSERDES_COM_SVS_MODE_CLK_SEL	(QSERDES_QMP_PLL + 0x184)
#define QSERDES_COM_SW_RESET	(QSERDES_QMP_PLL + 0x170)
#define QSERDES_COM_SYS_CLK_CTRL	(QSERDES_QMP_PLL + 0x4C)
#define QSERDES_COM_SYSCLK_BUF_ENABLE	(QSERDES_QMP_PLL + 0x50)
#define QSERDES_COM_SYSCLK_DET_COMP_STATUS	(QSERDES_QMP_PLL + 0x68)
#define QSERDES_COM_SYSCLK_EN_SEL	(QSERDES_QMP_PLL + 0x110)
#define QSERDES_COM_VCO_DC_LEVEL_CTRL	(QSERDES_QMP_PLL + 0x1A8)
#define QSERDES_COM_VCO_TUNE1_MODE0	(QSERDES_QMP_PLL + 0xA8)
#define QSERDES_COM_VCO_TUNE1_MODE1	(QSERDES_QMP_PLL + 0x118)
#define QSERDES_COM_VCO_TUNE2_MODE0	(QSERDES_QMP_PLL + 0xAC)
#define QSERDES_COM_VCO_TUNE2_MODE1	(QSERDES_QMP_PLL + 0x11C)
#define QSERDES_COM_VCO_TUNE_CTRL	(QSERDES_QMP_PLL + 0x108)
#define QSERDES_COM_VCO_TUNE_INITVAL1	(QSERDES_QMP_PLL + 0x120)
#define QSERDES_COM_VCO_TUNE_INITVAL2	(QSERDES_QMP_PLL + 0x148)
#define QSERDES_COM_VCO_TUNE_MAP	(QSERDES_QMP_PLL + 0x10C)
#define QSERDES_COM_VCO_TUNE_MAXVAL1	(QSERDES_QMP_PLL + 0x130)
#define QSERDES_COM_VCO_TUNE_MAXVAL2	(QSERDES_QMP_PLL + 0x134)
#define QSERDES_COM_VCO_TUNE_MINVAL1	(QSERDES_QMP_PLL + 0x128)
#define QSERDES_COM_VCO_TUNE_MINVAL2	(QSERDES_QMP_PLL + 0x12C)
#define QSERDES_COM_VCO_TUNE_TIMER1	(QSERDES_QMP_PLL + 0x138)
#define QSERDES_COM_VCO_TUNE_TIMER2	(QSERDES_QMP_PLL + 0x13C)
#define QSERDES_COM_VCOCAL_DEADMAN_CTRL	(QSERDES_QMP_PLL + 0x104)

#define QSERDES_RX	0x600
#define QSERDES_RX_UCDR_FO_GAIN_HALF	(QSERDES_RX + 0x0)
#define QSERDES_RX_UCDR_FO_GAIN_QUARTER	(QSERDES_RX + 0x4)
#define QSERDES_RX0_UCDR_FO_GAIN	(QSERDES_RX + 0x08)
#define QSERDES_RX_UCDR_SO_GAIN_HALF	(QSERDES_RX + 0xC)
#define QSERDES_RX_UCDR_SO_GAIN_QUARTER	(QSERDES_RX + 0x10)
#define QSERDES_RX0_UCDR_SO_GAIN	(QSERDES_RX + 0x14)
#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF	(QSERDES_RX + 0x18)
#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER	(QSERDES_RX + 0x1C)
#define QSERDES_RX_UCDR_SVS_FO_GAIN	(QSERDES_RX + 0x20)
#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF	(QSERDES_RX + 0x24)
#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER	(QSERDES_RX + 0x28)
#define QSERDES_RX_UCDR_SVS_SO_GAIN	(QSERDES_RX + 0x2C)
#define QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN	(QSERDES_RX + 0x30)
#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE	(QSERDES_RX + 0x34)
#define QSERDES_RX_UCDR_FO_TO_SO_DELAY	(QSERDES_RX + 0x38)
#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW	(QSERDES_RX + 0x3C)
#define QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH	(QSERDES_RX + 0x40)
#define QSERDES_RX0_UCDR_PI_CONTROLS	(QSERDES_RX + 0x44)
#define QSERDES_RX0_UCDR_PI_CTRL2	(QSERDES_RX + 0x48)
#define QSERDES_RX_UCDR_SB2_THRESH1	(QSERDES_RX + 0x4C)
#define QSERDES_RX_UCDR_SB2_THRESH2	(QSERDES_RX + 0x50)
#define QSERDES_RX_UCDR_SB2_GAIN1	(QSERDES_RX + 0x54)
#define QSERDES_RX_UCDR_SB2_GAIN2	(QSERDES_RX + 0x58)
#define QSERDES_RX_AUX_CONTROL	(QSERDES_RX + 0x5C)
#define QSERDES_RX_AUX_DATA_TCOARSE_TFINE	(QSERDES_RX + 0x60)
#define QSERDES_RX_RCLK_AUXDATA_SEL	(QSERDES_RX + 0x64)
#define QSERDES_RX_AC_JTAG_ENABLE	(QSERDES_RX + 0x68)
#define QSERDES_RX_AC_JTAG_INITP	(QSERDES_RX + 0x6C)
#define QSERDES_RX_AC_JTAG_INITN	(QSERDES_RX + 0x70)
#define QSERDES_RX_AC_JTAG_LVL	(QSERDES_RX + 0x74)
#define QSERDES_RX_AC_JTAG_MODE	(QSERDES_RX + 0x78)
#define QSERDES_RX_AC_JTAG_RESET	(QSERDES_RX + 0x7C)
#define QSERDES_RX0_RX_TERM_BW	(QSERDES_RX + 0x80)
#define QSERDES_RX_RX_RCVR_IQ_EN	(QSERDES_RX + 0x84)
#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS	(QSERDES_RX + 0x88)
#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS	(QSERDES_RX + 0x8C)
#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS	(QSERDES_RX + 0x90)
#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS	(QSERDES_RX + 0x94)
#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS	(QSERDES_RX + 0x98)
#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS	(QSERDES_RX + 0x9C)
#define QSERDES_RX_RX_IDAC_EN	(QSERDES_RX + 0xA0)
#define QSERDES_RX_RX_IDAC_ENABLES	(QSERDES_RX + 0xA4)
#define QSERDES_RX_RX_IDAC_SIGN	(QSERDES_RX + 0xA8)
#define QSERDES_RX_RX_HIGHZ_HIGHRATE	(QSERDES_RX + 0xAC)
#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	(QSERDES_RX + 0xB0)
#define QSERDES_RX_DFE_1	(QSERDES_RX + 0xB4)
#define QSERDES_RX_DFE_2	(QSERDES_RX + 0xB8)
#define QSERDES_RX_DFE_3	(QSERDES_RX + 0xBC)
#define QSERDES_RX_DFE_4	(QSERDES_RX + 0xC0)
#define QSERDES_RX_TX_ADAPT_PRE_THRESH1	(QSERDES_RX + 0xC4)
#define QSERDES_RX_TX_ADAPT_PRE_THRESH2	(QSERDES_RX + 0xC8)
#define QSERDES_RX_TX_ADAPT_POST_THRESH	(QSERDES_RX + 0xCC)
#define QSERDES_RX_TX_ADAPT_MAIN_THRESH	(QSERDES_RX + 0xD0)
#define QSERDES_RX_VGA_CAL_CNTRL1	(QSERDES_RX + 0xD4)
#define QSERDES_RX0_VGA_CAL_CNTRL2	(QSERDES_RX + 0xD8)
#define QSERDES_RX0_GM_CAL	(QSERDES_RX + 0xDC)
#define QSERDES_RX_RX_VGA_GAIN2_LSB	(QSERDES_RX + 0xE0)
#define QSERDES_RX_RX_VGA_GAIN2_MSB	(QSERDES_RX + 0xE4)
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1	(QSERDES_RX + 0xE8)
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2	(QSERDES_RX + 0xEC)
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3	(QSERDES_RX + 0xF0)
#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4	(QSERDES_RX + 0xF4)
#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW	(QSERDES_RX + 0xF8)
#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH	(QSERDES_RX + 0xFC)
#define QSERDES_RX0_RX_IDAC_MEASURE_TIME	(QSERDES_RX + 0x100)
#define QSERDES_RX_RX_IDAC_ACCUMULATOR	(QSERDES_RX + 0x104)
#define QSERDES_RX_RX_EQ_OFFSET_LSB	(QSERDES_RX + 0x108)
#define QSERDES_RX_RX_EQ_OFFSET_MSB	(QSERDES_RX + 0x10C)
#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1	(QSERDES_RX + 0x110)
#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2	(QSERDES_RX + 0x114)
#define QSERDES_RX_SIGDET_ENABLES	(QSERDES_RX + 0x118)
#define QSERDES_RX0_SIGDET_CNTRL	(QSERDES_RX + 0x11C)
#define QSERDES_RX0_SIGDET_CAL_CTRL1	(QSERDES_RX + 0x1E4)
#define QSERDES_RX_SIGDET_LVL	(QSERDES_RX + 0x120)
#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL	(QSERDES_RX + 0x124)
#define QSERDES_RX0_RX_BAND	(QSERDES_RX + 0x128)
#define QSERDES_RX_CDR_FREEZE_UP_DN	(QSERDES_RX + 0x12C)
#define QSERDES_RX_CDR_RESET_OVERRIDE	(QSERDES_RX + 0x130)
#define QSERDES_RX_RX_INTERFACE_MODE	(QSERDES_RX + 0x134)
#define QSERDES_RX_JITTER_GEN_MODE	(QSERDES_RX + 0x138)
#define QSERDES_RX_SJ_AMP1	(QSERDES_RX + 0x13C)
#define QSERDES_RX_SJ_AMP2	(QSERDES_RX + 0x140)
#define QSERDES_RX_SJ_PER1	(QSERDES_RX + 0x144)
#define QSERDES_RX_SJ_PER2	(QSERDES_RX + 0x148)
#define QSERDES_RX_PPM_OFFSET1	(QSERDES_RX + 0x14C)
#define QSERDES_RX_PPM_OFFSET2	(QSERDES_RX + 0x150)
#define QSERDES_RX_SIGN_PPM_PERIOD1	(QSERDES_RX + 0x154)
#define QSERDES_RX_SIGN_PPM_PERIOD2	(QSERDES_RX + 0x158)
#define QSERDES_RX0_RX_MODE_00_LOW	(QSERDES_RX + 0x15C)
#define QSERDES_RX0_RX_MODE_00_HIGH	(QSERDES_RX + 0x160)
#define QSERDES_RX0_RX_MODE_00_HIGH2	(QSERDES_RX + 0x164)
#define QSERDES_RX0_RX_MODE_00_HIGH3	(QSERDES_RX + 0x168)
#define QSERDES_RX0_RX_MODE_00_HIGH4	(QSERDES_RX + 0x16C)
#define QSERDES_RX0_RX_MODE_01_LOW	(QSERDES_RX + 0x170)
#define QSERDES_RX0_RX_MODE_01_HIGH	(QSERDES_RX + 0x174)
#define QSERDES_RX0_RX_MODE_01_HIGH2	(QSERDES_RX + 0x178)
#define QSERDES_RX0_RX_MODE_01_HIGH3	(QSERDES_RX + 0x17C)
#define QSERDES_RX0_RX_MODE_01_HIGH4	(QSERDES_RX + 0x180)
#define QSERDES_RX0_RX_MODE_10_LOW	(QSERDES_RX + 0x184)
#define QSERDES_RX0_RX_MODE_10_HIGH	(QSERDES_RX + 0x188)
#define QSERDES_RX0_RX_MODE_10_HIGH2	(QSERDES_RX + 0x18C)
#define QSERDES_RX0_RX_MODE_10_HIGH3	(QSERDES_RX + 0x190)
#define QSERDES_RX0_RX_MODE_10_HIGH4	(QSERDES_RX + 0x194)
#define QSERDES_RX_PHPRE_CTRL	(QSERDES_RX + 0x198)
#define QSERDES_RX_PHPRE_INITVAL	(QSERDES_RX + 0x19C)
#define QSERDES_RX_DFE_EN_TIMER	(QSERDES_RX + 0x1A0)
#define QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	(QSERDES_RX + 0x1A4)
#define QSERDES_RX0_DCC_CTRL1	(QSERDES_RX + 0x1A8)
#define QSERDES_RX_DCC_CTRL2	(QSERDES_RX + 0x1AC)
#define QSERDES_RX_VTH_CODE	(QSERDES_RX + 0x1B0)
#define QSERDES_RX_VTH_MIN_THRESH	(QSERDES_RX + 0x1B4)
#define QSERDES_RX_VTH_MAX_THRESH	(QSERDES_RX + 0x1B8)
#define QSERDES_RX_ALOG_OBSV_BUS_CTRL_1	(QSERDES_RX + 0x1BC)
#define QSERDES_RX_PI_CTRL1	(QSERDES_RX + 0x1C0)
#define QSERDES_RX_PI_CTRL2	(QSERDES_RX + 0x1C4)
#define QSERDES_RX_PI_QUAD	(QSERDES_RX + 0x1C8)
#define QSERDES_RX_IDATA1	(QSERDES_RX + 0x1CC)
#define QSERDES_RX_IDATA2	(QSERDES_RX + 0x1D0)
#define QSERDES_RX_AUX_DATA1	(QSERDES_RX + 0x1D4)
#define QSERDES_RX_AUX_DATA2	(QSERDES_RX + 0x1D8)
#define QSERDES_RX_AC_JTAG_OUTP	(QSERDES_RX + 0x1DC)
#define QSERDES_RX_AC_JTAG_OUTN	(QSERDES_RX + 0x1E0)
#define QSERDES_RX_RX_SIGDET	(QSERDES_RX + 0x1E4)
#define QSERDES_RX_ALOG_OBSV_BUS_STATUS_1	(QSERDES_RX + 0x1E0)
#define QSERDES_RX0_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE (QSERDES_RX + 0x1E8)

#define QSERDES_TX	0x400
#define QSERDES_TX_BIST_MODE_LANENO	(QSERDES_TX + 0x0)
#define QSERDES_TX_BIST_INVERT	(QSERDES_TX + 0x4)
#define QSERDES_TX_CLKBUF_ENABLE	(QSERDES_TX + 0x8)
#define QSERDES_TX_TX_EMP_POST1_LVL	(QSERDES_TX + 0xC)
#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP	(QSERDES_TX + 0x10)
#define QSERDES_TX_TX_DRV_LVL	(QSERDES_TX + 0x14)
#define QSERDES_TX_TX_DRV_LVL_OFFSET	(QSERDES_TX + 0x18)
#define QSERDES_TX_RESET_TSYNC_EN	(QSERDES_TX + 0x1C)
#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN	(QSERDES_TX + 0x20)
#define QSERDES_TX0_TX_BAND	(QSERDES_TX + 0x24)
#define QSERDES_TX0_SLEW_CNTL	(QSERDES_TX + 0x28)
#define QSERDES_TX_INTERFACE_SELECT	(QSERDES_TX + 0x2C)
#define QSERDES_TX_LPB_EN	(QSERDES_TX + 0x30)
#define QSERDES_TX_RES_CODE_LANE_TX	(QSERDES_TX + 0x34)
#define QSERDES_TX_RES_CODE_LANE_RX	(QSERDES_TX + 0x38)
#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX	(QSERDES_TX + 0x3C)
#define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX	(QSERDES_TX + 0x40)
#define QSERDES_TX_PERL_LENGTH1	(QSERDES_TX + 0x44)
#define QSERDES_TX_PERL_LENGTH2	(QSERDES_TX + 0x48)
#define QSERDES_TX_SERDES_BYP_EN_OUT	(QSERDES_TX + 0x4C)
#define QSERDES_TX_DEBUG_BUS_SEL	(QSERDES_TX + 0x50)
#define QSERDES_TX_TRANSCEIVER_BIAS_EN	(QSERDES_TX + 0x54)
#define QSERDES_TX_HIGHZ_DRVR_EN	(QSERDES_TX + 0x58)
#define QSERDES_TX_TX_POL_INV	(QSERDES_TX + 0x5C)
#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN	(QSERDES_TX + 0x60)
#define QSERDES_TX_BIST_PATTERN1	(QSERDES_TX + 0x64)
#define QSERDES_TX_BIST_PATTERN2	(QSERDES_TX + 0x68)
#define QSERDES_TX_BIST_PATTERN3	(QSERDES_TX + 0x6C)
#define QSERDES_TX_BIST_PATTERN4	(QSERDES_TX + 0x70)
#define QSERDES_TX_BIST_PATTERN5	(QSERDES_TX + 0x74)
#define QSERDES_TX_BIST_PATTERN6	(QSERDES_TX + 0x78)
#define QSERDES_TX_BIST_PATTERN7	(QSERDES_TX + 0x7C)
#define QSERDES_TX_BIST_PATTERN8	(QSERDES_TX + 0x80)
#define QSERDES_TX0_LANE_MODE_1	(QSERDES_TX + 0x84)
#define QSERDES_TX0_LANE_MODE_2	(QSERDES_TX + 0x88)
#define QSERDES_TX0_LANE_MODE_3	(QSERDES_TX + 0x8C)
#define QSERDES_TX_LANE_MODE_4	(QSERDES_TX + 0x90)
#define QSERDES_TX_LANE_MODE_5	(QSERDES_TX + 0x94)
#define QSERDES_TX_ATB_SEL1	(QSERDES_TX + 0x98)
#define QSERDES_TX_ATB_SEL2	(QSERDES_TX + 0x9C)
#define QSERDES_TX_RCV_DETECT_LVL	(QSERDES_TX + 0xA0)
#define QSERDES_TX0_RCV_DETECT_LVL_2	(QSERDES_TX + 0xA4)
#define QSERDES_TX_PRBS_SEED1	(QSERDES_TX + 0xA8)
#define QSERDES_TX_PRBS_SEED2	(QSERDES_TX + 0xAC)
#define QSERDES_TX_PRBS_SEED3	(QSERDES_TX + 0xB0)
#define QSERDES_TX_PRBS_SEED4	(QSERDES_TX + 0xB4)
#define QSERDES_TX_RESET_GEN	(QSERDES_TX + 0xB8)
#define QSERDES_TX_RESET_GEN_MUXES	(QSERDES_TX + 0xBC)
#define QSERDES_TX0_TRAN_DRVR_EMP_EN	(QSERDES_TX + 0xC0)
#define QSERDES_TX_TX_INTERFACE_MODE	(QSERDES_TX + 0xC4)
#define QSERDES_TX_VMODE_CTRL1	(QSERDES_TX + 0xC8)
#define QSERDES_TX_ALOG_OBSV_BUS_CTRL_1	(QSERDES_TX + 0xCC)
#define QSERDES_TX_BIST_STATUS	(QSERDES_TX + 0xD0)
#define QSERDES_TX_BIST_ERROR_COUNT1	(QSERDES_TX + 0xD4)
#define QSERDES_TX_BIST_ERROR_COUNT2	(QSERDES_TX + 0xD8)
#define QSERDES_TX_ALOG_OBSV_BUS_STATUS_1	(QSERDES_TX + 0xDC)
#define QSERDES_TX_LANE_DIG_CONFIG	(QSERDES_TX + 0xE0)
#define QSERDES_TX_PI_QEC_CTRL	(QSERDES_TX + 0xE4)
#define QSERDES_TX_PRE_EMPH	(QSERDES_TX + 0xE8)
#define QSERDES_TX_SW_RESET	(QSERDES_TX + 0xEC)
#define QSERDES_TX_DCC_OFFSET	(QSERDES_TX + 0xF0)
#define QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET	(QSERDES_TX + 0xF4)
#define QSERDES_TX_DCC_CMUX_CAL_CTRL1	(QSERDES_TX + 0xF8)
#define QSERDES_TX_DCC_CMUX_CAL_CTRL2	(QSERDES_TX + 0xFC)
#define QSERDES_TX_DIG_BKUP_CTRL	(QSERDES_TX + 0x100)
#define QSERDES_TX_DEBUG_BUS0	(QSERDES_TX + 0x104)
#define QSERDES_TX_DEBUG_BUS1	(QSERDES_TX + 0x108)
#define QSERDES_TX_DEBUG_BUS2	(QSERDES_TX + 0x10C)
#define QSERDES_TX_DEBUG_BUS3	(QSERDES_TX + 0x110)
#define QSERDES_TX_READ_EQCODE	(QSERDES_TX + 0x114)
#define QSERDES_TX_READ_OFFSETCODE	(QSERDES_TX + 0x118)
#define QSERDES_TX_IA_ERROR_COUNTER_LOW	(QSERDES_TX + 0x11C)
#define QSERDES_TX_IA_ERROR_COUNTER_HIGH	(QSERDES_TX + 0x120)
#define QSERDES_TX_VGA_READ_CODE	(QSERDES_TX + 0x124)
#define QSERDES_TX_VTH_READ_CODE	(QSERDES_TX + 0x128)
#define QSERDES_TX_DFE_TAP1_READ_CODE	(QSERDES_TX + 0x12C)
#define QSERDES_TX_DFE_TAP2_READ_CODE	(QSERDES_TX + 0x130)
#define QSERDES_TX_IDAC_STATUS_I	(QSERDES_TX + 0x134)
#define QSERDES_TX_IDAC_STATUS_IBAR	(QSERDES_TX + 0x138)
#define QSERDES_TX_IDAC_STATUS_Q	(QSERDES_TX + 0x13C)
#define QSERDES_TX_IDAC_STATUS_QBAR	(QSERDES_TX + 0x140)
#define QSERDES_TX_IDAC_STATUS_A	(QSERDES_TX + 0x144)
#define QSERDES_TX_IDAC_STATUS_ABAR	(QSERDES_TX + 0x148)
#define QSERDES_TX_IDAC_STATUS_SM_ON	(QSERDES_TX + 0x14C)
#define QSERDES_TX_IDAC_STATUS_CAL_DONE	(QSERDES_TX + 0x150)
#define QSERDES_TX_IDAC_STATUS_SIGNERROR	(QSERDES_TX + 0x154)
#define QSERDES_TX_DCC_CAL_STATUS	(QSERDES_TX + 0x158)
#define QSERDES_TX_DCC_READ_CODE_STATUS	(QSERDES_TX + 0x15C)

#define QSERDES_PCS	0xC00
#define SGMII_PHY_PCS_PHY_START (QSERDES_PCS + 0x0)
#define SGMII_PHY_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4)
#define SGMII_PHY_PCS_SW_RESET (QSERDES_PCS + 0x8)
#define SGMII_PHY_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xC)
#define QSERDES_PCS_PCS_CTRL1 (QSERDES_PCS + 0x10)
#define QSERDES_PCS_TSYNC_RSYNC_CNTL (QSERDES_PCS + 0x14)
#define QSERDES_PCS_RETIME_BUFFER_EN (QSERDES_PCS + 0x18)
#define QSERDES_PCS_PLL_CNTL (QSERDES_PCS + 0x1C)
#define SGMII_PHY_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20)
#define QSERDES_PCS_TX_LARGE_AMP_POST_EMP_LVL (QSERDES_PCS + 0x24)
#define SGMII_PHY_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28)
#define QSERDES_PCS_TX_SMALL_AMP_POST_EMP_LVL (QSERDES_PCS + 0x2C)
#define QSERDES_PCS_RX_SYNC_WAIT_TIME (QSERDES_PCS + 0x30)
#define QSERDES_PCS_L0_BIST_CTRL (QSERDES_PCS + 0x34)
#define QSERDES_PCS_MISC_BIST_CTRL (QSERDES_PCS + 0x38)
#define QSERDES_PCS_BIST_PRBS_POLY0 (QSERDES_PCS + 0x3C)
#define QSERDES_PCS_BIST_PRBS_POLY1 (QSERDES_PCS + 0x40)
#define QSERDES_PCS_BIST_PRBS_SEED0 (QSERDES_PCS + 0x44)
#define QSERDES_PCS_BIST_PRBS_SEED1 (QSERDES_PCS + 0x48)
#define QSERDES_PCS_BIST_PRBS_SEED2 (QSERDES_PCS + 0x4C)
#define QSERDES_PCS_BIST_NUM_IPG (QSERDES_PCS + 0x50)
#define QSERDES_PCS_RX_HS_EQUALIZER_SETTING_CAPABILITY (QSERDES_PCS + 0x54)
#define QSERDES_PCS_RX_HS_ADAPT_LENGTH_REFRESH_CAPABILITY (QSERDES_PCS + 0x58)
#define QSERDES_PCS_RX_HS_ADAPT_LENGTH_INITIAL_CAPABILITY (QSERDES_PCS + 0x5C)
#define QSERDES_PCS_DEBUG_BUS_CLKSEL (QSERDES_PCS + 0x60)
#define QSERDES_PCS_DEBUG_BUS_0_CTRL (QSERDES_PCS + 0x64)
#define QSERDES_PCS_DEBUG_BUS_1_CTRL (QSERDES_PCS + 0x68)
#define QSERDES_PCS_DEBUG_BUS_2_CTRL (QSERDES_PCS + 0x6C)
#define QSERDES_PCS_DEBUG_BUS_3_CTRL (QSERDES_PCS + 0x70)
#define QSERDES_PCS_DEBUG_BUS_0_STATUS_CHK (QSERDES_PCS + 0x74)
#define QSERDES_PCS_DEBUG_BUS_1_STATUS_CHK (QSERDES_PCS + 0x78)
#define QSERDES_PCS_DEBUG_BUS_2_STATUS_CHK (QSERDES_PCS + 0x7C)
#define QSERDES_PCS_DEBUG_BUS_3_STATUS_CHK (QSERDES_PCS + 0x80)
#define QSERDES_PCS_RX_MIN_HIBERN8_TIME (QSERDES_PCS + 0x84)
#define QSERDES_PCS_RX_SIGDET_CTRL1 (QSERDES_PCS + 0x88)
#define QSERDES_PCS_RX_SIGDET_CTRL2 (QSERDES_PCS + 0x8C)
#define QSERDES_PCS_TCLK_SYM_CNTR_INITVAL (QSERDES_PCS + 0x90)
#define SGMII_PHY_PCS_READY_STATUS (QSERDES_PCS + 0x94)
#define QSERDES_PCS_PCS_MISC_STATUS (QSERDES_PCS + 0x98)
#define QSERDES_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS (QSERDES_PCS + 0x9C)
#define QSERDES_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS (QSERDES_PCS + 0xA0)
#define QSERDES_PCS_L0_BIST_CHK_STATUS (QSERDES_PCS + 0xA4)
#define QSERDES_PCS_DEBUG_BUS_0_STATUS (QSERDES_PCS + 0xA8)
#define QSERDES_PCS_DEBUG_BUS_1_STATUS (QSERDES_PCS + 0xAC)
#define QSERDES_PCS_DEBUG_BUS_2_STATUS (QSERDES_PCS + 0xB0)
#define QSERDES_PCS_DEBUG_BUS_3_STATUS (QSERDES_PCS + 0xB4)
#define QSERDES_PCS_REVISION_ID0 (QSERDES_PCS + 0xB8)
#define QSERDES_PCS_REVISION_ID1 (QSERDES_PCS + 0xBC)
#define QSERDES_PCS_REVISION_ID2 (QSERDES_PCS + 0xC0)
#define QSERDES_PCS_REVISION_ID3 (QSERDES_PCS + 0xC4)
#define QSERDES_PCS_SYSCLK_EN_COUNT_CTRL (QSERDES_PCS + 0xC8)
#define QSERDES_PCS_PLL_SHUTDOWN_CTRL (QSERDES_PCS + 0xCC)
#define QSERDES_PCS_TIMER_20US_CORECLK_STEPS_MSB (QSERDES_PCS + 0xD0)
#define QSERDES_PCS_TIMER_20US_CORECLK_STEPS_LSB (QSERDES_PCS + 0xD4)
#define SGMII_PHY_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xD8)
#define SGMII_PHY_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xDC)
#define QSERDES_PCS_MULTI_LANE_CTRL1 (QSERDES_PCS + 0xE0)
#define QSERDES_PCS_L1_BIST_CTRL (QSERDES_PCS + 0xE4)
#define QSERDES_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS (QSERDES_PCS + 0xE8)
#define QSERDES_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS (QSERDES_PCS + 0xEC)
#define QSERDES_PCS_L1_BIST_CHK_STATUS (QSERDES_PCS + 0xF0)
#define QSERDES_PCS_STATUS_CLEAR (QSERDES_PCS + 0xF4)
#define QSERDES_PCS_RX_HSG4_SYNC_WAIT_TIME (QSERDES_PCS + 0xF8)
#define QSERDES_PCS_SGMII_MISC_CTRL1 (QSERDES_PCS + 0xFC)
#define QSERDES_PCS_SGMII_MISC_CTRL2 (QSERDES_PCS + 0x100)
#define QSERDES_PCS_SGMII_MISC_CTRL3 (QSERDES_PCS + 0x104)
#define QSERDES_PCS_SGMII_MISC_CTRL4 (QSERDES_PCS + 0x108)
#define QSERDES_PCS_SGMII_MISC_CTRL5 (QSERDES_PCS + 0x10C)
#define QSERDES_PCS_SGMII_MISC_CTRL6 (QSERDES_PCS + 0x110)
#define QSERDES_PCS_SGMII_INTERRUPT_STATUS (QSERDES_PCS + 0x11C)
#define QSERDES_PCS_SGMII_IRQ_CLEAR (QSERDES_PCS + 0x120)
#define QSERDES_PCS_SGMII_IRQ_MASK (QSERDES_PCS + 0x124)
#define SGMII_PHY_PCS_SGMII_MISC_CTRL7 (QSERDES_PCS + 0x114)
#define SGMII_PHY_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118)

#define QSERDES_PCS_2	0x200
#define QSERDES_PCS2_PCS_CMN_STATUS (QSERDES_PCS_2 + 0x0)
#define QSERDES_PCS2_TCLK_CTRL_STATUS (QSERDES_PCS_2 + 0x4)
#define QSERDES_PCS2_TX_LANE0_0_STATUS (QSERDES_PCS_2 + 0x8)
#define QSERDES_PCS2_TX_LANE0_1_STATUS (QSERDES_PCS_2 + 0xC)
#define QSERDES_PCS2_TX_LANE0_2_STATUS (QSERDES_PCS_2 + 0x10)
#define QSERDES_PCS2_RX_LANE0_0_STATUS (QSERDES_PCS_2 + 0x14)
#define QSERDES_PCS2_RX_LANE0_1_STATUS (QSERDES_PCS_2 + 0x18)
#define QSERDES_PCS2_RX_LANE0_3_STATUS (QSERDES_PCS_2 + 0x1C)
#define QSERDES_PCS2_TX_LANE1_0_STATUS (QSERDES_PCS_2 + 0x20)
#define QSERDES_PCS2_TX_LANE1_1_STATUS (QSERDES_PCS_2 + 0x24)
#define QSERDES_PCS2_TX_LANE1_2_STATUS (QSERDES_PCS_2 + 0x28)
#define QSERDES_PCS2_RX_LANE1_0_STATUS (QSERDES_PCS_2 + 0x2C)
#define QSERDES_PCS2_RX_LANE1_1_STATUS (QSERDES_PCS_2 + 0x30)
#define QSERDES_PCS2_RX_LANE1_3_STATUS (QSERDES_PCS_2 + 0x34)

#define QSERDES3_QMP_PLL	0x0
#define QSERDES3_COM_ATB_SEL1	(QSERDES3_QMP_PLL + 0x0)
#define QSERDES3_COM_ATB_SEL2	(QSERDES3_QMP_PLL + 0x4)
#define QSERDES3_COM_BG_TIMER	(QSERDES3_QMP_PLL + 0xC)
#define QSERDES3_COM_BIAS_EN_CLKBUFLR_EN	(QSERDES3_QMP_PLL + 0x44)
#define QSERDES3_COM_BIAS_EN_CTRL_BY_PSM	(QSERDES3_QMP_PLL + 0x90)
#define QSERDES3_COM_BIN_VCOCAL_CMP_CODE1_MODE0	(QSERDES3_QMP_PLL + 0x1AC)
#define QSERDES3_COM_BIN_VCOCAL_CMP_CODE1_MODE1	(QSERDES3_QMP_PLL + 0x1B4)
#define QSERDES3_COM_BIN_VCOCAL_CMP_CODE2_MODE0	(QSERDES3_QMP_PLL + 0x1B0)
#define QSERDES3_COM_BIN_VCOCAL_CMP_CODE2_MODE1	(QSERDES3_QMP_PLL + 0x1B8)
#define QSERDES3_COM_BIN_VCOCAL_HSCLK_SEL	(QSERDES3_QMP_PLL + 0x1BC)
#define QSERDES3_COM_C_READY_STATUS	(QSERDES3_QMP_PLL + 0x178)
#define QSERDES3_COM_CLK_ENABLE1	(QSERDES3_QMP_PLL + 0x48)
#define QSERDES3_COM_CLK_EP_DIV_MODE0	(QSERDES3_QMP_PLL + 0x6C)
#define QSERDES3_COM_CLK_EP_DIV_MODE1	(QSERDES3_QMP_PLL + 0x70)
#define QSERDES3_COM_CLK_SELECT	(QSERDES3_QMP_PLL + 0x154)
#define QSERDES3_COM_CML_SYSCLK_SEL	(QSERDES3_QMP_PLL + 0x98)
#define QSERDES3_COM_CMN_CONFIG	(QSERDES3_QMP_PLL + 0x17C)
#define QSERDES3_COM_CMN_IETRIM	(QSERDES3_QMP_PLL + 0x5C)
#define QSERDES3_COM_CMN_IPTRIM	(QSERDES3_QMP_PLL + 0x60)
#define QSERDES3_COM_CMN_MISC1	(QSERDES3_QMP_PLL + 0x19C)
#define QSERDES3_COM_CMN_MODE	(QSERDES3_QMP_PLL + 0x1A0)
#define QSERDES3_COM_CMN_MODE_CONTD	(QSERDES3_QMP_PLL + 0x1A4)
#define QSERDES3_COM_CMN_RATE_OVERRIDE	(QSERDES3_QMP_PLL + 0x180)
#define QSERDES3_COM_CMN_STATUS	(QSERDES3_QMP_PLL + 0x140)
#define QSERDES3_COM_CORE_CLK_EN	(QSERDES3_QMP_PLL + 0x174)
#define QSERDES3_COM_CORECLK_DIV_MODE0	(QSERDES3_QMP_PLL + 0x168)
#define QSERDES3_COM_CORECLK_DIV_MODE1	(QSERDES3_QMP_PLL + 0x16C)
#define QSERDES3_COM_CP_CTRL_MODE0	(QSERDES3_QMP_PLL + 0x74)
#define QSERDES3_COM_CP_CTRL_MODE1	(QSERDES3_QMP_PLL + 0x78)
#define QSERDES3_COM_DEBUG_BUS0	(QSERDES3_QMP_PLL + 0x188)
#define QSERDES3_COM_DEBUG_BUS1	(QSERDES3_QMP_PLL + 0x18C)
#define QSERDES3_COM_DEBUG_BUS2	(QSERDES3_QMP_PLL + 0x190)
#define QSERDES3_COM_DEBUG_BUS3	(QSERDES3_QMP_PLL + 0x194)
#define QSERDES3_COM_DEBUG_BUS_SEL	(QSERDES3_QMP_PLL + 0x198)
#define QSERDES3_COM_DEC_START_MODE0	(QSERDES3_QMP_PLL + 0xBC)
#define QSERDES3_COM_DEC_START_MODE1	(QSERDES3_QMP_PLL + 0xC4)
#define QSERDES3_COM_DEC_START_MSB_MODE0	(QSERDES3_QMP_PLL + 0xC0)
#define QSERDES3_COM_DEC_START_MSB_MODE1	(QSERDES3_QMP_PLL + 0xC8)
#define QSERDES3_COM_DIV_FRAC_START1_MODE0	(QSERDES3_QMP_PLL + 0xCC)
#define QSERDES3_COM_DIV_FRAC_START1_MODE1	(QSERDES3_QMP_PLL + 0xD8)
#define QSERDES3_COM_DIV_FRAC_START2_MODE0	(QSERDES3_QMP_PLL + 0xD0)
#define QSERDES3_COM_DIV_FRAC_START2_MODE1	(QSERDES3_QMP_PLL + 0xDC)
#define QSERDES3_COM_DIV_FRAC_START3_MODE0	(QSERDES3_QMP_PLL + 0xD4)
#define QSERDES3_COM_DIV_FRAC_START3_MODE1	(QSERDES3_QMP_PLL + 0xE0)
#define QSERDES3_COM_EP_CLOCK_DETECT_CTRL	(QSERDES3_QMP_PLL + 0x64)
#define QSERDES3_COM_FREQ_UPDATE	(QSERDES3_QMP_PLL + 0x8)
#define QSERDES3_COM_HSCLK_HS_SWITCH_SEL	(QSERDES3_QMP_PLL + 0x15C)
#define QSERDES3_COM_HSCLK_SEL	(QSERDES3_QMP_PLL + 0x158)
#define QSERDES3_COM_INTEGLOOP_BINCODE_STATUS	(QSERDES3_QMP_PLL + 0x160)
#define QSERDES3_COM_INTEGLOOP_EN	(QSERDES3_QMP_PLL + 0xE8)
#define QSERDES3_COM_INTEGLOOP_GAIN0_MODE0	(QSERDES3_QMP_PLL + 0xEC)
#define QSERDES3_COM_INTEGLOOP_GAIN0_MODE1	(QSERDES3_QMP_PLL + 0xF4)
#define QSERDES3_COM_INTEGLOOP_GAIN1_MODE0	(QSERDES3_QMP_PLL + 0xF0)
#define QSERDES3_COM_INTEGLOOP_GAIN1_MODE1	(QSERDES3_QMP_PLL + 0xF8)
#define QSERDES3_COM_INTEGLOOP_INITVAL	(QSERDES3_QMP_PLL + 0xE4)
#define QSERDES3_COM_INTEGLOOP_P_PATH_GAIN0	(QSERDES3_QMP_PLL + 0xFC)
#define QSERDES3_COM_INTEGLOOP_P_PATH_GAIN1	(QSERDES3_QMP_PLL + 0x100)
#define QSERDES3_COM_LOCK_CMP1_MODE0	(QSERDES3_QMP_PLL + 0xAC)
#define QSERDES3_COM_LOCK_CMP1_MODE1	(QSERDES3_QMP_PLL + 0xB4)
#define QSERDES3_COM_LOCK_CMP2_MODE0	(QSERDES3_QMP_PLL + 0xB0)
#define QSERDES3_COM_LOCK_CMP2_MODE1	(QSERDES3_QMP_PLL + 0xB8)
#define QSERDES3_COM_LOCK_CMP_CFG	(QSERDES3_QMP_PLL + 0xA8)
#define QSERDES3_COM_LOCK_CMP_EN	(QSERDES3_QMP_PLL + 0xA4)
#define QSERDES3_COM_MODE_OPERATION_STATUS	(QSERDES3_QMP_PLL + 0x1C4)
#define QSERDES3_COM_PLL_ANALOG	(QSERDES3_QMP_PLL + 0x164)
#define QSERDES3_COM_PLL_CCTRL_MODE0	(QSERDES3_QMP_PLL + 0x84)
#define QSERDES3_COM_PLL_CCTRL_MODE1	(QSERDES3_QMP_PLL + 0x88)
#define QSERDES3_COM_PLL_CNTRL	(QSERDES3_QMP_PLL + 0x8C)
#define QSERDES3_COM_PLL_EN	(QSERDES3_QMP_PLL + 0x54)
#define QSERDES3_COM_PLL_IVCO	(QSERDES3_QMP_PLL + 0x58)
#define QSERDES3_COM_PLL_RCTRL_MODE0	(QSERDES3_QMP_PLL + 0x7C)
#define QSERDES3_COM_PLL_RCTRL_MODE1	(QSERDES3_QMP_PLL + 0x80)
#define QSERDES3_COM_PLLCAL_CODE1_STATUS	(QSERDES3_QMP_PLL + 0x14C)
#define QSERDES3_COM_PLLCAL_CODE2_STATUS	(QSERDES3_QMP_PLL + 0x150)
#define QSERDES3_COM_POST_DIV	(QSERDES3_QMP_PLL + 0x3C)
#define QSERDES3_COM_POST_DIV_MUX	(QSERDES3_QMP_PLL + 0x40)
#define QSERDES3_COM_RESERVED_1	(QSERDES3_QMP_PLL + 0x1C0)
#define QSERDES3_COM_RESET_SM_STATUS	(QSERDES3_QMP_PLL + 0x144)
#define QSERDES3_COM_RESETSM_CNTRL	(QSERDES3_QMP_PLL + 0x9C)
#define QSERDES3_COM_RESETSM_CNTRL2	(QSERDES3_QMP_PLL + 0xA0)
#define QSERDES3_COM_RESTRIM_CODE_STATUS	(QSERDES3_QMP_PLL + 0x148)
#define QSERDES3_COM_SSC_ADJ_PER1	(QSERDES3_QMP_PLL + 0x14)
#define QSERDES3_COM_SSC_ADJ_PER2	(QSERDES3_QMP_PLL + 0x18)
#define QSERDES3_COM_SSC_EN_CENTER	(QSERDES3_QMP_PLL + 0x10)
#define QSERDES3_COM_SSC_PER1	(QSERDES3_QMP_PLL + 0x1C)
#define QSERDES3_COM_SSC_PER2	(QSERDES3_QMP_PLL + 0x20)
#define QSERDES3_COM_SSC_STEP_SIZE1_MODE0	(QSERDES3_QMP_PLL + 0x24)
#define QSERDES3_COM_SSC_STEP_SIZE1_MODE1	(QSERDES3_QMP_PLL + 0x30)
#define QSERDES3_COM_SSC_STEP_SIZE2_MODE0	(QSERDES3_QMP_PLL + 0x28)
#define QSERDES3_COM_SSC_STEP_SIZE2_MODE1	(QSERDES3_QMP_PLL + 0x34)
#define QSERDES3_COM_SSC_STEP_SIZE3_MODE0	(QSERDES3_QMP_PLL + 0x2C)
#define QSERDES3_COM_SSC_STEP_SIZE3_MODE1	(QSERDES3_QMP_PLL + 0x38)
#define QSERDES3_COM_SVS_MODE_CLK_SEL	(QSERDES3_QMP_PLL + 0x184)
#define QSERDES3_COM_SW_RESET	(QSERDES3_QMP_PLL + 0x170)
#define QSERDES3_COM_SYS_CLK_CTRL	(QSERDES3_QMP_PLL + 0x4C)
#define QSERDES3_COM_SYSCLK_BUF_ENABLE	(QSERDES3_QMP_PLL + 0x50)
#define QSERDES3_COM_SYSCLK_DET_COMP_STATUS	(QSERDES3_QMP_PLL + 0x68)
#define QSERDES3_COM_SYSCLK_EN_SEL	(QSERDES3_QMP_PLL + 0x94)
#define QSERDES3_COM_VCO_DC_LEVEL_CTRL	(QSERDES3_QMP_PLL + 0x1A8)
#define QSERDES3_COM_VCO_TUNE1_MODE0	(QSERDES3_QMP_PLL + 0x110)
#define QSERDES3_COM_VCO_TUNE1_MODE1	(QSERDES3_QMP_PLL + 0x118)
#define QSERDES3_COM_VCO_TUNE2_MODE0	(QSERDES3_QMP_PLL + 0x114)
#define QSERDES3_COM_VCO_TUNE2_MODE1	(QSERDES3_QMP_PLL + 0x11C)
#define QSERDES3_COM_VCO_TUNE_CTRL	(QSERDES3_QMP_PLL + 0x108)
#define QSERDES3_COM_VCO_TUNE_INITVAL1	(QSERDES3_QMP_PLL + 0x120)
#define QSERDES3_COM_VCO_TUNE_INITVAL2	(QSERDES3_QMP_PLL + 0x124)
#define QSERDES3_COM_VCO_TUNE_MAP	(QSERDES3_QMP_PLL + 0x10C)
#define QSERDES3_COM_VCO_TUNE_MAXVAL1	(QSERDES3_QMP_PLL + 0x130)
#define QSERDES3_COM_VCO_TUNE_MAXVAL2	(QSERDES3_QMP_PLL + 0x134)
#define QSERDES3_COM_VCO_TUNE_MINVAL1	(QSERDES3_QMP_PLL + 0x128)
#define QSERDES3_COM_VCO_TUNE_MINVAL2	(QSERDES3_QMP_PLL + 0x12C)
#define QSERDES3_COM_VCO_TUNE_TIMER1	(QSERDES3_QMP_PLL + 0x138)
#define QSERDES3_COM_VCO_TUNE_TIMER2	(QSERDES3_QMP_PLL + 0x13C)
#define QSERDES3_COM_VCOCAL_DEADMAN_CTRL	(QSERDES3_QMP_PLL + 0x104)

#define QSERDES3_RX	0x600
#define QSERDES3_RX_UCDR_FO_GAIN_HALF	(QSERDES3_RX + 0x0)
#define QSERDES3_RX_UCDR_FO_GAIN_QUARTER	(QSERDES3_RX + 0x4)
#define QSERDES3_RX_UCDR_FO_GAIN	(QSERDES3_RX + 0x8)
#define QSERDES3_RX_UCDR_SO_GAIN_HALF	(QSERDES3_RX + 0xC)
#define QSERDES3_RX_UCDR_SO_GAIN_QUARTER	(QSERDES3_RX + 0x10)
#define QSERDES3_RX_UCDR_SO_GAIN	(QSERDES3_RX + 0x14)
#define QSERDES3_RX_UCDR_SVS_FO_GAIN_HALF	(QSERDES3_RX + 0x18)
#define QSERDES3_RX_UCDR_SVS_FO_GAIN_QUARTER	(QSERDES3_RX + 0x1C)
#define QSERDES3_RX_UCDR_SVS_FO_GAIN	(QSERDES3_RX + 0x20)
#define QSERDES3_RX_UCDR_SVS_SO_GAIN_HALF	(QSERDES3_RX + 0x24)
#define QSERDES3_RX_UCDR_SVS_SO_GAIN_QUARTER	(QSERDES3_RX + 0x28)
#define QSERDES3_RX_UCDR_SVS_SO_GAIN	(QSERDES3_RX + 0x2C)
#define QSERDES3_RX_UCDR_FASTLOCK_FO_GAIN	(QSERDES3_RX + 0x30)
#define QSERDES3_RX_UCDR_SO_SATURATION_AND_ENABLE	(QSERDES3_RX + 0x34)
#define QSERDES3_RX_UCDR_FO_TO_SO_DELAY	(QSERDES3_RX + 0x38)
#define QSERDES3_RX_UCDR_FASTLOCK_COUNT_LOW	(QSERDES3_RX + 0x3C)
#define QSERDES3_RX_UCDR_FASTLOCK_COUNT_HIGH	(QSERDES3_RX + 0x40)
#define QSERDES3_RX_UCDR_PI_CONTROLS	(QSERDES3_RX + 0x44)
#define QSERDES3_RX_UCDR_PI_CTRL2	(QSERDES3_RX + 0x48)
#define QSERDES3_RX_UCDR_SB2_THRESH1	(QSERDES3_RX + 0x4C)
#define QSERDES3_RX_UCDR_SB2_THRESH2	(QSERDES3_RX + 0x50)
#define QSERDES3_RX_UCDR_SB2_GAIN1	(QSERDES3_RX + 0x54)
#define QSERDES3_RX_UCDR_SB2_GAIN2	(QSERDES3_RX + 0x58)
#define QSERDES3_RX_AUX_CONTROL	(QSERDES3_RX + 0x5C)
#define QSERDES3_RX_AUX_DATA_TCOARSE_TFINE	(QSERDES3_RX + 0x60)
#define QSERDES3_RX_RCLK_AUXDATA_SEL	(QSERDES3_RX + 0x64)
#define QSERDES3_RX_AC_JTAG_ENABLE	(QSERDES3_RX + 0x68)
#define QSERDES3_RX_AC_JTAG_INITP	(QSERDES3_RX + 0x6C)
#define QSERDES3_RX_AC_JTAG_INITN	(QSERDES3_RX + 0x70)
#define QSERDES3_RX_AC_JTAG_LVL	(QSERDES3_RX + 0x74)
#define QSERDES3_RX_AC_JTAG_MODE	(QSERDES3_RX + 0x78)
#define QSERDES3_RX_AC_JTAG_RESET	(QSERDES3_RX + 0x7C)
#define QSERDES3_RX_RX_TERM_BW	(QSERDES3_RX + 0x80)
#define QSERDES3_RX_RX_RCVR_IQ_EN	(QSERDES3_RX + 0x84)
#define QSERDES3_RX_RX_IDAC_I_DC_OFFSETS	(QSERDES3_RX + 0x88)
#define QSERDES3_RX_RX_IDAC_IBAR_DC_OFFSETS	(QSERDES3_RX + 0x8C)
#define QSERDES3_RX_RX_IDAC_Q_DC_OFFSETS	(QSERDES3_RX + 0x90)
#define QSERDES3_RX_RX_IDAC_QBAR_DC_OFFSETS	(QSERDES3_RX + 0x94)
#define QSERDES3_RX_RX_IDAC_A_DC_OFFSETS	(QSERDES3_RX + 0x98)
#define QSERDES3_RX_RX_IDAC_ABAR_DC_OFFSETS	(QSERDES3_RX + 0x9C)
#define QSERDES3_RX_RX_IDAC_EN	(QSERDES3_RX + 0xA0)
#define QSERDES3_RX_RX_IDAC_ENABLES	(QSERDES3_RX + 0xA4)
#define QSERDES3_RX_RX_IDAC_SIGN	(QSERDES3_RX + 0xA8)
#define QSERDES3_RX_RX_HIGHZ_HIGHRATE	(QSERDES3_RX + 0xAC)
#define QSERDES3_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	(QSERDES3_RX + 0xB0)
#define QSERDES3_RX_DFE_1	(QSERDES3_RX + 0xB4)
#define QSERDES3_RX_DFE_2	(QSERDES3_RX + 0xB8)
#define QSERDES3_RX_DFE_3	(QSERDES3_RX + 0xBC)
#define QSERDES3_RX_DFE_4	(QSERDES3_RX + 0xC0)
#define QSERDES3_RX_TX_ADAPT_PRE_THRESH1	(QSERDES3_RX + 0xC4)
#define QSERDES3_RX_TX_ADAPT_PRE_THRESH2	(QSERDES3_RX + 0xC8)
#define QSERDES3_RX_TX_ADAPT_POST_THRESH	(QSERDES3_RX + 0xCC)
#define QSERDES3_RX_TX_ADAPT_MAIN_THRESH	(QSERDES3_RX + 0xD0)
#define QSERDES3_RX_VGA_CAL_CNTRL1	(QSERDES3_RX + 0xD4)
#define QSERDES3_RX_VGA_CAL_CNTRL2	(QSERDES3_RX + 0xD8)
#define QSERDES3_RX_GM_CAL	(QSERDES3_RX + 0xDC)
#define QSERDES3_RX_RX_VGA_GAIN2_LSB	(QSERDES3_RX + 0xE0)
#define QSERDES3_RX_RX_VGA_GAIN2_MSB	(QSERDES3_RX + 0xE4)
#define QSERDES3_RX_RX_EQU_ADAPTOR_CNTRL1	(QSERDES3_RX + 0xE8)
#define QSERDES3_RX_RX_EQU_ADAPTOR_CNTRL2	(QSERDES3_RX + 0xEC)
#define QSERDES3_RX_RX_EQU_ADAPTOR_CNTRL3	(QSERDES3_RX + 0xF0)
#define QSERDES3_RX_RX_EQU_ADAPTOR_CNTRL4	(QSERDES3_RX + 0xF4)
#define QSERDES3_RX_RX_IDAC_TSETTLE_LOW	(QSERDES3_RX + 0xF8)
#define QSERDES3_RX_RX_IDAC_TSETTLE_HIGH	(QSERDES3_RX + 0xFC)
#define QSERDES3_RX_RX_IDAC_MEASURE_TIME	(QSERDES3_RX + 0x100)
#define QSERDES3_RX_RX_IDAC_ACCUMULATOR	(QSERDES3_RX + 0x104)
#define QSERDES3_RX_RX_EQ_OFFSET_LSB	(QSERDES3_RX + 0x108)
#define QSERDES3_RX_RX_EQ_OFFSET_MSB	(QSERDES3_RX + 0x10C)
#define QSERDES3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	(QSERDES3_RX + 0x110)
#define QSERDES3_RX_RX_OFFSET_ADAPTOR_CNTRL2	(QSERDES3_RX + 0x114)
#define QSERDES3_RX_SIGDET_ENABLES	(QSERDES3_RX + 0x118)
#define QSERDES3_RX_SIGDET_CNTRL	(QSERDES3_RX + 0x11C)
#define QSERDES3_RX_SIGDET_LVL	(QSERDES3_RX + 0x120)
#define QSERDES3_RX_SIGDET_DEGLITCH_CNTRL	(QSERDES3_RX + 0x124)
#define QSERDES3_RX_RX_BAND	(QSERDES3_RX + 0x128)
#define QSERDES3_RX_CDR_FREEZE_UP_DN	(QSERDES3_RX + 0x12C)
#define QSERDES3_RX_CDR_RESET_OVERRIDE	(QSERDES3_RX + 0x130)
#define QSERDES3_RX_RX_INTERFACE_MODE	(QSERDES3_RX + 0x134)
#define QSERDES3_RX_JITTER_GEN_MODE	(QSERDES3_RX + 0x138)
#define QSERDES3_RX_SJ_AMP1	(QSERDES3_RX + 0x13C)
#define QSERDES3_RX_SJ_AMP2	(QSERDES3_RX + 0x140)
#define QSERDES3_RX_SJ_PER1	(QSERDES3_RX + 0x144)
#define QSERDES3_RX_SJ_PER2	(QSERDES3_RX + 0x148)
#define QSERDES3_RX_PPM_OFFSET1	(QSERDES3_RX + 0x14C)
#define QSERDES3_RX_PPM_OFFSET2	(QSERDES3_RX + 0x150)
#define QSERDES3_RX_SIGN_PPM_PERIOD1	(QSERDES3_RX + 0x154)
#define QSERDES3_RX_SIGN_PPM_PERIOD2	(QSERDES3_RX + 0x158)
#define QSERDES3_RX_RX_MODE_00_LOW	(QSERDES3_RX + 0x15C)
#define QSERDES3_RX_RX_MODE_00_HIGH	(QSERDES3_RX + 0x160)
#define QSERDES3_RX_RX_MODE_00_HIGH2	(QSERDES3_RX + 0x164)
#define QSERDES3_RX_RX_MODE_00_HIGH3	(QSERDES3_RX + 0x168)
#define QSERDES3_RX_RX_MODE_00_HIGH4	(QSERDES3_RX + 0x16C)
#define QSERDES3_RX_RX_MODE_01_LOW	(QSERDES3_RX + 0x170)
#define QSERDES3_RX_RX_MODE_01_HIGH	(QSERDES3_RX + 0x174)
#define QSERDES3_RX_RX_MODE_01_HIGH2	(QSERDES3_RX + 0x178)
#define QSERDES3_RX_RX_MODE_01_HIGH3	(QSERDES3_RX + 0x17C)
#define QSERDES3_RX_RX_MODE_01_HIGH4	(QSERDES3_RX + 0x180)
#define QSERDES3_RX_RX_MODE_10_LOW	(QSERDES3_RX + 0x184)
#define QSERDES3_RX_RX_MODE_10_HIGH	(QSERDES3_RX + 0x188)
#define QSERDES3_RX_RX_MODE_10_HIGH2	(QSERDES3_RX + 0x18C)
#define QSERDES3_RX_RX_MODE_10_HIGH3	(QSERDES3_RX + 0x190)
#define QSERDES3_RX_RX_MODE_10_HIGH4	(QSERDES3_RX + 0x194)
#define QSERDES3_RX_PHPRE_CTRL	(QSERDES3_RX + 0x198)
#define QSERDES3_RX_PHPRE_INITVAL	(QSERDES3_RX + 0x19C)
#define QSERDES3_RX_DFE_EN_TIMER	(QSERDES3_RX + 0x1A0)
#define QSERDES3_RX_DFE_CTLE_POST_CAL_OFFSET	(QSERDES3_RX + 0x1A4)
#define QSERDES3_RX_DCC_CTRL1	(QSERDES3_RX + 0x1A8)
#define QSERDES3_RX_DCC_CTRL2	(QSERDES3_RX + 0x1AC)
#define QSERDES3_RX_VTH_CODE	(QSERDES3_RX + 0x1B0)
#define QSERDES3_RX_VTH_MIN_THRESH	(QSERDES3_RX + 0x1B4)
#define QSERDES3_RX_VTH_MAX_THRESH	(QSERDES3_RX + 0x1B8)
#define QSERDES3_RX_ALOG_OBSV_BUS_CTRL_1	(QSERDES3_RX + 0x1BC)
#define QSERDES3_RX_PI_CTRL1	(QSERDES3_RX + 0x1C0)
#define QSERDES3_RX_PI_CTRL2	(QSERDES3_RX + 0x1C4)
#define QSERDES3_RX_PI_QUAD	(QSERDES3_RX + 0x1C8)
#define QSERDES3_RX_IDATA1	(QSERDES3_RX + 0x1CC)
#define QSERDES3_RX_IDATA2	(QSERDES3_RX + 0x1D0)
#define QSERDES3_RX_AUX_DATA1	(QSERDES3_RX + 0x1D4)
#define QSERDES3_RX_AUX_DATA2	(QSERDES3_RX + 0x1D8)
#define QSERDES3_RX_AC_JTAG_OUTP	(QSERDES3_RX + 0x1DC)
#define QSERDES3_RX_AC_JTAG_OUTN	(QSERDES3_RX + 0x1E0)
#define QSERDES3_RX_RX_SIGDET	(QSERDES3_RX + 0x1E4)
#define QSERDES3_RX_ALOG_OBSV_BUS_STATUS_1	(QSERDES3_RX + 0x1E8)

#define QSERDES3_TX	0x400
#define QSERDES3_TX_BIST_MODE_LANENO	(QSERDES3_TX + 0x0)
#define QSERDES3_TX_BIST_INVERT	(QSERDES3_TX + 0x4)
#define QSERDES3_TX_CLKBUF_ENABLE	(QSERDES3_TX + 0x8)
#define QSERDES3_TX_TX_EMP_POST1_LVL	(QSERDES3_TX + 0xC)
#define QSERDES3_TX_TX_IDLE_LVL_LARGE_AMP	(QSERDES3_TX + 0x10)
#define QSERDES3_TX_TX_DRV_LVL	(QSERDES3_TX + 0x14)
#define QSERDES3_TX_TX_DRV_LVL_OFFSET	(QSERDES3_TX + 0x18)
#define QSERDES3_TX_RESET_TSYNC_EN	(QSERDES3_TX + 0x1C)
#define QSERDES3_TX_PRE_STALL_LDO_BOOST_EN	(QSERDES3_TX + 0x20)
#define QSERDES3_TX_TX_BAND	(QSERDES3_TX + 0x24)
#define QSERDES3_TX_SLEW_CNTL	(QSERDES3_TX + 0x28)
#define QSERDES3_TX_INTERFACE_SELECT	(QSERDES3_TX + 0x2C)
#define QSERDES3_TX_LPB_EN	(QSERDES3_TX + 0x30)
#define QSERDES3_TX_RES_CODE_LANE_TX	(QSERDES3_TX + 0x34)
#define QSERDES3_TX_RES_CODE_LANE_RX	(QSERDES3_TX + 0x38)
#define QSERDES3_TX_RES_CODE_LANE_OFFSET_TX	(QSERDES3_TX + 0x3C)
#define QSERDES3_TX_RES_CODE_LANE_OFFSET_RX	(QSERDES3_TX + 0x40)
#define QSERDES3_TX_PERL_LENGTH1	(QSERDES3_TX + 0x44)
#define QSERDES3_TX_PERL_LENGTH2	(QSERDES3_TX + 0x48)
#define QSERDES3_TX_SERDES_BYP_EN_OUT	(QSERDES3_TX + 0x4C)
#define QSERDES3_TX_DEBUG_BUS_SEL	(QSERDES3_TX + 0x50)
#define QSERDES3_TX_TRANSCEIVER_BIAS_EN	(QSERDES3_TX + 0x54)
#define QSERDES3_TX_HIGHZ_DRVR_EN	(QSERDES3_TX + 0x58)
#define QSERDES3_TX_TX_POL_INV	(QSERDES3_TX + 0x5C)
#define QSERDES3_TX_PARRATE_REC_DETECT_IDLE_EN	(QSERDES3_TX + 0x60)
#define QSERDES3_TX_BIST_PATTERN1	(QSERDES3_TX + 0x64)
#define QSERDES3_TX_BIST_PATTERN2	(QSERDES3_TX + 0x68)
#define QSERDES3_TX_BIST_PATTERN3	(QSERDES3_TX + 0x6C)
#define QSERDES3_TX_BIST_PATTERN4	(QSERDES3_TX + 0x70)
#define QSERDES3_TX_BIST_PATTERN5	(QSERDES3_TX + 0x74)
#define QSERDES3_TX_BIST_PATTERN6	(QSERDES3_TX + 0x78)
#define QSERDES3_TX_BIST_PATTERN7	(QSERDES3_TX + 0x7C)
#define QSERDES3_TX_BIST_PATTERN8	(QSERDES3_TX + 0x80)
#define QSERDES3_TX_LANE_MODE_1	(QSERDES3_TX + 0x84)
#define QSERDES3_TX_LANE_MODE_2	(QSERDES3_TX + 0x88)
#define QSERDES3_TX_LANE_MODE_3	(QSERDES3_TX + 0x8C)
#define QSERDES3_TX_LANE_MODE_4	(QSERDES3_TX + 0x90)
#define QSERDES3_TX_LANE_MODE_5	(QSERDES3_TX + 0x94)
#define QSERDES3_TX_ATB_SEL1	(QSERDES3_TX + 0x98)
#define QSERDES3_TX_ATB_SEL2	(QSERDES3_TX + 0x9C)
#define QSERDES3_TX_RCV_DETECT_LVL	(QSERDES3_TX + 0xA0)
#define QSERDES3_TX_RCV_DETECT_LVL_2	(QSERDES3_TX + 0xA4)
#define QSERDES3_TX_PRBS_SEED1	(QSERDES3_TX + 0xA8)
#define QSERDES3_TX_PRBS_SEED2	(QSERDES3_TX + 0xAC)
#define QSERDES3_TX_PRBS_SEED3	(QSERDES3_TX + 0xB0)
#define QSERDES3_TX_PRBS_SEED4	(QSERDES3_TX + 0xB4)
#define QSERDES3_TX_RESET_GEN	(QSERDES3_TX + 0xB8)
#define QSERDES3_TX_RESET_GEN_MUXES	(QSERDES3_TX + 0xBC)
#define QSERDES3_TX_TRAN_DRVR_EMP_EN	(QSERDES3_TX + 0xC0)
#define QSERDES3_TX_TX_INTERFACE_MODE	(QSERDES3_TX + 0xC4)
#define QSERDES3_TX_VMODE_CTRL1	(QSERDES3_TX + 0xC8)
#define QSERDES3_TX_ALOG_OBSV_BUS_CTRL_1	(QSERDES3_TX + 0xCC)
#define QSERDES3_TX_BIST_STATUS	(QSERDES3_TX + 0xD0)
#define QSERDES3_TX_BIST_ERROR_COUNT1	(QSERDES3_TX + 0xD4)
#define QSERDES3_TX_BIST_ERROR_COUNT2	(QSERDES3_TX + 0xD8)
#define QSERDES3_TX_ALOG_OBSV_BUS_STATUS_1	(QSERDES3_TX + 0xDC)
#define QSERDES3_TX_LANE_DIG_CONFIG	(QSERDES3_TX + 0xE0)
#define QSERDES3_TX_PI_QEC_CTRL	(QSERDES3_TX + 0xE4)
#define QSERDES3_TX_PRE_EMPH	(QSERDES3_TX + 0xE8)
#define QSERDES3_TX_SW_RESET	(QSERDES3_TX + 0xEC)
#define QSERDES3_TX_DCC_OFFSET	(QSERDES3_TX + 0xF0)
#define QSERDES3_TX_DCC_CMUX_POSTCAL_OFFSET	(QSERDES3_TX + 0xF4)
#define QSERDES3_TX_DCC_CMUX_CAL_CTRL1	(QSERDES3_TX + 0xF8)
#define QSERDES3_TX_DCC_CMUX_CAL_CTRL2	(QSERDES3_TX + 0xFC)
#define QSERDES3_TX_DIG_BKUP_CTRL	(QSERDES3_TX + 0x100)
#define QSERDES3_TX_DEBUG_BUS0	(QSERDES3_TX + 0x104)
#define QSERDES3_TX_DEBUG_BUS1	(QSERDES3_TX + 0x108)
#define QSERDES3_TX_DEBUG_BUS2	(QSERDES3_TX + 0x10C)
#define QSERDES3_TX_DEBUG_BUS3	(QSERDES3_TX + 0x110)
#define QSERDES3_TX_READ_EQCODE	(QSERDES3_TX + 0x114)
#define QSERDES3_TX_READ_OFFSETCODE	(QSERDES3_TX + 0x118)
#define QSERDES3_TX_IA_ERROR_COUNTER_LOW	(QSERDES3_TX + 0x11C)
#define QSERDES3_TX_IA_ERROR_COUNTER_HIGH	(QSERDES3_TX + 0x120)
#define QSERDES3_TX_VGA_READ_CODE	(QSERDES3_TX + 0x124)
#define QSERDES3_TX_VTH_READ_CODE	(QSERDES3_TX + 0x128)
#define QSERDES3_TX_DFE_TAP1_READ_CODE	(QSERDES3_TX + 0x12C)
#define QSERDES3_TX_DFE_TAP2_READ_CODE	(QSERDES3_TX + 0x130)
#define QSERDES3_TX_IDAC_STATUS_I	(QSERDES3_TX + 0x134)
#define QSERDES3_TX_IDAC_STATUS_IBAR	(QSERDES3_TX + 0x138)
#define QSERDES3_TX_IDAC_STATUS_Q	(QSERDES3_TX + 0x13C)
#define QSERDES3_TX_IDAC_STATUS_QBAR	(QSERDES3_TX + 0x140)
#define QSERDES3_TX_IDAC_STATUS_A	(QSERDES3_TX + 0x144)
#define QSERDES3_TX_IDAC_STATUS_ABAR	(QSERDES3_TX + 0x148)
#define QSERDES3_TX_IDAC_STATUS_SM_ON	(QSERDES3_TX + 0x14C)
#define QSERDES3_TX_IDAC_STATUS_CAL_DONE	(QSERDES3_TX + 0x150)
#define QSERDES3_TX_IDAC_STATUS_SIGNERROR	(QSERDES3_TX + 0x154)
#define QSERDES3_TX_DCC_CAL_STATUS	(QSERDES3_TX + 0x158)
#define QSERDES3_TX_DCC_READ_CODE_STATUS	(QSERDES3_TX + 0x15C)

#define QSERDES3_PCS	0xC00
#define QSERDES3_PCS_PHY_START (QSERDES3_PCS + 0x0)
#define QSERDES3_PCS_POWER_DOWN_CONTROL (QSERDES3_PCS + 0x4)
#define QSERDES3_PCS_SW_RESET (QSERDES3_PCS + 0x8)
#define QSERDES3_PCS_LINE_RESET_TIME (QSERDES3_PCS + 0xC)
#define QSERDES3_PCS_PCS_CTRL1 (QSERDES3_PCS + 0x10)
#define QSERDES3_PCS_TSYNC_RSYNC_CNTL (QSERDES3_PCS + 0x14)
#define QSERDES3_PCS_RETIME_BUFFER_EN (QSERDES3_PCS + 0x18)
#define QSERDES3_PCS_PLL_CNTL (QSERDES3_PCS + 0x1C)
#define QSERDES3_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES3_PCS + 0x20)
#define QSERDES3_PCS_TX_LARGE_AMP_POST_EMP_LVL (QSERDES3_PCS + 0x24)
#define QSERDES3_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES3_PCS + 0x28)
#define QSERDES3_PCS_TX_SMALL_AMP_POST_EMP_LVL (QSERDES3_PCS + 0x2C)
#define QSERDES3_PCS_RX_SYNC_WAIT_TIME (QSERDES3_PCS + 0x30)
#define QSERDES3_PCS_L0_BIST_CTRL (QSERDES3_PCS + 0x34)
#define QSERDES3_PCS_MISC_BIST_CTRL (QSERDES3_PCS + 0x38)
#define QSERDES3_PCS_BIST_PRBS_POLY0 (QSERDES3_PCS + 0x3C)
#define QSERDES3_PCS_BIST_PRBS_POLY1 (QSERDES3_PCS + 0x40)
#define QSERDES3_PCS_BIST_PRBS_SEED0 (QSERDES3_PCS + 0x44)
#define QSERDES3_PCS_BIST_PRBS_SEED1 (QSERDES3_PCS + 0x48)
#define QSERDES3_PCS_BIST_PRBS_SEED2 (QSERDES3_PCS + 0x4C)
#define QSERDES3_PCS_BIST_NUM_IPG (QSERDES3_PCS + 0x50)
#define QSERDES3_PCS_RX_HS_EQUALIZER_SETTING_CAPABILITY (QSERDES3_PCS + 0x54)
#define QSERDES3_PCS_RX_HS_ADAPT_LENGTH_REFRESH_CAPABILITY (QSERDES3_PCS + 0x58)
#define QSERDES3_PCS_RX_HS_ADAPT_LENGTH_INITIAL_CAPABILITY (QSERDES3_PCS + 0x5C)
#define QSERDES3_PCS_DEBUG_BUS_CLKSEL (QSERDES3_PCS + 0x60)
#define QSERDES3_PCS_DEBUG_BUS_0_CTRL (QSERDES3_PCS + 0x64)
#define QSERDES3_PCS_DEBUG_BUS_1_CTRL (QSERDES3_PCS + 0x68)
#define QSERDES3_PCS_DEBUG_BUS_2_CTRL (QSERDES3_PCS + 0x6C)
#define QSERDES3_PCS_DEBUG_BUS_3_CTRL (QSERDES3_PCS + 0x70)
#define QSERDES3_PCS_DEBUG_BUS_0_STATUS_CHK (QSERDES3_PCS + 0x74)
#define QSERDES3_PCS_DEBUG_BUS_1_STATUS_CHK (QSERDES3_PCS + 0x78)
#define QSERDES3_PCS_DEBUG_BUS_2_STATUS_CHK (QSERDES3_PCS + 0x7C)
#define QSERDES3_PCS_DEBUG_BUS_3_STATUS_CHK (QSERDES3_PCS + 0x80)
#define QSERDES3_PCS_RX_MIN_HIBERN8_TIME (QSERDES3_PCS + 0x84)
#define QSERDES3_PCS_RX_SIGDET_CTRL1 (QSERDES3_PCS + 0x88)
#define QSERDES3_PCS_RX_SIGDET_CTRL2 (QSERDES3_PCS + 0x8C)
#define QSERDES3_PCS_TCLK_SYM_CNTR_INITVAL (QSERDES3_PCS + 0x90)
#define QSERDES3_PCS_PCS_READY_STATUS (QSERDES3_PCS + 0x94)
#define QSERDES3_PCS_PCS_MISC_STATUS (QSERDES3_PCS + 0x98)
#define QSERDES3_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS (QSERDES3_PCS + 0x9C)
#define QSERDES3_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS (QSERDES3_PCS + 0xA0)
#define QSERDES3_PCS_L0_BIST_CHK_STATUS (QSERDES3_PCS + 0xA4)
#define QSERDES3_PCS_DEBUG_BUS_0_STATUS (QSERDES3_PCS + 0xA8)
#define QSERDES3_PCS_DEBUG_BUS_1_STATUS (QSERDES3_PCS + 0xAC)
#define QSERDES3_PCS_DEBUG_BUS_2_STATUS (QSERDES3_PCS + 0xB0)
#define QSERDES3_PCS_DEBUG_BUS_3_STATUS (QSERDES3_PCS + 0xB4)
#define QSERDES3_PCS_REVISION_ID0 (QSERDES3_PCS + 0xB8)
#define QSERDES3_PCS_REVISION_ID1 (QSERDES3_PCS + 0xBC)
#define QSERDES3_PCS_REVISION_ID2 (QSERDES3_PCS + 0xC0)
#define QSERDES3_PCS_REVISION_ID3 (QSERDES3_PCS + 0xC4)
#define QSERDES3_PCS_SYSCLK_EN_COUNT_CTRL (QSERDES3_PCS + 0xC8)
#define QSERDES3_PCS_PLL_SHUTDOWN_CTRL (QSERDES3_PCS + 0xCC)
#define QSERDES3_PCS_TIMER_20US_CORECLK_STEPS_MSB (QSERDES3_PCS + 0xD0)
#define QSERDES3_PCS_TIMER_20US_CORECLK_STEPS_LSB (QSERDES3_PCS + 0xD4)
#define QSERDES3_PCS_TX_MID_TERM_CTRL1 (QSERDES3_PCS + 0xD8)
#define QSERDES3_PCS_TX_MID_TERM_CTRL2 (QSERDES3_PCS + 0xDC)
#define QSERDES3_PCS_MULTI_LANE_CTRL1 (QSERDES3_PCS + 0xE0)
#define QSERDES3_PCS_L1_BIST_CTRL (QSERDES3_PCS + 0xE4)
#define QSERDES3_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS (QSERDES3_PCS + 0xE8)
#define QSERDES3_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS (QSERDES3_PCS + 0xEC)
#define QSERDES3_PCS_L1_BIST_CHK_STATUS (QSERDES3_PCS + 0xF0)
#define QSERDES3_PCS_STATUS_CLEAR (QSERDES3_PCS + 0xF4)
#define QSERDES3_PCS_RX_HSG4_SYNC_WAIT_TIME (QSERDES3_PCS + 0xF8)
#define QSERDES3_PCS_SGMII_MISC_CTRL1 (QSERDES3_PCS + 0xFC)
#define QSERDES3_PCS_SGMII_MISC_CTRL2 (QSERDES3_PCS + 0x100)
#define QSERDES3_PCS_SGMII_MISC_CTRL3 (QSERDES3_PCS + 0x104)
#define QSERDES3_PCS_SGMII_MISC_CTRL4 (QSERDES3_PCS + 0x108)
#define QSERDES3_PCS_SGMII_MISC_CTRL5 (QSERDES3_PCS + 0x10C)
#define QSERDES3_PCS_SGMII_MISC_CTRL6 (QSERDES3_PCS + 0x110)
#define QSERDES3_PCS_SGMII_MISC_CTRL7 (QSERDES3_PCS + 0x114)
#define QSERDES3_PCS_SGMII_MISC_CTRL8 (QSERDES3_PCS + 0x118)
#define QSERDES3_PCS_SGMII_INTERRUPT_STATUS (QSERDES3_PCS + 0x11C)
#define QSERDES3_PCS_SGMII_IRQ_CLEAR (QSERDES3_PCS + 0x120)
#define QSERDES3_PCS_SGMII_IRQ_MASK (QSERDES3_PCS + 0x124)

#define QSERDES3_PCS_2	0x200
#define QSERDES3_PCS2_PCS_CMN_STATUS (QSERDES3_PCS_2 + 0x0)
#define QSERDES3_PCS2_TCLK_CTRL_STATUS (QSERDES3_PCS_2 + 0x4)
#define QSERDES3_PCS2_TX_LANE0_0_STATUS (QSERDES3_PCS_2 + 0x8)
#define QSERDES3_PCS2_TX_LANE0_1_STATUS (QSERDES3_PCS_2 + 0xC)
#define QSERDES3_PCS2_TX_LANE0_2_STATUS (QSERDES3_PCS_2 + 0x10)
#define QSERDES3_PCS2_RX_LANE0_0_STATUS (QSERDES3_PCS_2 + 0x14)
#define QSERDES3_PCS2_RX_LANE0_1_STATUS (QSERDES3_PCS_2 + 0x18)
#define QSERDES3_PCS2_RX_LANE0_3_STATUS (QSERDES3_PCS_2 + 0x1C)
#define QSERDES3_PCS2_TX_LANE1_0_STATUS (QSERDES3_PCS_2 + 0x20)
#define QSERDES3_PCS2_TX_LANE1_1_STATUS (QSERDES3_PCS_2 + 0x24)
#define QSERDES3_PCS2_TX_LANE1_2_STATUS (QSERDES3_PCS_2 + 0x28)
#define QSERDES3_PCS2_RX_LANE1_0_STATUS (QSERDES3_PCS_2 + 0x2C)
#define QSERDES3_PCS2_RX_LANE1_1_STATUS (QSERDES3_PCS_2 + 0x30)
#define QSERDES3_PCS2_RX_LANE1_3_STATUS (QSERDES3_PCS_2 + 0x34)

#define QSERDES3_COM_C_READY BIT(0)
#define QSERDES3_PCS_READY BIT(0)
#define QSERDES3_PCS_SGMIIPHY_READY BIT(7)
#define QSERDES3_COM_C_PLL_LOCKED BIT(1)

#if IS_ENABLED(CONFIG_ETHQOS_QCOM_SERDES)
int qcom_ethqos_serdes_configure_dt(struct qcom_ethqos *ethqos);
int qcom_ethqos_serdes_update(struct qcom_ethqos *ethqos,
			      int speed,
			      int interface);
#else
static inline int qcom_ethqos_serdes_configure_dt(struct qcom_ethqos *ethqos)
{
	return 0;
}

static inline int qcom_ethqos_serdes_update(struct qcom_ethqos *ethqos,
					    int speed,
					    int interface)
{
	return 0;
}
#endif

#endif /*_DWMAC_QCOM_SERDES_H*/