lan743x_main.c 102 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* Copyright (C) 2018 Microchip Technology Inc. */
  3. #include <linux/module.h>
  4. #include <linux/pci.h>
  5. #include <linux/netdevice.h>
  6. #include <linux/etherdevice.h>
  7. #include <linux/crc32.h>
  8. #include <linux/microchipphy.h>
  9. #include <linux/net_tstamp.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/of_net.h>
  12. #include <linux/phy.h>
  13. #include <linux/phy_fixed.h>
  14. #include <linux/rtnetlink.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/crc16.h>
  17. #include "lan743x_main.h"
  18. #include "lan743x_ethtool.h"
  19. #define MMD_ACCESS_ADDRESS 0
  20. #define MMD_ACCESS_WRITE 1
  21. #define MMD_ACCESS_READ 2
  22. #define MMD_ACCESS_READ_INC 3
  23. #define PCS_POWER_STATE_DOWN 0x6
  24. #define PCS_POWER_STATE_UP 0x4
  25. static void pci11x1x_strap_get_status(struct lan743x_adapter *adapter)
  26. {
  27. u32 chip_rev;
  28. u32 cfg_load;
  29. u32 hw_cfg;
  30. u32 strap;
  31. int ret;
  32. /* Timeout = 100 (i.e. 1 sec (10 msce * 100)) */
  33. ret = lan743x_hs_syslock_acquire(adapter, 100);
  34. if (ret < 0) {
  35. netif_err(adapter, drv, adapter->netdev,
  36. "Sys Lock acquire failed ret:%d\n", ret);
  37. return;
  38. }
  39. cfg_load = lan743x_csr_read(adapter, ETH_SYS_CONFIG_LOAD_STARTED_REG);
  40. lan743x_hs_syslock_release(adapter);
  41. hw_cfg = lan743x_csr_read(adapter, HW_CFG);
  42. if (cfg_load & GEN_SYS_LOAD_STARTED_REG_ETH_ ||
  43. hw_cfg & HW_CFG_RST_PROTECT_) {
  44. strap = lan743x_csr_read(adapter, STRAP_READ);
  45. if (strap & STRAP_READ_SGMII_EN_)
  46. adapter->is_sgmii_en = true;
  47. else
  48. adapter->is_sgmii_en = false;
  49. } else {
  50. chip_rev = lan743x_csr_read(adapter, FPGA_REV);
  51. if (chip_rev) {
  52. if (chip_rev & FPGA_SGMII_OP)
  53. adapter->is_sgmii_en = true;
  54. else
  55. adapter->is_sgmii_en = false;
  56. } else {
  57. adapter->is_sgmii_en = false;
  58. }
  59. }
  60. netif_dbg(adapter, drv, adapter->netdev,
  61. "SGMII I/F %sable\n", adapter->is_sgmii_en ? "En" : "Dis");
  62. }
  63. static bool is_pci11x1x_chip(struct lan743x_adapter *adapter)
  64. {
  65. struct lan743x_csr *csr = &adapter->csr;
  66. u32 id_rev = csr->id_rev;
  67. if (((id_rev & 0xFFFF0000) == ID_REV_ID_A011_) ||
  68. ((id_rev & 0xFFFF0000) == ID_REV_ID_A041_)) {
  69. return true;
  70. }
  71. return false;
  72. }
  73. static void lan743x_pci_cleanup(struct lan743x_adapter *adapter)
  74. {
  75. pci_release_selected_regions(adapter->pdev,
  76. pci_select_bars(adapter->pdev,
  77. IORESOURCE_MEM));
  78. pci_disable_device(adapter->pdev);
  79. }
  80. static int lan743x_pci_init(struct lan743x_adapter *adapter,
  81. struct pci_dev *pdev)
  82. {
  83. unsigned long bars = 0;
  84. int ret;
  85. adapter->pdev = pdev;
  86. ret = pci_enable_device_mem(pdev);
  87. if (ret)
  88. goto return_error;
  89. netif_info(adapter, probe, adapter->netdev,
  90. "PCI: Vendor ID = 0x%04X, Device ID = 0x%04X\n",
  91. pdev->vendor, pdev->device);
  92. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  93. if (!test_bit(0, &bars))
  94. goto disable_device;
  95. ret = pci_request_selected_regions(pdev, bars, DRIVER_NAME);
  96. if (ret)
  97. goto disable_device;
  98. pci_set_master(pdev);
  99. return 0;
  100. disable_device:
  101. pci_disable_device(adapter->pdev);
  102. return_error:
  103. return ret;
  104. }
  105. u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset)
  106. {
  107. return ioread32(&adapter->csr.csr_address[offset]);
  108. }
  109. void lan743x_csr_write(struct lan743x_adapter *adapter, int offset,
  110. u32 data)
  111. {
  112. iowrite32(data, &adapter->csr.csr_address[offset]);
  113. }
  114. #define LAN743X_CSR_READ_OP(offset) lan743x_csr_read(adapter, offset)
  115. static int lan743x_csr_light_reset(struct lan743x_adapter *adapter)
  116. {
  117. u32 data;
  118. data = lan743x_csr_read(adapter, HW_CFG);
  119. data |= HW_CFG_LRST_;
  120. lan743x_csr_write(adapter, HW_CFG, data);
  121. return readx_poll_timeout(LAN743X_CSR_READ_OP, HW_CFG, data,
  122. !(data & HW_CFG_LRST_), 100000, 10000000);
  123. }
  124. static int lan743x_csr_wait_for_bit_atomic(struct lan743x_adapter *adapter,
  125. int offset, u32 bit_mask,
  126. int target_value, int udelay_min,
  127. int udelay_max, int count)
  128. {
  129. u32 data;
  130. return readx_poll_timeout_atomic(LAN743X_CSR_READ_OP, offset, data,
  131. target_value == !!(data & bit_mask),
  132. udelay_max, udelay_min * count);
  133. }
  134. static int lan743x_csr_wait_for_bit(struct lan743x_adapter *adapter,
  135. int offset, u32 bit_mask,
  136. int target_value, int usleep_min,
  137. int usleep_max, int count)
  138. {
  139. u32 data;
  140. return readx_poll_timeout(LAN743X_CSR_READ_OP, offset, data,
  141. target_value == ((data & bit_mask) ? 1 : 0),
  142. usleep_max, usleep_min * count);
  143. }
  144. static int lan743x_csr_init(struct lan743x_adapter *adapter)
  145. {
  146. struct lan743x_csr *csr = &adapter->csr;
  147. resource_size_t bar_start, bar_length;
  148. int result;
  149. bar_start = pci_resource_start(adapter->pdev, 0);
  150. bar_length = pci_resource_len(adapter->pdev, 0);
  151. csr->csr_address = devm_ioremap(&adapter->pdev->dev,
  152. bar_start, bar_length);
  153. if (!csr->csr_address) {
  154. result = -ENOMEM;
  155. goto clean_up;
  156. }
  157. csr->id_rev = lan743x_csr_read(adapter, ID_REV);
  158. csr->fpga_rev = lan743x_csr_read(adapter, FPGA_REV);
  159. netif_info(adapter, probe, adapter->netdev,
  160. "ID_REV = 0x%08X, FPGA_REV = %d.%d\n",
  161. csr->id_rev, FPGA_REV_GET_MAJOR_(csr->fpga_rev),
  162. FPGA_REV_GET_MINOR_(csr->fpga_rev));
  163. if (!ID_REV_IS_VALID_CHIP_ID_(csr->id_rev)) {
  164. result = -ENODEV;
  165. goto clean_up;
  166. }
  167. csr->flags = LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR;
  168. switch (csr->id_rev & ID_REV_CHIP_REV_MASK_) {
  169. case ID_REV_CHIP_REV_A0_:
  170. csr->flags |= LAN743X_CSR_FLAG_IS_A0;
  171. csr->flags &= ~LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR;
  172. break;
  173. case ID_REV_CHIP_REV_B0_:
  174. csr->flags |= LAN743X_CSR_FLAG_IS_B0;
  175. break;
  176. }
  177. result = lan743x_csr_light_reset(adapter);
  178. if (result)
  179. goto clean_up;
  180. return 0;
  181. clean_up:
  182. return result;
  183. }
  184. static void lan743x_intr_software_isr(struct lan743x_adapter *adapter)
  185. {
  186. struct lan743x_intr *intr = &adapter->intr;
  187. /* disable the interrupt to prevent repeated re-triggering */
  188. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_SW_GP_);
  189. intr->software_isr_flag = true;
  190. wake_up(&intr->software_isr_wq);
  191. }
  192. static void lan743x_tx_isr(void *context, u32 int_sts, u32 flags)
  193. {
  194. struct lan743x_tx *tx = context;
  195. struct lan743x_adapter *adapter = tx->adapter;
  196. bool enable_flag = true;
  197. lan743x_csr_read(adapter, INT_EN_SET);
  198. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR) {
  199. lan743x_csr_write(adapter, INT_EN_CLR,
  200. INT_BIT_DMA_TX_(tx->channel_number));
  201. }
  202. if (int_sts & INT_BIT_DMA_TX_(tx->channel_number)) {
  203. u32 ioc_bit = DMAC_INT_BIT_TX_IOC_(tx->channel_number);
  204. u32 dmac_int_sts;
  205. u32 dmac_int_en;
  206. if (flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ)
  207. dmac_int_sts = lan743x_csr_read(adapter, DMAC_INT_STS);
  208. else
  209. dmac_int_sts = ioc_bit;
  210. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK)
  211. dmac_int_en = lan743x_csr_read(adapter,
  212. DMAC_INT_EN_SET);
  213. else
  214. dmac_int_en = ioc_bit;
  215. dmac_int_en &= ioc_bit;
  216. dmac_int_sts &= dmac_int_en;
  217. if (dmac_int_sts & ioc_bit) {
  218. napi_schedule(&tx->napi);
  219. enable_flag = false;/* poll func will enable later */
  220. }
  221. }
  222. if (enable_flag)
  223. /* enable isr */
  224. lan743x_csr_write(adapter, INT_EN_SET,
  225. INT_BIT_DMA_TX_(tx->channel_number));
  226. }
  227. static void lan743x_rx_isr(void *context, u32 int_sts, u32 flags)
  228. {
  229. struct lan743x_rx *rx = context;
  230. struct lan743x_adapter *adapter = rx->adapter;
  231. bool enable_flag = true;
  232. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR) {
  233. lan743x_csr_write(adapter, INT_EN_CLR,
  234. INT_BIT_DMA_RX_(rx->channel_number));
  235. }
  236. if (int_sts & INT_BIT_DMA_RX_(rx->channel_number)) {
  237. u32 rx_frame_bit = DMAC_INT_BIT_RXFRM_(rx->channel_number);
  238. u32 dmac_int_sts;
  239. u32 dmac_int_en;
  240. if (flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ)
  241. dmac_int_sts = lan743x_csr_read(adapter, DMAC_INT_STS);
  242. else
  243. dmac_int_sts = rx_frame_bit;
  244. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK)
  245. dmac_int_en = lan743x_csr_read(adapter,
  246. DMAC_INT_EN_SET);
  247. else
  248. dmac_int_en = rx_frame_bit;
  249. dmac_int_en &= rx_frame_bit;
  250. dmac_int_sts &= dmac_int_en;
  251. if (dmac_int_sts & rx_frame_bit) {
  252. napi_schedule(&rx->napi);
  253. enable_flag = false;/* poll funct will enable later */
  254. }
  255. }
  256. if (enable_flag) {
  257. /* enable isr */
  258. lan743x_csr_write(adapter, INT_EN_SET,
  259. INT_BIT_DMA_RX_(rx->channel_number));
  260. }
  261. }
  262. static void lan743x_intr_shared_isr(void *context, u32 int_sts, u32 flags)
  263. {
  264. struct lan743x_adapter *adapter = context;
  265. unsigned int channel;
  266. if (int_sts & INT_BIT_ALL_RX_) {
  267. for (channel = 0; channel < LAN743X_USED_RX_CHANNELS;
  268. channel++) {
  269. u32 int_bit = INT_BIT_DMA_RX_(channel);
  270. if (int_sts & int_bit) {
  271. lan743x_rx_isr(&adapter->rx[channel],
  272. int_bit, flags);
  273. int_sts &= ~int_bit;
  274. }
  275. }
  276. }
  277. if (int_sts & INT_BIT_ALL_TX_) {
  278. for (channel = 0; channel < adapter->used_tx_channels;
  279. channel++) {
  280. u32 int_bit = INT_BIT_DMA_TX_(channel);
  281. if (int_sts & int_bit) {
  282. lan743x_tx_isr(&adapter->tx[channel],
  283. int_bit, flags);
  284. int_sts &= ~int_bit;
  285. }
  286. }
  287. }
  288. if (int_sts & INT_BIT_ALL_OTHER_) {
  289. if (int_sts & INT_BIT_SW_GP_) {
  290. lan743x_intr_software_isr(adapter);
  291. int_sts &= ~INT_BIT_SW_GP_;
  292. }
  293. if (int_sts & INT_BIT_1588_) {
  294. lan743x_ptp_isr(adapter);
  295. int_sts &= ~INT_BIT_1588_;
  296. }
  297. }
  298. if (int_sts)
  299. lan743x_csr_write(adapter, INT_EN_CLR, int_sts);
  300. }
  301. static irqreturn_t lan743x_intr_entry_isr(int irq, void *ptr)
  302. {
  303. struct lan743x_vector *vector = ptr;
  304. struct lan743x_adapter *adapter = vector->adapter;
  305. irqreturn_t result = IRQ_NONE;
  306. u32 int_enables;
  307. u32 int_sts;
  308. if (vector->flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ) {
  309. int_sts = lan743x_csr_read(adapter, INT_STS);
  310. } else if (vector->flags &
  311. (LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C |
  312. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C)) {
  313. int_sts = lan743x_csr_read(adapter, INT_STS_R2C);
  314. } else {
  315. /* use mask as implied status */
  316. int_sts = vector->int_mask | INT_BIT_MAS_;
  317. }
  318. if (!(int_sts & INT_BIT_MAS_))
  319. goto irq_done;
  320. if (vector->flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR)
  321. /* disable vector interrupt */
  322. lan743x_csr_write(adapter,
  323. INT_VEC_EN_CLR,
  324. INT_VEC_EN_(vector->vector_index));
  325. if (vector->flags & LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR)
  326. /* disable master interrupt */
  327. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_MAS_);
  328. if (vector->flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK) {
  329. int_enables = lan743x_csr_read(adapter, INT_EN_SET);
  330. } else {
  331. /* use vector mask as implied enable mask */
  332. int_enables = vector->int_mask;
  333. }
  334. int_sts &= int_enables;
  335. int_sts &= vector->int_mask;
  336. if (int_sts) {
  337. if (vector->handler) {
  338. vector->handler(vector->context,
  339. int_sts, vector->flags);
  340. } else {
  341. /* disable interrupts on this vector */
  342. lan743x_csr_write(adapter, INT_EN_CLR,
  343. vector->int_mask);
  344. }
  345. result = IRQ_HANDLED;
  346. }
  347. if (vector->flags & LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET)
  348. /* enable master interrupt */
  349. lan743x_csr_write(adapter, INT_EN_SET, INT_BIT_MAS_);
  350. if (vector->flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET)
  351. /* enable vector interrupt */
  352. lan743x_csr_write(adapter,
  353. INT_VEC_EN_SET,
  354. INT_VEC_EN_(vector->vector_index));
  355. irq_done:
  356. return result;
  357. }
  358. static int lan743x_intr_test_isr(struct lan743x_adapter *adapter)
  359. {
  360. struct lan743x_intr *intr = &adapter->intr;
  361. int ret;
  362. intr->software_isr_flag = false;
  363. /* enable and activate test interrupt */
  364. lan743x_csr_write(adapter, INT_EN_SET, INT_BIT_SW_GP_);
  365. lan743x_csr_write(adapter, INT_SET, INT_BIT_SW_GP_);
  366. ret = wait_event_timeout(intr->software_isr_wq,
  367. intr->software_isr_flag,
  368. msecs_to_jiffies(200));
  369. /* disable test interrupt */
  370. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_SW_GP_);
  371. return ret > 0 ? 0 : -ENODEV;
  372. }
  373. static int lan743x_intr_register_isr(struct lan743x_adapter *adapter,
  374. int vector_index, u32 flags,
  375. u32 int_mask,
  376. lan743x_vector_handler handler,
  377. void *context)
  378. {
  379. struct lan743x_vector *vector = &adapter->intr.vector_list
  380. [vector_index];
  381. int ret;
  382. vector->adapter = adapter;
  383. vector->flags = flags;
  384. vector->vector_index = vector_index;
  385. vector->int_mask = int_mask;
  386. vector->handler = handler;
  387. vector->context = context;
  388. ret = request_irq(vector->irq,
  389. lan743x_intr_entry_isr,
  390. (flags & LAN743X_VECTOR_FLAG_IRQ_SHARED) ?
  391. IRQF_SHARED : 0, DRIVER_NAME, vector);
  392. if (ret) {
  393. vector->handler = NULL;
  394. vector->context = NULL;
  395. vector->int_mask = 0;
  396. vector->flags = 0;
  397. }
  398. return ret;
  399. }
  400. static void lan743x_intr_unregister_isr(struct lan743x_adapter *adapter,
  401. int vector_index)
  402. {
  403. struct lan743x_vector *vector = &adapter->intr.vector_list
  404. [vector_index];
  405. free_irq(vector->irq, vector);
  406. vector->handler = NULL;
  407. vector->context = NULL;
  408. vector->int_mask = 0;
  409. vector->flags = 0;
  410. }
  411. static u32 lan743x_intr_get_vector_flags(struct lan743x_adapter *adapter,
  412. u32 int_mask)
  413. {
  414. int index;
  415. for (index = 0; index < adapter->max_vector_count; index++) {
  416. if (adapter->intr.vector_list[index].int_mask & int_mask)
  417. return adapter->intr.vector_list[index].flags;
  418. }
  419. return 0;
  420. }
  421. static void lan743x_intr_close(struct lan743x_adapter *adapter)
  422. {
  423. struct lan743x_intr *intr = &adapter->intr;
  424. int index = 0;
  425. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_MAS_);
  426. if (adapter->is_pci11x1x)
  427. lan743x_csr_write(adapter, INT_VEC_EN_CLR, 0x0000FFFF);
  428. else
  429. lan743x_csr_write(adapter, INT_VEC_EN_CLR, 0x000000FF);
  430. for (index = 0; index < intr->number_of_vectors; index++) {
  431. if (intr->flags & INTR_FLAG_IRQ_REQUESTED(index)) {
  432. lan743x_intr_unregister_isr(adapter, index);
  433. intr->flags &= ~INTR_FLAG_IRQ_REQUESTED(index);
  434. }
  435. }
  436. if (intr->flags & INTR_FLAG_MSI_ENABLED) {
  437. pci_disable_msi(adapter->pdev);
  438. intr->flags &= ~INTR_FLAG_MSI_ENABLED;
  439. }
  440. if (intr->flags & INTR_FLAG_MSIX_ENABLED) {
  441. pci_disable_msix(adapter->pdev);
  442. intr->flags &= ~INTR_FLAG_MSIX_ENABLED;
  443. }
  444. }
  445. static int lan743x_intr_open(struct lan743x_adapter *adapter)
  446. {
  447. struct msix_entry msix_entries[PCI11X1X_MAX_VECTOR_COUNT];
  448. struct lan743x_intr *intr = &adapter->intr;
  449. unsigned int used_tx_channels;
  450. u32 int_vec_en_auto_clr = 0;
  451. u8 max_vector_count;
  452. u32 int_vec_map0 = 0;
  453. u32 int_vec_map1 = 0;
  454. int ret = -ENODEV;
  455. int index = 0;
  456. u32 flags = 0;
  457. intr->number_of_vectors = 0;
  458. /* Try to set up MSIX interrupts */
  459. max_vector_count = adapter->max_vector_count;
  460. memset(&msix_entries[0], 0,
  461. sizeof(struct msix_entry) * max_vector_count);
  462. for (index = 0; index < max_vector_count; index++)
  463. msix_entries[index].entry = index;
  464. used_tx_channels = adapter->used_tx_channels;
  465. ret = pci_enable_msix_range(adapter->pdev,
  466. msix_entries, 1,
  467. 1 + used_tx_channels +
  468. LAN743X_USED_RX_CHANNELS);
  469. if (ret > 0) {
  470. intr->flags |= INTR_FLAG_MSIX_ENABLED;
  471. intr->number_of_vectors = ret;
  472. intr->using_vectors = true;
  473. for (index = 0; index < intr->number_of_vectors; index++)
  474. intr->vector_list[index].irq = msix_entries
  475. [index].vector;
  476. netif_info(adapter, ifup, adapter->netdev,
  477. "using MSIX interrupts, number of vectors = %d\n",
  478. intr->number_of_vectors);
  479. }
  480. /* If MSIX failed try to setup using MSI interrupts */
  481. if (!intr->number_of_vectors) {
  482. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  483. if (!pci_enable_msi(adapter->pdev)) {
  484. intr->flags |= INTR_FLAG_MSI_ENABLED;
  485. intr->number_of_vectors = 1;
  486. intr->using_vectors = true;
  487. intr->vector_list[0].irq =
  488. adapter->pdev->irq;
  489. netif_info(adapter, ifup, adapter->netdev,
  490. "using MSI interrupts, number of vectors = %d\n",
  491. intr->number_of_vectors);
  492. }
  493. }
  494. }
  495. /* If MSIX, and MSI failed, setup using legacy interrupt */
  496. if (!intr->number_of_vectors) {
  497. intr->number_of_vectors = 1;
  498. intr->using_vectors = false;
  499. intr->vector_list[0].irq = intr->irq;
  500. netif_info(adapter, ifup, adapter->netdev,
  501. "using legacy interrupts\n");
  502. }
  503. /* At this point we must have at least one irq */
  504. lan743x_csr_write(adapter, INT_VEC_EN_CLR, 0xFFFFFFFF);
  505. /* map all interrupts to vector 0 */
  506. lan743x_csr_write(adapter, INT_VEC_MAP0, 0x00000000);
  507. lan743x_csr_write(adapter, INT_VEC_MAP1, 0x00000000);
  508. lan743x_csr_write(adapter, INT_VEC_MAP2, 0x00000000);
  509. flags = LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ |
  510. LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C |
  511. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK |
  512. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR;
  513. if (intr->using_vectors) {
  514. flags |= LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR |
  515. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET;
  516. } else {
  517. flags |= LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR |
  518. LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET |
  519. LAN743X_VECTOR_FLAG_IRQ_SHARED;
  520. }
  521. if (adapter->csr.flags & LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {
  522. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ;
  523. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C;
  524. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR;
  525. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK;
  526. flags |= LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C;
  527. flags |= LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C;
  528. }
  529. init_waitqueue_head(&intr->software_isr_wq);
  530. ret = lan743x_intr_register_isr(adapter, 0, flags,
  531. INT_BIT_ALL_RX_ | INT_BIT_ALL_TX_ |
  532. INT_BIT_ALL_OTHER_,
  533. lan743x_intr_shared_isr, adapter);
  534. if (ret)
  535. goto clean_up;
  536. intr->flags |= INTR_FLAG_IRQ_REQUESTED(0);
  537. if (intr->using_vectors)
  538. lan743x_csr_write(adapter, INT_VEC_EN_SET,
  539. INT_VEC_EN_(0));
  540. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  541. lan743x_csr_write(adapter, INT_MOD_CFG0, LAN743X_INT_MOD);
  542. lan743x_csr_write(adapter, INT_MOD_CFG1, LAN743X_INT_MOD);
  543. lan743x_csr_write(adapter, INT_MOD_CFG2, LAN743X_INT_MOD);
  544. lan743x_csr_write(adapter, INT_MOD_CFG3, LAN743X_INT_MOD);
  545. lan743x_csr_write(adapter, INT_MOD_CFG4, LAN743X_INT_MOD);
  546. lan743x_csr_write(adapter, INT_MOD_CFG5, LAN743X_INT_MOD);
  547. lan743x_csr_write(adapter, INT_MOD_CFG6, LAN743X_INT_MOD);
  548. lan743x_csr_write(adapter, INT_MOD_CFG7, LAN743X_INT_MOD);
  549. if (adapter->is_pci11x1x) {
  550. lan743x_csr_write(adapter, INT_MOD_CFG8, LAN743X_INT_MOD);
  551. lan743x_csr_write(adapter, INT_MOD_CFG9, LAN743X_INT_MOD);
  552. lan743x_csr_write(adapter, INT_MOD_MAP0, 0x00007654);
  553. lan743x_csr_write(adapter, INT_MOD_MAP1, 0x00003210);
  554. } else {
  555. lan743x_csr_write(adapter, INT_MOD_MAP0, 0x00005432);
  556. lan743x_csr_write(adapter, INT_MOD_MAP1, 0x00000001);
  557. }
  558. lan743x_csr_write(adapter, INT_MOD_MAP2, 0x00FFFFFF);
  559. }
  560. /* enable interrupts */
  561. lan743x_csr_write(adapter, INT_EN_SET, INT_BIT_MAS_);
  562. ret = lan743x_intr_test_isr(adapter);
  563. if (ret)
  564. goto clean_up;
  565. if (intr->number_of_vectors > 1) {
  566. int number_of_tx_vectors = intr->number_of_vectors - 1;
  567. if (number_of_tx_vectors > used_tx_channels)
  568. number_of_tx_vectors = used_tx_channels;
  569. flags = LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ |
  570. LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C |
  571. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK |
  572. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR |
  573. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR |
  574. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET;
  575. if (adapter->csr.flags &
  576. LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {
  577. flags = LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET |
  578. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET |
  579. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR |
  580. LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR;
  581. }
  582. for (index = 0; index < number_of_tx_vectors; index++) {
  583. u32 int_bit = INT_BIT_DMA_TX_(index);
  584. int vector = index + 1;
  585. /* map TX interrupt to vector */
  586. int_vec_map1 |= INT_VEC_MAP1_TX_VEC_(index, vector);
  587. lan743x_csr_write(adapter, INT_VEC_MAP1, int_vec_map1);
  588. /* Remove TX interrupt from shared mask */
  589. intr->vector_list[0].int_mask &= ~int_bit;
  590. ret = lan743x_intr_register_isr(adapter, vector, flags,
  591. int_bit, lan743x_tx_isr,
  592. &adapter->tx[index]);
  593. if (ret)
  594. goto clean_up;
  595. intr->flags |= INTR_FLAG_IRQ_REQUESTED(vector);
  596. if (!(flags &
  597. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET))
  598. lan743x_csr_write(adapter, INT_VEC_EN_SET,
  599. INT_VEC_EN_(vector));
  600. }
  601. }
  602. if ((intr->number_of_vectors - used_tx_channels) > 1) {
  603. int number_of_rx_vectors = intr->number_of_vectors -
  604. used_tx_channels - 1;
  605. if (number_of_rx_vectors > LAN743X_USED_RX_CHANNELS)
  606. number_of_rx_vectors = LAN743X_USED_RX_CHANNELS;
  607. flags = LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ |
  608. LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C |
  609. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK |
  610. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR |
  611. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR |
  612. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET;
  613. if (adapter->csr.flags &
  614. LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {
  615. flags = LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR |
  616. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET |
  617. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET |
  618. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR |
  619. LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR;
  620. }
  621. for (index = 0; index < number_of_rx_vectors; index++) {
  622. int vector = index + 1 + used_tx_channels;
  623. u32 int_bit = INT_BIT_DMA_RX_(index);
  624. /* map RX interrupt to vector */
  625. int_vec_map0 |= INT_VEC_MAP0_RX_VEC_(index, vector);
  626. lan743x_csr_write(adapter, INT_VEC_MAP0, int_vec_map0);
  627. if (flags &
  628. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR) {
  629. int_vec_en_auto_clr |= INT_VEC_EN_(vector);
  630. lan743x_csr_write(adapter, INT_VEC_EN_AUTO_CLR,
  631. int_vec_en_auto_clr);
  632. }
  633. /* Remove RX interrupt from shared mask */
  634. intr->vector_list[0].int_mask &= ~int_bit;
  635. ret = lan743x_intr_register_isr(adapter, vector, flags,
  636. int_bit, lan743x_rx_isr,
  637. &adapter->rx[index]);
  638. if (ret)
  639. goto clean_up;
  640. intr->flags |= INTR_FLAG_IRQ_REQUESTED(vector);
  641. lan743x_csr_write(adapter, INT_VEC_EN_SET,
  642. INT_VEC_EN_(vector));
  643. }
  644. }
  645. return 0;
  646. clean_up:
  647. lan743x_intr_close(adapter);
  648. return ret;
  649. }
  650. static int lan743x_dp_write(struct lan743x_adapter *adapter,
  651. u32 select, u32 addr, u32 length, u32 *buf)
  652. {
  653. u32 dp_sel;
  654. int i;
  655. if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL, DP_SEL_DPRDY_,
  656. 1, 40, 100, 100))
  657. return -EIO;
  658. dp_sel = lan743x_csr_read(adapter, DP_SEL);
  659. dp_sel &= ~DP_SEL_MASK_;
  660. dp_sel |= select;
  661. lan743x_csr_write(adapter, DP_SEL, dp_sel);
  662. for (i = 0; i < length; i++) {
  663. lan743x_csr_write(adapter, DP_ADDR, addr + i);
  664. lan743x_csr_write(adapter, DP_DATA_0, buf[i]);
  665. lan743x_csr_write(adapter, DP_CMD, DP_CMD_WRITE_);
  666. if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL,
  667. DP_SEL_DPRDY_,
  668. 1, 40, 100, 100))
  669. return -EIO;
  670. }
  671. return 0;
  672. }
  673. static u32 lan743x_mac_mii_access(u16 id, u16 index, int read)
  674. {
  675. u32 ret;
  676. ret = (id << MAC_MII_ACC_PHY_ADDR_SHIFT_) &
  677. MAC_MII_ACC_PHY_ADDR_MASK_;
  678. ret |= (index << MAC_MII_ACC_MIIRINDA_SHIFT_) &
  679. MAC_MII_ACC_MIIRINDA_MASK_;
  680. if (read)
  681. ret |= MAC_MII_ACC_MII_READ_;
  682. else
  683. ret |= MAC_MII_ACC_MII_WRITE_;
  684. ret |= MAC_MII_ACC_MII_BUSY_;
  685. return ret;
  686. }
  687. static int lan743x_mac_mii_wait_till_not_busy(struct lan743x_adapter *adapter)
  688. {
  689. u32 data;
  690. return readx_poll_timeout(LAN743X_CSR_READ_OP, MAC_MII_ACC, data,
  691. !(data & MAC_MII_ACC_MII_BUSY_), 0, 1000000);
  692. }
  693. static int lan743x_mdiobus_read(struct mii_bus *bus, int phy_id, int index)
  694. {
  695. struct lan743x_adapter *adapter = bus->priv;
  696. u32 val, mii_access;
  697. int ret;
  698. /* comfirm MII not busy */
  699. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  700. if (ret < 0)
  701. return ret;
  702. /* set the address, index & direction (read from PHY) */
  703. mii_access = lan743x_mac_mii_access(phy_id, index, MAC_MII_READ);
  704. lan743x_csr_write(adapter, MAC_MII_ACC, mii_access);
  705. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  706. if (ret < 0)
  707. return ret;
  708. val = lan743x_csr_read(adapter, MAC_MII_DATA);
  709. return (int)(val & 0xFFFF);
  710. }
  711. static int lan743x_mdiobus_write(struct mii_bus *bus,
  712. int phy_id, int index, u16 regval)
  713. {
  714. struct lan743x_adapter *adapter = bus->priv;
  715. u32 val, mii_access;
  716. int ret;
  717. /* confirm MII not busy */
  718. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  719. if (ret < 0)
  720. return ret;
  721. val = (u32)regval;
  722. lan743x_csr_write(adapter, MAC_MII_DATA, val);
  723. /* set the address, index & direction (write to PHY) */
  724. mii_access = lan743x_mac_mii_access(phy_id, index, MAC_MII_WRITE);
  725. lan743x_csr_write(adapter, MAC_MII_ACC, mii_access);
  726. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  727. return ret;
  728. }
  729. static u32 lan743x_mac_mmd_access(int id, int index, int op)
  730. {
  731. u16 dev_addr;
  732. u32 ret;
  733. dev_addr = (index >> 16) & 0x1f;
  734. ret = (id << MAC_MII_ACC_PHY_ADDR_SHIFT_) &
  735. MAC_MII_ACC_PHY_ADDR_MASK_;
  736. ret |= (dev_addr << MAC_MII_ACC_MIIMMD_SHIFT_) &
  737. MAC_MII_ACC_MIIMMD_MASK_;
  738. if (op == MMD_ACCESS_WRITE)
  739. ret |= MAC_MII_ACC_MIICMD_WRITE_;
  740. else if (op == MMD_ACCESS_READ)
  741. ret |= MAC_MII_ACC_MIICMD_READ_;
  742. else if (op == MMD_ACCESS_READ_INC)
  743. ret |= MAC_MII_ACC_MIICMD_READ_INC_;
  744. else
  745. ret |= MAC_MII_ACC_MIICMD_ADDR_;
  746. ret |= (MAC_MII_ACC_MII_BUSY_ | MAC_MII_ACC_MIICL45_);
  747. return ret;
  748. }
  749. static int lan743x_mdiobus_c45_read(struct mii_bus *bus, int phy_id, int index)
  750. {
  751. struct lan743x_adapter *adapter = bus->priv;
  752. u32 mmd_access;
  753. int ret;
  754. /* comfirm MII not busy */
  755. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  756. if (ret < 0)
  757. return ret;
  758. if (index & MII_ADDR_C45) {
  759. /* Load Register Address */
  760. lan743x_csr_write(adapter, MAC_MII_DATA, (u32)(index & 0xffff));
  761. mmd_access = lan743x_mac_mmd_access(phy_id, index,
  762. MMD_ACCESS_ADDRESS);
  763. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  764. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  765. if (ret < 0)
  766. return ret;
  767. /* Read Data */
  768. mmd_access = lan743x_mac_mmd_access(phy_id, index,
  769. MMD_ACCESS_READ);
  770. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  771. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  772. if (ret < 0)
  773. return ret;
  774. ret = lan743x_csr_read(adapter, MAC_MII_DATA);
  775. return (int)(ret & 0xFFFF);
  776. }
  777. ret = lan743x_mdiobus_read(bus, phy_id, index);
  778. return ret;
  779. }
  780. static int lan743x_mdiobus_c45_write(struct mii_bus *bus,
  781. int phy_id, int index, u16 regval)
  782. {
  783. struct lan743x_adapter *adapter = bus->priv;
  784. u32 mmd_access;
  785. int ret;
  786. /* confirm MII not busy */
  787. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  788. if (ret < 0)
  789. return ret;
  790. if (index & MII_ADDR_C45) {
  791. /* Load Register Address */
  792. lan743x_csr_write(adapter, MAC_MII_DATA, (u32)(index & 0xffff));
  793. mmd_access = lan743x_mac_mmd_access(phy_id, index,
  794. MMD_ACCESS_ADDRESS);
  795. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  796. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  797. if (ret < 0)
  798. return ret;
  799. /* Write Data */
  800. lan743x_csr_write(adapter, MAC_MII_DATA, (u32)regval);
  801. mmd_access = lan743x_mac_mmd_access(phy_id, index,
  802. MMD_ACCESS_WRITE);
  803. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  804. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  805. } else {
  806. ret = lan743x_mdiobus_write(bus, phy_id, index, regval);
  807. }
  808. return ret;
  809. }
  810. static int lan743x_sgmii_wait_till_not_busy(struct lan743x_adapter *adapter)
  811. {
  812. u32 data;
  813. int ret;
  814. ret = readx_poll_timeout(LAN743X_CSR_READ_OP, SGMII_ACC, data,
  815. !(data & SGMII_ACC_SGMII_BZY_), 100, 1000000);
  816. if (ret < 0)
  817. netif_err(adapter, drv, adapter->netdev,
  818. "%s: error %d sgmii wait timeout\n", __func__, ret);
  819. return ret;
  820. }
  821. static int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr)
  822. {
  823. u32 mmd_access;
  824. int ret;
  825. u32 val;
  826. if (mmd > 31) {
  827. netif_err(adapter, probe, adapter->netdev,
  828. "%s mmd should <= 31\n", __func__);
  829. return -EINVAL;
  830. }
  831. mutex_lock(&adapter->sgmii_rw_lock);
  832. /* Load Register Address */
  833. mmd_access = mmd << SGMII_ACC_SGMII_MMD_SHIFT_;
  834. mmd_access |= (addr | SGMII_ACC_SGMII_BZY_);
  835. lan743x_csr_write(adapter, SGMII_ACC, mmd_access);
  836. ret = lan743x_sgmii_wait_till_not_busy(adapter);
  837. if (ret < 0)
  838. goto sgmii_unlock;
  839. val = lan743x_csr_read(adapter, SGMII_DATA);
  840. ret = (int)(val & SGMII_DATA_MASK_);
  841. sgmii_unlock:
  842. mutex_unlock(&adapter->sgmii_rw_lock);
  843. return ret;
  844. }
  845. static int lan743x_sgmii_write(struct lan743x_adapter *adapter,
  846. u8 mmd, u16 addr, u16 val)
  847. {
  848. u32 mmd_access;
  849. int ret;
  850. if (mmd > 31) {
  851. netif_err(adapter, probe, adapter->netdev,
  852. "%s mmd should <= 31\n", __func__);
  853. return -EINVAL;
  854. }
  855. mutex_lock(&adapter->sgmii_rw_lock);
  856. /* Load Register Data */
  857. lan743x_csr_write(adapter, SGMII_DATA, (u32)(val & SGMII_DATA_MASK_));
  858. /* Load Register Address */
  859. mmd_access = mmd << SGMII_ACC_SGMII_MMD_SHIFT_;
  860. mmd_access |= (addr | SGMII_ACC_SGMII_BZY_ | SGMII_ACC_SGMII_WR_);
  861. lan743x_csr_write(adapter, SGMII_ACC, mmd_access);
  862. ret = lan743x_sgmii_wait_till_not_busy(adapter);
  863. mutex_unlock(&adapter->sgmii_rw_lock);
  864. return ret;
  865. }
  866. static int lan743x_sgmii_mpll_set(struct lan743x_adapter *adapter,
  867. u16 baud)
  868. {
  869. int mpllctrl0;
  870. int mpllctrl1;
  871. int miscctrl1;
  872. int ret;
  873. mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  874. VR_MII_GEN2_4_MPLL_CTRL0);
  875. if (mpllctrl0 < 0)
  876. return mpllctrl0;
  877. mpllctrl0 &= ~VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_;
  878. if (baud == VR_MII_BAUD_RATE_1P25GBPS) {
  879. mpllctrl1 = VR_MII_MPLL_MULTIPLIER_100;
  880. /* mpll_baud_clk/4 */
  881. miscctrl1 = 0xA;
  882. } else {
  883. mpllctrl1 = VR_MII_MPLL_MULTIPLIER_125;
  884. /* mpll_baud_clk/2 */
  885. miscctrl1 = 0x5;
  886. }
  887. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  888. VR_MII_GEN2_4_MPLL_CTRL0, mpllctrl0);
  889. if (ret < 0)
  890. return ret;
  891. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  892. VR_MII_GEN2_4_MPLL_CTRL1, mpllctrl1);
  893. if (ret < 0)
  894. return ret;
  895. return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  896. VR_MII_GEN2_4_MISC_CTRL1, miscctrl1);
  897. }
  898. static int lan743x_sgmii_2_5G_mode_set(struct lan743x_adapter *adapter,
  899. bool enable)
  900. {
  901. if (enable)
  902. return lan743x_sgmii_mpll_set(adapter,
  903. VR_MII_BAUD_RATE_3P125GBPS);
  904. else
  905. return lan743x_sgmii_mpll_set(adapter,
  906. VR_MII_BAUD_RATE_1P25GBPS);
  907. }
  908. static int lan743x_is_sgmii_2_5G_mode(struct lan743x_adapter *adapter,
  909. bool *status)
  910. {
  911. int ret;
  912. ret = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  913. VR_MII_GEN2_4_MPLL_CTRL1);
  914. if (ret < 0)
  915. return ret;
  916. if (ret == VR_MII_MPLL_MULTIPLIER_125 ||
  917. ret == VR_MII_MPLL_MULTIPLIER_50)
  918. *status = true;
  919. else
  920. *status = false;
  921. return 0;
  922. }
  923. static int lan743x_sgmii_aneg_update(struct lan743x_adapter *adapter)
  924. {
  925. enum lan743x_sgmii_lsd lsd = adapter->sgmii_lsd;
  926. int mii_ctrl;
  927. int dgt_ctrl;
  928. int an_ctrl;
  929. int ret;
  930. if (lsd == LINK_2500_MASTER || lsd == LINK_2500_SLAVE)
  931. /* Switch to 2.5 Gbps */
  932. ret = lan743x_sgmii_2_5G_mode_set(adapter, true);
  933. else
  934. /* Switch to 10/100/1000 Mbps clock */
  935. ret = lan743x_sgmii_2_5G_mode_set(adapter, false);
  936. if (ret < 0)
  937. return ret;
  938. /* Enable SGMII Auto NEG */
  939. mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR);
  940. if (mii_ctrl < 0)
  941. return mii_ctrl;
  942. an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL);
  943. if (an_ctrl < 0)
  944. return an_ctrl;
  945. dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  946. VR_MII_DIG_CTRL1);
  947. if (dgt_ctrl < 0)
  948. return dgt_ctrl;
  949. if (lsd == LINK_2500_MASTER || lsd == LINK_2500_SLAVE) {
  950. mii_ctrl &= ~(BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100);
  951. mii_ctrl |= BMCR_SPEED1000;
  952. dgt_ctrl |= VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_;
  953. dgt_ctrl &= ~VR_MII_DIG_CTRL1_MAC_AUTO_SW_;
  954. /* In order for Auto-Negotiation to operate properly at
  955. * 2.5 Gbps the 1.6ms link timer values must be adjusted
  956. * The VR_MII_LINK_TIMER_CTRL Register must be set to
  957. * 16'h7A1 and The CL37_TMR_OVR_RIDE bit of the
  958. * VR_MII_DIG_CTRL1 Register set to 1
  959. */
  960. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  961. VR_MII_LINK_TIMER_CTRL, 0x7A1);
  962. if (ret < 0)
  963. return ret;
  964. } else {
  965. mii_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  966. an_ctrl &= ~VR_MII_AN_CTRL_SGMII_LINK_STS_;
  967. dgt_ctrl &= ~VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_;
  968. dgt_ctrl |= VR_MII_DIG_CTRL1_MAC_AUTO_SW_;
  969. }
  970. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR,
  971. mii_ctrl);
  972. if (ret < 0)
  973. return ret;
  974. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  975. VR_MII_DIG_CTRL1, dgt_ctrl);
  976. if (ret < 0)
  977. return ret;
  978. return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  979. VR_MII_AN_CTRL, an_ctrl);
  980. }
  981. static int lan743x_pcs_seq_state(struct lan743x_adapter *adapter, u8 state)
  982. {
  983. u8 wait_cnt = 0;
  984. u32 dig_sts;
  985. do {
  986. dig_sts = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  987. VR_MII_DIG_STS);
  988. if (((dig_sts & VR_MII_DIG_STS_PSEQ_STATE_MASK_) >>
  989. VR_MII_DIG_STS_PSEQ_STATE_POS_) == state)
  990. break;
  991. usleep_range(1000, 2000);
  992. } while (wait_cnt++ < 10);
  993. if (wait_cnt >= 10)
  994. return -ETIMEDOUT;
  995. return 0;
  996. }
  997. static int lan743x_sgmii_config(struct lan743x_adapter *adapter)
  998. {
  999. struct net_device *netdev = adapter->netdev;
  1000. struct phy_device *phydev = netdev->phydev;
  1001. enum lan743x_sgmii_lsd lsd = POWER_DOWN;
  1002. int mii_ctl;
  1003. bool status;
  1004. int ret;
  1005. switch (phydev->speed) {
  1006. case SPEED_2500:
  1007. if (phydev->master_slave_state == MASTER_SLAVE_STATE_MASTER)
  1008. lsd = LINK_2500_MASTER;
  1009. else
  1010. lsd = LINK_2500_SLAVE;
  1011. break;
  1012. case SPEED_1000:
  1013. if (phydev->master_slave_state == MASTER_SLAVE_STATE_MASTER)
  1014. lsd = LINK_1000_MASTER;
  1015. else
  1016. lsd = LINK_1000_SLAVE;
  1017. break;
  1018. case SPEED_100:
  1019. if (phydev->duplex)
  1020. lsd = LINK_100FD;
  1021. else
  1022. lsd = LINK_100HD;
  1023. break;
  1024. case SPEED_10:
  1025. if (phydev->duplex)
  1026. lsd = LINK_10FD;
  1027. else
  1028. lsd = LINK_10HD;
  1029. break;
  1030. default:
  1031. netif_err(adapter, drv, adapter->netdev,
  1032. "Invalid speed %d\n", phydev->speed);
  1033. return -EINVAL;
  1034. }
  1035. adapter->sgmii_lsd = lsd;
  1036. ret = lan743x_sgmii_aneg_update(adapter);
  1037. if (ret < 0) {
  1038. netif_err(adapter, drv, adapter->netdev,
  1039. "error %d SGMII cfg failed\n", ret);
  1040. return ret;
  1041. }
  1042. ret = lan743x_is_sgmii_2_5G_mode(adapter, &status);
  1043. if (ret < 0) {
  1044. netif_err(adapter, drv, adapter->netdev,
  1045. "erro %d SGMII get mode failed\n", ret);
  1046. return ret;
  1047. }
  1048. if (status)
  1049. netif_dbg(adapter, drv, adapter->netdev,
  1050. "SGMII 2.5G mode enable\n");
  1051. else
  1052. netif_dbg(adapter, drv, adapter->netdev,
  1053. "SGMII 1G mode enable\n");
  1054. /* SGMII/1000/2500BASE-X PCS power down */
  1055. mii_ctl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR);
  1056. if (mii_ctl < 0)
  1057. return mii_ctl;
  1058. mii_ctl |= BMCR_PDOWN;
  1059. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, mii_ctl);
  1060. if (ret < 0)
  1061. return ret;
  1062. ret = lan743x_pcs_seq_state(adapter, PCS_POWER_STATE_DOWN);
  1063. if (ret < 0)
  1064. return ret;
  1065. /* SGMII/1000/2500BASE-X PCS power up */
  1066. mii_ctl &= ~BMCR_PDOWN;
  1067. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, mii_ctl);
  1068. if (ret < 0)
  1069. return ret;
  1070. ret = lan743x_pcs_seq_state(adapter, PCS_POWER_STATE_UP);
  1071. if (ret < 0)
  1072. return ret;
  1073. return 0;
  1074. }
  1075. static void lan743x_mac_set_address(struct lan743x_adapter *adapter,
  1076. u8 *addr)
  1077. {
  1078. u32 addr_lo, addr_hi;
  1079. addr_lo = addr[0] |
  1080. addr[1] << 8 |
  1081. addr[2] << 16 |
  1082. addr[3] << 24;
  1083. addr_hi = addr[4] |
  1084. addr[5] << 8;
  1085. lan743x_csr_write(adapter, MAC_RX_ADDRL, addr_lo);
  1086. lan743x_csr_write(adapter, MAC_RX_ADDRH, addr_hi);
  1087. ether_addr_copy(adapter->mac_address, addr);
  1088. netif_info(adapter, drv, adapter->netdev,
  1089. "MAC address set to %pM\n", addr);
  1090. }
  1091. static int lan743x_mac_init(struct lan743x_adapter *adapter)
  1092. {
  1093. bool mac_address_valid = true;
  1094. struct net_device *netdev;
  1095. u32 mac_addr_hi = 0;
  1096. u32 mac_addr_lo = 0;
  1097. u32 data;
  1098. netdev = adapter->netdev;
  1099. /* disable auto duplex, and speed detection. Phylib does that */
  1100. data = lan743x_csr_read(adapter, MAC_CR);
  1101. data &= ~(MAC_CR_ADD_ | MAC_CR_ASD_);
  1102. data |= MAC_CR_CNTR_RST_;
  1103. lan743x_csr_write(adapter, MAC_CR, data);
  1104. if (!is_valid_ether_addr(adapter->mac_address)) {
  1105. mac_addr_hi = lan743x_csr_read(adapter, MAC_RX_ADDRH);
  1106. mac_addr_lo = lan743x_csr_read(adapter, MAC_RX_ADDRL);
  1107. adapter->mac_address[0] = mac_addr_lo & 0xFF;
  1108. adapter->mac_address[1] = (mac_addr_lo >> 8) & 0xFF;
  1109. adapter->mac_address[2] = (mac_addr_lo >> 16) & 0xFF;
  1110. adapter->mac_address[3] = (mac_addr_lo >> 24) & 0xFF;
  1111. adapter->mac_address[4] = mac_addr_hi & 0xFF;
  1112. adapter->mac_address[5] = (mac_addr_hi >> 8) & 0xFF;
  1113. if (((mac_addr_hi & 0x0000FFFF) == 0x0000FFFF) &&
  1114. mac_addr_lo == 0xFFFFFFFF) {
  1115. mac_address_valid = false;
  1116. } else if (!is_valid_ether_addr(adapter->mac_address)) {
  1117. mac_address_valid = false;
  1118. }
  1119. if (!mac_address_valid)
  1120. eth_random_addr(adapter->mac_address);
  1121. }
  1122. lan743x_mac_set_address(adapter, adapter->mac_address);
  1123. eth_hw_addr_set(netdev, adapter->mac_address);
  1124. return 0;
  1125. }
  1126. static int lan743x_mac_open(struct lan743x_adapter *adapter)
  1127. {
  1128. u32 temp;
  1129. temp = lan743x_csr_read(adapter, MAC_RX);
  1130. lan743x_csr_write(adapter, MAC_RX, temp | MAC_RX_RXEN_);
  1131. temp = lan743x_csr_read(adapter, MAC_TX);
  1132. lan743x_csr_write(adapter, MAC_TX, temp | MAC_TX_TXEN_);
  1133. return 0;
  1134. }
  1135. static void lan743x_mac_close(struct lan743x_adapter *adapter)
  1136. {
  1137. u32 temp;
  1138. temp = lan743x_csr_read(adapter, MAC_TX);
  1139. temp &= ~MAC_TX_TXEN_;
  1140. lan743x_csr_write(adapter, MAC_TX, temp);
  1141. lan743x_csr_wait_for_bit(adapter, MAC_TX, MAC_TX_TXD_,
  1142. 1, 1000, 20000, 100);
  1143. temp = lan743x_csr_read(adapter, MAC_RX);
  1144. temp &= ~MAC_RX_RXEN_;
  1145. lan743x_csr_write(adapter, MAC_RX, temp);
  1146. lan743x_csr_wait_for_bit(adapter, MAC_RX, MAC_RX_RXD_,
  1147. 1, 1000, 20000, 100);
  1148. }
  1149. static void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter,
  1150. bool tx_enable, bool rx_enable)
  1151. {
  1152. u32 flow_setting = 0;
  1153. /* set maximum pause time because when fifo space frees
  1154. * up a zero value pause frame will be sent to release the pause
  1155. */
  1156. flow_setting = MAC_FLOW_CR_FCPT_MASK_;
  1157. if (tx_enable)
  1158. flow_setting |= MAC_FLOW_CR_TX_FCEN_;
  1159. if (rx_enable)
  1160. flow_setting |= MAC_FLOW_CR_RX_FCEN_;
  1161. lan743x_csr_write(adapter, MAC_FLOW, flow_setting);
  1162. }
  1163. static int lan743x_mac_set_mtu(struct lan743x_adapter *adapter, int new_mtu)
  1164. {
  1165. int enabled = 0;
  1166. u32 mac_rx = 0;
  1167. mac_rx = lan743x_csr_read(adapter, MAC_RX);
  1168. if (mac_rx & MAC_RX_RXEN_) {
  1169. enabled = 1;
  1170. if (mac_rx & MAC_RX_RXD_) {
  1171. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1172. mac_rx &= ~MAC_RX_RXD_;
  1173. }
  1174. mac_rx &= ~MAC_RX_RXEN_;
  1175. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1176. lan743x_csr_wait_for_bit(adapter, MAC_RX, MAC_RX_RXD_,
  1177. 1, 1000, 20000, 100);
  1178. lan743x_csr_write(adapter, MAC_RX, mac_rx | MAC_RX_RXD_);
  1179. }
  1180. mac_rx &= ~(MAC_RX_MAX_SIZE_MASK_);
  1181. mac_rx |= (((new_mtu + ETH_HLEN + ETH_FCS_LEN)
  1182. << MAC_RX_MAX_SIZE_SHIFT_) & MAC_RX_MAX_SIZE_MASK_);
  1183. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1184. if (enabled) {
  1185. mac_rx |= MAC_RX_RXEN_;
  1186. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1187. }
  1188. return 0;
  1189. }
  1190. /* PHY */
  1191. static int lan743x_phy_reset(struct lan743x_adapter *adapter)
  1192. {
  1193. u32 data;
  1194. /* Only called with in probe, and before mdiobus_register */
  1195. data = lan743x_csr_read(adapter, PMT_CTL);
  1196. data |= PMT_CTL_ETH_PHY_RST_;
  1197. lan743x_csr_write(adapter, PMT_CTL, data);
  1198. return readx_poll_timeout(LAN743X_CSR_READ_OP, PMT_CTL, data,
  1199. (!(data & PMT_CTL_ETH_PHY_RST_) &&
  1200. (data & PMT_CTL_READY_)),
  1201. 50000, 1000000);
  1202. }
  1203. static void lan743x_phy_update_flowcontrol(struct lan743x_adapter *adapter,
  1204. u16 local_adv, u16 remote_adv)
  1205. {
  1206. struct lan743x_phy *phy = &adapter->phy;
  1207. u8 cap;
  1208. if (phy->fc_autoneg)
  1209. cap = mii_resolve_flowctrl_fdx(local_adv, remote_adv);
  1210. else
  1211. cap = phy->fc_request_control;
  1212. lan743x_mac_flow_ctrl_set_enables(adapter,
  1213. cap & FLOW_CTRL_TX,
  1214. cap & FLOW_CTRL_RX);
  1215. }
  1216. static int lan743x_phy_init(struct lan743x_adapter *adapter)
  1217. {
  1218. return lan743x_phy_reset(adapter);
  1219. }
  1220. static void lan743x_phy_link_status_change(struct net_device *netdev)
  1221. {
  1222. struct lan743x_adapter *adapter = netdev_priv(netdev);
  1223. struct phy_device *phydev = netdev->phydev;
  1224. u32 data;
  1225. phy_print_status(phydev);
  1226. if (phydev->state == PHY_RUNNING) {
  1227. int remote_advertisement = 0;
  1228. int local_advertisement = 0;
  1229. data = lan743x_csr_read(adapter, MAC_CR);
  1230. /* set interface mode */
  1231. if (phy_interface_is_rgmii(phydev))
  1232. /* RGMII */
  1233. data &= ~MAC_CR_MII_EN_;
  1234. else
  1235. /* GMII */
  1236. data |= MAC_CR_MII_EN_;
  1237. /* set duplex mode */
  1238. if (phydev->duplex)
  1239. data |= MAC_CR_DPX_;
  1240. else
  1241. data &= ~MAC_CR_DPX_;
  1242. /* set bus speed */
  1243. switch (phydev->speed) {
  1244. case SPEED_10:
  1245. data &= ~MAC_CR_CFG_H_;
  1246. data &= ~MAC_CR_CFG_L_;
  1247. break;
  1248. case SPEED_100:
  1249. data &= ~MAC_CR_CFG_H_;
  1250. data |= MAC_CR_CFG_L_;
  1251. break;
  1252. case SPEED_1000:
  1253. data |= MAC_CR_CFG_H_;
  1254. data &= ~MAC_CR_CFG_L_;
  1255. break;
  1256. case SPEED_2500:
  1257. data |= MAC_CR_CFG_H_;
  1258. data |= MAC_CR_CFG_L_;
  1259. break;
  1260. }
  1261. lan743x_csr_write(adapter, MAC_CR, data);
  1262. local_advertisement =
  1263. linkmode_adv_to_mii_adv_t(phydev->advertising);
  1264. remote_advertisement =
  1265. linkmode_adv_to_mii_adv_t(phydev->lp_advertising);
  1266. lan743x_phy_update_flowcontrol(adapter, local_advertisement,
  1267. remote_advertisement);
  1268. lan743x_ptp_update_latency(adapter, phydev->speed);
  1269. if (phydev->interface == PHY_INTERFACE_MODE_SGMII ||
  1270. phydev->interface == PHY_INTERFACE_MODE_1000BASEX ||
  1271. phydev->interface == PHY_INTERFACE_MODE_2500BASEX)
  1272. lan743x_sgmii_config(adapter);
  1273. }
  1274. }
  1275. static void lan743x_phy_close(struct lan743x_adapter *adapter)
  1276. {
  1277. struct net_device *netdev = adapter->netdev;
  1278. phy_stop(netdev->phydev);
  1279. phy_disconnect(netdev->phydev);
  1280. netdev->phydev = NULL;
  1281. }
  1282. static int lan743x_phy_open(struct lan743x_adapter *adapter)
  1283. {
  1284. struct net_device *netdev = adapter->netdev;
  1285. struct lan743x_phy *phy = &adapter->phy;
  1286. struct phy_device *phydev;
  1287. int ret = -EIO;
  1288. /* try devicetree phy, or fixed link */
  1289. phydev = of_phy_get_and_connect(netdev, adapter->pdev->dev.of_node,
  1290. lan743x_phy_link_status_change);
  1291. if (!phydev) {
  1292. /* try internal phy */
  1293. phydev = phy_find_first(adapter->mdiobus);
  1294. if (!phydev)
  1295. goto return_error;
  1296. if (adapter->is_pci11x1x)
  1297. ret = phy_connect_direct(netdev, phydev,
  1298. lan743x_phy_link_status_change,
  1299. PHY_INTERFACE_MODE_RGMII);
  1300. else
  1301. ret = phy_connect_direct(netdev, phydev,
  1302. lan743x_phy_link_status_change,
  1303. PHY_INTERFACE_MODE_GMII);
  1304. if (ret)
  1305. goto return_error;
  1306. }
  1307. /* MAC doesn't support 1000T Half */
  1308. phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
  1309. /* support both flow controls */
  1310. phy_support_asym_pause(phydev);
  1311. phy->fc_request_control = (FLOW_CTRL_RX | FLOW_CTRL_TX);
  1312. phy->fc_autoneg = phydev->autoneg;
  1313. phy_start(phydev);
  1314. phy_start_aneg(phydev);
  1315. phy_attached_info(phydev);
  1316. return 0;
  1317. return_error:
  1318. return ret;
  1319. }
  1320. static void lan743x_rfe_open(struct lan743x_adapter *adapter)
  1321. {
  1322. lan743x_csr_write(adapter, RFE_RSS_CFG,
  1323. RFE_RSS_CFG_UDP_IPV6_EX_ |
  1324. RFE_RSS_CFG_TCP_IPV6_EX_ |
  1325. RFE_RSS_CFG_IPV6_EX_ |
  1326. RFE_RSS_CFG_UDP_IPV6_ |
  1327. RFE_RSS_CFG_TCP_IPV6_ |
  1328. RFE_RSS_CFG_IPV6_ |
  1329. RFE_RSS_CFG_UDP_IPV4_ |
  1330. RFE_RSS_CFG_TCP_IPV4_ |
  1331. RFE_RSS_CFG_IPV4_ |
  1332. RFE_RSS_CFG_VALID_HASH_BITS_ |
  1333. RFE_RSS_CFG_RSS_QUEUE_ENABLE_ |
  1334. RFE_RSS_CFG_RSS_HASH_STORE_ |
  1335. RFE_RSS_CFG_RSS_ENABLE_);
  1336. }
  1337. static void lan743x_rfe_update_mac_address(struct lan743x_adapter *adapter)
  1338. {
  1339. u8 *mac_addr;
  1340. u32 mac_addr_hi = 0;
  1341. u32 mac_addr_lo = 0;
  1342. /* Add mac address to perfect Filter */
  1343. mac_addr = adapter->mac_address;
  1344. mac_addr_lo = ((((u32)(mac_addr[0])) << 0) |
  1345. (((u32)(mac_addr[1])) << 8) |
  1346. (((u32)(mac_addr[2])) << 16) |
  1347. (((u32)(mac_addr[3])) << 24));
  1348. mac_addr_hi = ((((u32)(mac_addr[4])) << 0) |
  1349. (((u32)(mac_addr[5])) << 8));
  1350. lan743x_csr_write(adapter, RFE_ADDR_FILT_LO(0), mac_addr_lo);
  1351. lan743x_csr_write(adapter, RFE_ADDR_FILT_HI(0),
  1352. mac_addr_hi | RFE_ADDR_FILT_HI_VALID_);
  1353. }
  1354. static void lan743x_rfe_set_multicast(struct lan743x_adapter *adapter)
  1355. {
  1356. struct net_device *netdev = adapter->netdev;
  1357. u32 hash_table[DP_SEL_VHF_HASH_LEN];
  1358. u32 rfctl;
  1359. u32 data;
  1360. rfctl = lan743x_csr_read(adapter, RFE_CTL);
  1361. rfctl &= ~(RFE_CTL_AU_ | RFE_CTL_AM_ |
  1362. RFE_CTL_DA_PERFECT_ | RFE_CTL_MCAST_HASH_);
  1363. rfctl |= RFE_CTL_AB_;
  1364. if (netdev->flags & IFF_PROMISC) {
  1365. rfctl |= RFE_CTL_AM_ | RFE_CTL_AU_;
  1366. } else {
  1367. if (netdev->flags & IFF_ALLMULTI)
  1368. rfctl |= RFE_CTL_AM_;
  1369. }
  1370. if (netdev->features & NETIF_F_RXCSUM)
  1371. rfctl |= RFE_CTL_IP_COE_ | RFE_CTL_TCP_UDP_COE_;
  1372. memset(hash_table, 0, DP_SEL_VHF_HASH_LEN * sizeof(u32));
  1373. if (netdev_mc_count(netdev)) {
  1374. struct netdev_hw_addr *ha;
  1375. int i;
  1376. rfctl |= RFE_CTL_DA_PERFECT_;
  1377. i = 1;
  1378. netdev_for_each_mc_addr(ha, netdev) {
  1379. /* set first 32 into Perfect Filter */
  1380. if (i < 33) {
  1381. lan743x_csr_write(adapter,
  1382. RFE_ADDR_FILT_HI(i), 0);
  1383. data = ha->addr[3];
  1384. data = ha->addr[2] | (data << 8);
  1385. data = ha->addr[1] | (data << 8);
  1386. data = ha->addr[0] | (data << 8);
  1387. lan743x_csr_write(adapter,
  1388. RFE_ADDR_FILT_LO(i), data);
  1389. data = ha->addr[5];
  1390. data = ha->addr[4] | (data << 8);
  1391. data |= RFE_ADDR_FILT_HI_VALID_;
  1392. lan743x_csr_write(adapter,
  1393. RFE_ADDR_FILT_HI(i), data);
  1394. } else {
  1395. u32 bitnum = (ether_crc(ETH_ALEN, ha->addr) >>
  1396. 23) & 0x1FF;
  1397. hash_table[bitnum / 32] |= (1 << (bitnum % 32));
  1398. rfctl |= RFE_CTL_MCAST_HASH_;
  1399. }
  1400. i++;
  1401. }
  1402. }
  1403. lan743x_dp_write(adapter, DP_SEL_RFE_RAM,
  1404. DP_SEL_VHF_VLAN_LEN,
  1405. DP_SEL_VHF_HASH_LEN, hash_table);
  1406. lan743x_csr_write(adapter, RFE_CTL, rfctl);
  1407. }
  1408. static int lan743x_dmac_init(struct lan743x_adapter *adapter)
  1409. {
  1410. u32 data = 0;
  1411. lan743x_csr_write(adapter, DMAC_CMD, DMAC_CMD_SWR_);
  1412. lan743x_csr_wait_for_bit(adapter, DMAC_CMD, DMAC_CMD_SWR_,
  1413. 0, 1000, 20000, 100);
  1414. switch (DEFAULT_DMA_DESCRIPTOR_SPACING) {
  1415. case DMA_DESCRIPTOR_SPACING_16:
  1416. data = DMAC_CFG_MAX_DSPACE_16_;
  1417. break;
  1418. case DMA_DESCRIPTOR_SPACING_32:
  1419. data = DMAC_CFG_MAX_DSPACE_32_;
  1420. break;
  1421. case DMA_DESCRIPTOR_SPACING_64:
  1422. data = DMAC_CFG_MAX_DSPACE_64_;
  1423. break;
  1424. case DMA_DESCRIPTOR_SPACING_128:
  1425. data = DMAC_CFG_MAX_DSPACE_128_;
  1426. break;
  1427. default:
  1428. return -EPERM;
  1429. }
  1430. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))
  1431. data |= DMAC_CFG_COAL_EN_;
  1432. data |= DMAC_CFG_CH_ARB_SEL_RX_HIGH_;
  1433. data |= DMAC_CFG_MAX_READ_REQ_SET_(6);
  1434. lan743x_csr_write(adapter, DMAC_CFG, data);
  1435. data = DMAC_COAL_CFG_TIMER_LIMIT_SET_(1);
  1436. data |= DMAC_COAL_CFG_TIMER_TX_START_;
  1437. data |= DMAC_COAL_CFG_FLUSH_INTS_;
  1438. data |= DMAC_COAL_CFG_INT_EXIT_COAL_;
  1439. data |= DMAC_COAL_CFG_CSR_EXIT_COAL_;
  1440. data |= DMAC_COAL_CFG_TX_THRES_SET_(0x0A);
  1441. data |= DMAC_COAL_CFG_RX_THRES_SET_(0x0C);
  1442. lan743x_csr_write(adapter, DMAC_COAL_CFG, data);
  1443. data = DMAC_OBFF_TX_THRES_SET_(0x08);
  1444. data |= DMAC_OBFF_RX_THRES_SET_(0x0A);
  1445. lan743x_csr_write(adapter, DMAC_OBFF_CFG, data);
  1446. return 0;
  1447. }
  1448. static int lan743x_dmac_tx_get_state(struct lan743x_adapter *adapter,
  1449. int tx_channel)
  1450. {
  1451. u32 dmac_cmd = 0;
  1452. dmac_cmd = lan743x_csr_read(adapter, DMAC_CMD);
  1453. return DMAC_CHANNEL_STATE_SET((dmac_cmd &
  1454. DMAC_CMD_START_T_(tx_channel)),
  1455. (dmac_cmd &
  1456. DMAC_CMD_STOP_T_(tx_channel)));
  1457. }
  1458. static int lan743x_dmac_tx_wait_till_stopped(struct lan743x_adapter *adapter,
  1459. int tx_channel)
  1460. {
  1461. int timeout = 100;
  1462. int result = 0;
  1463. while (timeout &&
  1464. ((result = lan743x_dmac_tx_get_state(adapter, tx_channel)) ==
  1465. DMAC_CHANNEL_STATE_STOP_PENDING)) {
  1466. usleep_range(1000, 20000);
  1467. timeout--;
  1468. }
  1469. if (result == DMAC_CHANNEL_STATE_STOP_PENDING)
  1470. result = -ENODEV;
  1471. return result;
  1472. }
  1473. static int lan743x_dmac_rx_get_state(struct lan743x_adapter *adapter,
  1474. int rx_channel)
  1475. {
  1476. u32 dmac_cmd = 0;
  1477. dmac_cmd = lan743x_csr_read(adapter, DMAC_CMD);
  1478. return DMAC_CHANNEL_STATE_SET((dmac_cmd &
  1479. DMAC_CMD_START_R_(rx_channel)),
  1480. (dmac_cmd &
  1481. DMAC_CMD_STOP_R_(rx_channel)));
  1482. }
  1483. static int lan743x_dmac_rx_wait_till_stopped(struct lan743x_adapter *adapter,
  1484. int rx_channel)
  1485. {
  1486. int timeout = 100;
  1487. int result = 0;
  1488. while (timeout &&
  1489. ((result = lan743x_dmac_rx_get_state(adapter, rx_channel)) ==
  1490. DMAC_CHANNEL_STATE_STOP_PENDING)) {
  1491. usleep_range(1000, 20000);
  1492. timeout--;
  1493. }
  1494. if (result == DMAC_CHANNEL_STATE_STOP_PENDING)
  1495. result = -ENODEV;
  1496. return result;
  1497. }
  1498. static void lan743x_tx_release_desc(struct lan743x_tx *tx,
  1499. int descriptor_index, bool cleanup)
  1500. {
  1501. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1502. struct lan743x_tx_descriptor *descriptor = NULL;
  1503. u32 descriptor_type = 0;
  1504. bool ignore_sync;
  1505. descriptor = &tx->ring_cpu_ptr[descriptor_index];
  1506. buffer_info = &tx->buffer_info[descriptor_index];
  1507. if (!(buffer_info->flags & TX_BUFFER_INFO_FLAG_ACTIVE))
  1508. goto done;
  1509. descriptor_type = le32_to_cpu(descriptor->data0) &
  1510. TX_DESC_DATA0_DTYPE_MASK_;
  1511. if (descriptor_type == TX_DESC_DATA0_DTYPE_DATA_)
  1512. goto clean_up_data_descriptor;
  1513. else
  1514. goto clear_active;
  1515. clean_up_data_descriptor:
  1516. if (buffer_info->dma_ptr) {
  1517. if (buffer_info->flags &
  1518. TX_BUFFER_INFO_FLAG_SKB_FRAGMENT) {
  1519. dma_unmap_page(&tx->adapter->pdev->dev,
  1520. buffer_info->dma_ptr,
  1521. buffer_info->buffer_length,
  1522. DMA_TO_DEVICE);
  1523. } else {
  1524. dma_unmap_single(&tx->adapter->pdev->dev,
  1525. buffer_info->dma_ptr,
  1526. buffer_info->buffer_length,
  1527. DMA_TO_DEVICE);
  1528. }
  1529. buffer_info->dma_ptr = 0;
  1530. buffer_info->buffer_length = 0;
  1531. }
  1532. if (!buffer_info->skb)
  1533. goto clear_active;
  1534. if (!(buffer_info->flags & TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED)) {
  1535. dev_kfree_skb_any(buffer_info->skb);
  1536. goto clear_skb;
  1537. }
  1538. if (cleanup) {
  1539. lan743x_ptp_unrequest_tx_timestamp(tx->adapter);
  1540. dev_kfree_skb_any(buffer_info->skb);
  1541. } else {
  1542. ignore_sync = (buffer_info->flags &
  1543. TX_BUFFER_INFO_FLAG_IGNORE_SYNC) != 0;
  1544. lan743x_ptp_tx_timestamp_skb(tx->adapter,
  1545. buffer_info->skb, ignore_sync);
  1546. }
  1547. clear_skb:
  1548. buffer_info->skb = NULL;
  1549. clear_active:
  1550. buffer_info->flags &= ~TX_BUFFER_INFO_FLAG_ACTIVE;
  1551. done:
  1552. memset(buffer_info, 0, sizeof(*buffer_info));
  1553. memset(descriptor, 0, sizeof(*descriptor));
  1554. }
  1555. static int lan743x_tx_next_index(struct lan743x_tx *tx, int index)
  1556. {
  1557. return ((++index) % tx->ring_size);
  1558. }
  1559. static void lan743x_tx_release_completed_descriptors(struct lan743x_tx *tx)
  1560. {
  1561. while (le32_to_cpu(*tx->head_cpu_ptr) != (tx->last_head)) {
  1562. lan743x_tx_release_desc(tx, tx->last_head, false);
  1563. tx->last_head = lan743x_tx_next_index(tx, tx->last_head);
  1564. }
  1565. }
  1566. static void lan743x_tx_release_all_descriptors(struct lan743x_tx *tx)
  1567. {
  1568. u32 original_head = 0;
  1569. original_head = tx->last_head;
  1570. do {
  1571. lan743x_tx_release_desc(tx, tx->last_head, true);
  1572. tx->last_head = lan743x_tx_next_index(tx, tx->last_head);
  1573. } while (tx->last_head != original_head);
  1574. memset(tx->ring_cpu_ptr, 0,
  1575. sizeof(*tx->ring_cpu_ptr) * (tx->ring_size));
  1576. memset(tx->buffer_info, 0,
  1577. sizeof(*tx->buffer_info) * (tx->ring_size));
  1578. }
  1579. static int lan743x_tx_get_desc_cnt(struct lan743x_tx *tx,
  1580. struct sk_buff *skb)
  1581. {
  1582. int result = 1; /* 1 for the main skb buffer */
  1583. int nr_frags = 0;
  1584. if (skb_is_gso(skb))
  1585. result++; /* requires an extension descriptor */
  1586. nr_frags = skb_shinfo(skb)->nr_frags;
  1587. result += nr_frags; /* 1 for each fragment buffer */
  1588. return result;
  1589. }
  1590. static int lan743x_tx_get_avail_desc(struct lan743x_tx *tx)
  1591. {
  1592. int last_head = tx->last_head;
  1593. int last_tail = tx->last_tail;
  1594. if (last_tail >= last_head)
  1595. return tx->ring_size - last_tail + last_head - 1;
  1596. else
  1597. return last_head - last_tail - 1;
  1598. }
  1599. void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
  1600. bool enable_timestamping,
  1601. bool enable_onestep_sync)
  1602. {
  1603. if (enable_timestamping)
  1604. tx->ts_flags |= TX_TS_FLAG_TIMESTAMPING_ENABLED;
  1605. else
  1606. tx->ts_flags &= ~TX_TS_FLAG_TIMESTAMPING_ENABLED;
  1607. if (enable_onestep_sync)
  1608. tx->ts_flags |= TX_TS_FLAG_ONE_STEP_SYNC;
  1609. else
  1610. tx->ts_flags &= ~TX_TS_FLAG_ONE_STEP_SYNC;
  1611. }
  1612. static int lan743x_tx_frame_start(struct lan743x_tx *tx,
  1613. unsigned char *first_buffer,
  1614. unsigned int first_buffer_length,
  1615. unsigned int frame_length,
  1616. bool time_stamp,
  1617. bool check_sum)
  1618. {
  1619. /* called only from within lan743x_tx_xmit_frame.
  1620. * assuming tx->ring_lock has already been acquired.
  1621. */
  1622. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1623. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1624. struct lan743x_adapter *adapter = tx->adapter;
  1625. struct device *dev = &adapter->pdev->dev;
  1626. dma_addr_t dma_ptr;
  1627. tx->frame_flags |= TX_FRAME_FLAG_IN_PROGRESS;
  1628. tx->frame_first = tx->last_tail;
  1629. tx->frame_tail = tx->frame_first;
  1630. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1631. buffer_info = &tx->buffer_info[tx->frame_tail];
  1632. dma_ptr = dma_map_single(dev, first_buffer, first_buffer_length,
  1633. DMA_TO_DEVICE);
  1634. if (dma_mapping_error(dev, dma_ptr))
  1635. return -ENOMEM;
  1636. tx_descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(dma_ptr));
  1637. tx_descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(dma_ptr));
  1638. tx_descriptor->data3 = cpu_to_le32((frame_length << 16) &
  1639. TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_);
  1640. buffer_info->skb = NULL;
  1641. buffer_info->dma_ptr = dma_ptr;
  1642. buffer_info->buffer_length = first_buffer_length;
  1643. buffer_info->flags |= TX_BUFFER_INFO_FLAG_ACTIVE;
  1644. tx->frame_data0 = (first_buffer_length &
  1645. TX_DESC_DATA0_BUF_LENGTH_MASK_) |
  1646. TX_DESC_DATA0_DTYPE_DATA_ |
  1647. TX_DESC_DATA0_FS_ |
  1648. TX_DESC_DATA0_FCS_;
  1649. if (time_stamp)
  1650. tx->frame_data0 |= TX_DESC_DATA0_TSE_;
  1651. if (check_sum)
  1652. tx->frame_data0 |= TX_DESC_DATA0_ICE_ |
  1653. TX_DESC_DATA0_IPE_ |
  1654. TX_DESC_DATA0_TPE_;
  1655. /* data0 will be programmed in one of other frame assembler functions */
  1656. return 0;
  1657. }
  1658. static void lan743x_tx_frame_add_lso(struct lan743x_tx *tx,
  1659. unsigned int frame_length,
  1660. int nr_frags)
  1661. {
  1662. /* called only from within lan743x_tx_xmit_frame.
  1663. * assuming tx->ring_lock has already been acquired.
  1664. */
  1665. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1666. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1667. /* wrap up previous descriptor */
  1668. tx->frame_data0 |= TX_DESC_DATA0_EXT_;
  1669. if (nr_frags <= 0) {
  1670. tx->frame_data0 |= TX_DESC_DATA0_LS_;
  1671. tx->frame_data0 |= TX_DESC_DATA0_IOC_;
  1672. }
  1673. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1674. tx_descriptor->data0 = cpu_to_le32(tx->frame_data0);
  1675. /* move to next descriptor */
  1676. tx->frame_tail = lan743x_tx_next_index(tx, tx->frame_tail);
  1677. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1678. buffer_info = &tx->buffer_info[tx->frame_tail];
  1679. /* add extension descriptor */
  1680. tx_descriptor->data1 = 0;
  1681. tx_descriptor->data2 = 0;
  1682. tx_descriptor->data3 = 0;
  1683. buffer_info->skb = NULL;
  1684. buffer_info->dma_ptr = 0;
  1685. buffer_info->buffer_length = 0;
  1686. buffer_info->flags |= TX_BUFFER_INFO_FLAG_ACTIVE;
  1687. tx->frame_data0 = (frame_length & TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_) |
  1688. TX_DESC_DATA0_DTYPE_EXT_ |
  1689. TX_DESC_DATA0_EXT_LSO_;
  1690. /* data0 will be programmed in one of other frame assembler functions */
  1691. }
  1692. static int lan743x_tx_frame_add_fragment(struct lan743x_tx *tx,
  1693. const skb_frag_t *fragment,
  1694. unsigned int frame_length)
  1695. {
  1696. /* called only from within lan743x_tx_xmit_frame
  1697. * assuming tx->ring_lock has already been acquired
  1698. */
  1699. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1700. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1701. struct lan743x_adapter *adapter = tx->adapter;
  1702. struct device *dev = &adapter->pdev->dev;
  1703. unsigned int fragment_length = 0;
  1704. dma_addr_t dma_ptr;
  1705. fragment_length = skb_frag_size(fragment);
  1706. if (!fragment_length)
  1707. return 0;
  1708. /* wrap up previous descriptor */
  1709. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1710. tx_descriptor->data0 = cpu_to_le32(tx->frame_data0);
  1711. /* move to next descriptor */
  1712. tx->frame_tail = lan743x_tx_next_index(tx, tx->frame_tail);
  1713. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1714. buffer_info = &tx->buffer_info[tx->frame_tail];
  1715. dma_ptr = skb_frag_dma_map(dev, fragment,
  1716. 0, fragment_length,
  1717. DMA_TO_DEVICE);
  1718. if (dma_mapping_error(dev, dma_ptr)) {
  1719. int desc_index;
  1720. /* cleanup all previously setup descriptors */
  1721. desc_index = tx->frame_first;
  1722. while (desc_index != tx->frame_tail) {
  1723. lan743x_tx_release_desc(tx, desc_index, true);
  1724. desc_index = lan743x_tx_next_index(tx, desc_index);
  1725. }
  1726. dma_wmb();
  1727. tx->frame_flags &= ~TX_FRAME_FLAG_IN_PROGRESS;
  1728. tx->frame_first = 0;
  1729. tx->frame_data0 = 0;
  1730. tx->frame_tail = 0;
  1731. return -ENOMEM;
  1732. }
  1733. tx_descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(dma_ptr));
  1734. tx_descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(dma_ptr));
  1735. tx_descriptor->data3 = cpu_to_le32((frame_length << 16) &
  1736. TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_);
  1737. buffer_info->skb = NULL;
  1738. buffer_info->dma_ptr = dma_ptr;
  1739. buffer_info->buffer_length = fragment_length;
  1740. buffer_info->flags |= TX_BUFFER_INFO_FLAG_ACTIVE;
  1741. buffer_info->flags |= TX_BUFFER_INFO_FLAG_SKB_FRAGMENT;
  1742. tx->frame_data0 = (fragment_length & TX_DESC_DATA0_BUF_LENGTH_MASK_) |
  1743. TX_DESC_DATA0_DTYPE_DATA_ |
  1744. TX_DESC_DATA0_FCS_;
  1745. /* data0 will be programmed in one of other frame assembler functions */
  1746. return 0;
  1747. }
  1748. static void lan743x_tx_frame_end(struct lan743x_tx *tx,
  1749. struct sk_buff *skb,
  1750. bool time_stamp,
  1751. bool ignore_sync)
  1752. {
  1753. /* called only from within lan743x_tx_xmit_frame
  1754. * assuming tx->ring_lock has already been acquired
  1755. */
  1756. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1757. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1758. struct lan743x_adapter *adapter = tx->adapter;
  1759. u32 tx_tail_flags = 0;
  1760. /* wrap up previous descriptor */
  1761. if ((tx->frame_data0 & TX_DESC_DATA0_DTYPE_MASK_) ==
  1762. TX_DESC_DATA0_DTYPE_DATA_) {
  1763. tx->frame_data0 |= TX_DESC_DATA0_LS_;
  1764. tx->frame_data0 |= TX_DESC_DATA0_IOC_;
  1765. }
  1766. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1767. buffer_info = &tx->buffer_info[tx->frame_tail];
  1768. buffer_info->skb = skb;
  1769. if (time_stamp)
  1770. buffer_info->flags |= TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED;
  1771. if (ignore_sync)
  1772. buffer_info->flags |= TX_BUFFER_INFO_FLAG_IGNORE_SYNC;
  1773. tx_descriptor->data0 = cpu_to_le32(tx->frame_data0);
  1774. tx->frame_tail = lan743x_tx_next_index(tx, tx->frame_tail);
  1775. tx->last_tail = tx->frame_tail;
  1776. dma_wmb();
  1777. if (tx->vector_flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET)
  1778. tx_tail_flags |= TX_TAIL_SET_TOP_INT_VEC_EN_;
  1779. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET)
  1780. tx_tail_flags |= TX_TAIL_SET_DMAC_INT_EN_ |
  1781. TX_TAIL_SET_TOP_INT_EN_;
  1782. lan743x_csr_write(adapter, TX_TAIL(tx->channel_number),
  1783. tx_tail_flags | tx->frame_tail);
  1784. tx->frame_flags &= ~TX_FRAME_FLAG_IN_PROGRESS;
  1785. }
  1786. static netdev_tx_t lan743x_tx_xmit_frame(struct lan743x_tx *tx,
  1787. struct sk_buff *skb)
  1788. {
  1789. int required_number_of_descriptors = 0;
  1790. unsigned int start_frame_length = 0;
  1791. netdev_tx_t retval = NETDEV_TX_OK;
  1792. unsigned int frame_length = 0;
  1793. unsigned int head_length = 0;
  1794. unsigned long irq_flags = 0;
  1795. bool do_timestamp = false;
  1796. bool ignore_sync = false;
  1797. struct netdev_queue *txq;
  1798. int nr_frags = 0;
  1799. bool gso = false;
  1800. int j;
  1801. required_number_of_descriptors = lan743x_tx_get_desc_cnt(tx, skb);
  1802. spin_lock_irqsave(&tx->ring_lock, irq_flags);
  1803. if (required_number_of_descriptors >
  1804. lan743x_tx_get_avail_desc(tx)) {
  1805. if (required_number_of_descriptors > (tx->ring_size - 1)) {
  1806. dev_kfree_skb_irq(skb);
  1807. } else {
  1808. /* save how many descriptors we needed to restart the queue */
  1809. tx->rqd_descriptors = required_number_of_descriptors;
  1810. retval = NETDEV_TX_BUSY;
  1811. txq = netdev_get_tx_queue(tx->adapter->netdev,
  1812. tx->channel_number);
  1813. netif_tx_stop_queue(txq);
  1814. }
  1815. goto unlock;
  1816. }
  1817. /* space available, transmit skb */
  1818. if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
  1819. (tx->ts_flags & TX_TS_FLAG_TIMESTAMPING_ENABLED) &&
  1820. (lan743x_ptp_request_tx_timestamp(tx->adapter))) {
  1821. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1822. do_timestamp = true;
  1823. if (tx->ts_flags & TX_TS_FLAG_ONE_STEP_SYNC)
  1824. ignore_sync = true;
  1825. }
  1826. head_length = skb_headlen(skb);
  1827. frame_length = skb_pagelen(skb);
  1828. nr_frags = skb_shinfo(skb)->nr_frags;
  1829. start_frame_length = frame_length;
  1830. gso = skb_is_gso(skb);
  1831. if (gso) {
  1832. start_frame_length = max(skb_shinfo(skb)->gso_size,
  1833. (unsigned short)8);
  1834. }
  1835. if (lan743x_tx_frame_start(tx,
  1836. skb->data, head_length,
  1837. start_frame_length,
  1838. do_timestamp,
  1839. skb->ip_summed == CHECKSUM_PARTIAL)) {
  1840. dev_kfree_skb_irq(skb);
  1841. goto unlock;
  1842. }
  1843. tx->frame_count++;
  1844. if (gso)
  1845. lan743x_tx_frame_add_lso(tx, frame_length, nr_frags);
  1846. if (nr_frags <= 0)
  1847. goto finish;
  1848. for (j = 0; j < nr_frags; j++) {
  1849. const skb_frag_t *frag = &(skb_shinfo(skb)->frags[j]);
  1850. if (lan743x_tx_frame_add_fragment(tx, frag, frame_length)) {
  1851. /* upon error no need to call
  1852. * lan743x_tx_frame_end
  1853. * frame assembler clean up was performed inside
  1854. * lan743x_tx_frame_add_fragment
  1855. */
  1856. dev_kfree_skb_irq(skb);
  1857. goto unlock;
  1858. }
  1859. }
  1860. finish:
  1861. lan743x_tx_frame_end(tx, skb, do_timestamp, ignore_sync);
  1862. unlock:
  1863. spin_unlock_irqrestore(&tx->ring_lock, irq_flags);
  1864. return retval;
  1865. }
  1866. static int lan743x_tx_napi_poll(struct napi_struct *napi, int weight)
  1867. {
  1868. struct lan743x_tx *tx = container_of(napi, struct lan743x_tx, napi);
  1869. struct lan743x_adapter *adapter = tx->adapter;
  1870. unsigned long irq_flags = 0;
  1871. struct netdev_queue *txq;
  1872. u32 ioc_bit = 0;
  1873. ioc_bit = DMAC_INT_BIT_TX_IOC_(tx->channel_number);
  1874. lan743x_csr_read(adapter, DMAC_INT_STS);
  1875. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C)
  1876. lan743x_csr_write(adapter, DMAC_INT_STS, ioc_bit);
  1877. spin_lock_irqsave(&tx->ring_lock, irq_flags);
  1878. /* clean up tx ring */
  1879. lan743x_tx_release_completed_descriptors(tx);
  1880. txq = netdev_get_tx_queue(adapter->netdev, tx->channel_number);
  1881. if (netif_tx_queue_stopped(txq)) {
  1882. if (tx->rqd_descriptors) {
  1883. if (tx->rqd_descriptors <=
  1884. lan743x_tx_get_avail_desc(tx)) {
  1885. tx->rqd_descriptors = 0;
  1886. netif_tx_wake_queue(txq);
  1887. }
  1888. } else {
  1889. netif_tx_wake_queue(txq);
  1890. }
  1891. }
  1892. spin_unlock_irqrestore(&tx->ring_lock, irq_flags);
  1893. if (!napi_complete(napi))
  1894. goto done;
  1895. /* enable isr */
  1896. lan743x_csr_write(adapter, INT_EN_SET,
  1897. INT_BIT_DMA_TX_(tx->channel_number));
  1898. lan743x_csr_read(adapter, INT_STS);
  1899. done:
  1900. return 0;
  1901. }
  1902. static void lan743x_tx_ring_cleanup(struct lan743x_tx *tx)
  1903. {
  1904. if (tx->head_cpu_ptr) {
  1905. dma_free_coherent(&tx->adapter->pdev->dev,
  1906. sizeof(*tx->head_cpu_ptr), tx->head_cpu_ptr,
  1907. tx->head_dma_ptr);
  1908. tx->head_cpu_ptr = NULL;
  1909. tx->head_dma_ptr = 0;
  1910. }
  1911. kfree(tx->buffer_info);
  1912. tx->buffer_info = NULL;
  1913. if (tx->ring_cpu_ptr) {
  1914. dma_free_coherent(&tx->adapter->pdev->dev,
  1915. tx->ring_allocation_size, tx->ring_cpu_ptr,
  1916. tx->ring_dma_ptr);
  1917. tx->ring_allocation_size = 0;
  1918. tx->ring_cpu_ptr = NULL;
  1919. tx->ring_dma_ptr = 0;
  1920. }
  1921. tx->ring_size = 0;
  1922. }
  1923. static int lan743x_tx_ring_init(struct lan743x_tx *tx)
  1924. {
  1925. size_t ring_allocation_size = 0;
  1926. void *cpu_ptr = NULL;
  1927. dma_addr_t dma_ptr;
  1928. int ret = -ENOMEM;
  1929. tx->ring_size = LAN743X_TX_RING_SIZE;
  1930. if (tx->ring_size & ~TX_CFG_B_TX_RING_LEN_MASK_) {
  1931. ret = -EINVAL;
  1932. goto cleanup;
  1933. }
  1934. if (dma_set_mask_and_coherent(&tx->adapter->pdev->dev,
  1935. DMA_BIT_MASK(64))) {
  1936. dev_warn(&tx->adapter->pdev->dev,
  1937. "lan743x_: No suitable DMA available\n");
  1938. ret = -ENOMEM;
  1939. goto cleanup;
  1940. }
  1941. ring_allocation_size = ALIGN(tx->ring_size *
  1942. sizeof(struct lan743x_tx_descriptor),
  1943. PAGE_SIZE);
  1944. dma_ptr = 0;
  1945. cpu_ptr = dma_alloc_coherent(&tx->adapter->pdev->dev,
  1946. ring_allocation_size, &dma_ptr, GFP_KERNEL);
  1947. if (!cpu_ptr) {
  1948. ret = -ENOMEM;
  1949. goto cleanup;
  1950. }
  1951. tx->ring_allocation_size = ring_allocation_size;
  1952. tx->ring_cpu_ptr = (struct lan743x_tx_descriptor *)cpu_ptr;
  1953. tx->ring_dma_ptr = dma_ptr;
  1954. cpu_ptr = kcalloc(tx->ring_size, sizeof(*tx->buffer_info), GFP_KERNEL);
  1955. if (!cpu_ptr) {
  1956. ret = -ENOMEM;
  1957. goto cleanup;
  1958. }
  1959. tx->buffer_info = (struct lan743x_tx_buffer_info *)cpu_ptr;
  1960. dma_ptr = 0;
  1961. cpu_ptr = dma_alloc_coherent(&tx->adapter->pdev->dev,
  1962. sizeof(*tx->head_cpu_ptr), &dma_ptr,
  1963. GFP_KERNEL);
  1964. if (!cpu_ptr) {
  1965. ret = -ENOMEM;
  1966. goto cleanup;
  1967. }
  1968. tx->head_cpu_ptr = cpu_ptr;
  1969. tx->head_dma_ptr = dma_ptr;
  1970. if (tx->head_dma_ptr & 0x3) {
  1971. ret = -ENOMEM;
  1972. goto cleanup;
  1973. }
  1974. return 0;
  1975. cleanup:
  1976. lan743x_tx_ring_cleanup(tx);
  1977. return ret;
  1978. }
  1979. static void lan743x_tx_close(struct lan743x_tx *tx)
  1980. {
  1981. struct lan743x_adapter *adapter = tx->adapter;
  1982. lan743x_csr_write(adapter,
  1983. DMAC_CMD,
  1984. DMAC_CMD_STOP_T_(tx->channel_number));
  1985. lan743x_dmac_tx_wait_till_stopped(adapter, tx->channel_number);
  1986. lan743x_csr_write(adapter,
  1987. DMAC_INT_EN_CLR,
  1988. DMAC_INT_BIT_TX_IOC_(tx->channel_number));
  1989. lan743x_csr_write(adapter, INT_EN_CLR,
  1990. INT_BIT_DMA_TX_(tx->channel_number));
  1991. napi_disable(&tx->napi);
  1992. netif_napi_del(&tx->napi);
  1993. lan743x_csr_write(adapter, FCT_TX_CTL,
  1994. FCT_TX_CTL_DIS_(tx->channel_number));
  1995. lan743x_csr_wait_for_bit(adapter, FCT_TX_CTL,
  1996. FCT_TX_CTL_EN_(tx->channel_number),
  1997. 0, 1000, 20000, 100);
  1998. lan743x_tx_release_all_descriptors(tx);
  1999. tx->rqd_descriptors = 0;
  2000. lan743x_tx_ring_cleanup(tx);
  2001. }
  2002. static int lan743x_tx_open(struct lan743x_tx *tx)
  2003. {
  2004. struct lan743x_adapter *adapter = NULL;
  2005. u32 data = 0;
  2006. int ret;
  2007. adapter = tx->adapter;
  2008. ret = lan743x_tx_ring_init(tx);
  2009. if (ret)
  2010. return ret;
  2011. /* initialize fifo */
  2012. lan743x_csr_write(adapter, FCT_TX_CTL,
  2013. FCT_TX_CTL_RESET_(tx->channel_number));
  2014. lan743x_csr_wait_for_bit(adapter, FCT_TX_CTL,
  2015. FCT_TX_CTL_RESET_(tx->channel_number),
  2016. 0, 1000, 20000, 100);
  2017. /* enable fifo */
  2018. lan743x_csr_write(adapter, FCT_TX_CTL,
  2019. FCT_TX_CTL_EN_(tx->channel_number));
  2020. /* reset tx channel */
  2021. lan743x_csr_write(adapter, DMAC_CMD,
  2022. DMAC_CMD_TX_SWR_(tx->channel_number));
  2023. lan743x_csr_wait_for_bit(adapter, DMAC_CMD,
  2024. DMAC_CMD_TX_SWR_(tx->channel_number),
  2025. 0, 1000, 20000, 100);
  2026. /* Write TX_BASE_ADDR */
  2027. lan743x_csr_write(adapter,
  2028. TX_BASE_ADDRH(tx->channel_number),
  2029. DMA_ADDR_HIGH32(tx->ring_dma_ptr));
  2030. lan743x_csr_write(adapter,
  2031. TX_BASE_ADDRL(tx->channel_number),
  2032. DMA_ADDR_LOW32(tx->ring_dma_ptr));
  2033. /* Write TX_CFG_B */
  2034. data = lan743x_csr_read(adapter, TX_CFG_B(tx->channel_number));
  2035. data &= ~TX_CFG_B_TX_RING_LEN_MASK_;
  2036. data |= ((tx->ring_size) & TX_CFG_B_TX_RING_LEN_MASK_);
  2037. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))
  2038. data |= TX_CFG_B_TDMABL_512_;
  2039. lan743x_csr_write(adapter, TX_CFG_B(tx->channel_number), data);
  2040. /* Write TX_CFG_A */
  2041. data = TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ | TX_CFG_A_TX_HP_WB_EN_;
  2042. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  2043. data |= TX_CFG_A_TX_HP_WB_ON_INT_TMR_;
  2044. data |= TX_CFG_A_TX_PF_THRES_SET_(0x10);
  2045. data |= TX_CFG_A_TX_PF_PRI_THRES_SET_(0x04);
  2046. data |= TX_CFG_A_TX_HP_WB_THRES_SET_(0x07);
  2047. }
  2048. lan743x_csr_write(adapter, TX_CFG_A(tx->channel_number), data);
  2049. /* Write TX_HEAD_WRITEBACK_ADDR */
  2050. lan743x_csr_write(adapter,
  2051. TX_HEAD_WRITEBACK_ADDRH(tx->channel_number),
  2052. DMA_ADDR_HIGH32(tx->head_dma_ptr));
  2053. lan743x_csr_write(adapter,
  2054. TX_HEAD_WRITEBACK_ADDRL(tx->channel_number),
  2055. DMA_ADDR_LOW32(tx->head_dma_ptr));
  2056. /* set last head */
  2057. tx->last_head = lan743x_csr_read(adapter, TX_HEAD(tx->channel_number));
  2058. /* write TX_TAIL */
  2059. tx->last_tail = 0;
  2060. lan743x_csr_write(adapter, TX_TAIL(tx->channel_number),
  2061. (u32)(tx->last_tail));
  2062. tx->vector_flags = lan743x_intr_get_vector_flags(adapter,
  2063. INT_BIT_DMA_TX_
  2064. (tx->channel_number));
  2065. netif_napi_add_tx_weight(adapter->netdev,
  2066. &tx->napi, lan743x_tx_napi_poll,
  2067. NAPI_POLL_WEIGHT);
  2068. napi_enable(&tx->napi);
  2069. data = 0;
  2070. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR)
  2071. data |= TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_;
  2072. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR)
  2073. data |= TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_;
  2074. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C)
  2075. data |= TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_;
  2076. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C)
  2077. data |= TX_CFG_C_TX_INT_EN_R2C_;
  2078. lan743x_csr_write(adapter, TX_CFG_C(tx->channel_number), data);
  2079. if (!(tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET))
  2080. lan743x_csr_write(adapter, INT_EN_SET,
  2081. INT_BIT_DMA_TX_(tx->channel_number));
  2082. lan743x_csr_write(adapter, DMAC_INT_EN_SET,
  2083. DMAC_INT_BIT_TX_IOC_(tx->channel_number));
  2084. /* start dmac channel */
  2085. lan743x_csr_write(adapter, DMAC_CMD,
  2086. DMAC_CMD_START_T_(tx->channel_number));
  2087. return 0;
  2088. }
  2089. static int lan743x_rx_next_index(struct lan743x_rx *rx, int index)
  2090. {
  2091. return ((++index) % rx->ring_size);
  2092. }
  2093. static void lan743x_rx_update_tail(struct lan743x_rx *rx, int index)
  2094. {
  2095. /* update the tail once per 8 descriptors */
  2096. if ((index & 7) == 7)
  2097. lan743x_csr_write(rx->adapter, RX_TAIL(rx->channel_number),
  2098. index);
  2099. }
  2100. static int lan743x_rx_init_ring_element(struct lan743x_rx *rx, int index,
  2101. gfp_t gfp)
  2102. {
  2103. struct net_device *netdev = rx->adapter->netdev;
  2104. struct device *dev = &rx->adapter->pdev->dev;
  2105. struct lan743x_rx_buffer_info *buffer_info;
  2106. unsigned int buffer_length, used_length;
  2107. struct lan743x_rx_descriptor *descriptor;
  2108. struct sk_buff *skb;
  2109. dma_addr_t dma_ptr;
  2110. buffer_length = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + RX_HEAD_PADDING;
  2111. descriptor = &rx->ring_cpu_ptr[index];
  2112. buffer_info = &rx->buffer_info[index];
  2113. skb = __netdev_alloc_skb(netdev, buffer_length, gfp);
  2114. if (!skb)
  2115. return -ENOMEM;
  2116. dma_ptr = dma_map_single(dev, skb->data, buffer_length, DMA_FROM_DEVICE);
  2117. if (dma_mapping_error(dev, dma_ptr)) {
  2118. dev_kfree_skb_any(skb);
  2119. return -ENOMEM;
  2120. }
  2121. if (buffer_info->dma_ptr) {
  2122. /* sync used area of buffer only */
  2123. if (le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_LS_)
  2124. /* frame length is valid only if LS bit is set.
  2125. * it's a safe upper bound for the used area in this
  2126. * buffer.
  2127. */
  2128. used_length = min(RX_DESC_DATA0_FRAME_LENGTH_GET_
  2129. (le32_to_cpu(descriptor->data0)),
  2130. buffer_info->buffer_length);
  2131. else
  2132. used_length = buffer_info->buffer_length;
  2133. dma_sync_single_for_cpu(dev, buffer_info->dma_ptr,
  2134. used_length,
  2135. DMA_FROM_DEVICE);
  2136. dma_unmap_single_attrs(dev, buffer_info->dma_ptr,
  2137. buffer_info->buffer_length,
  2138. DMA_FROM_DEVICE,
  2139. DMA_ATTR_SKIP_CPU_SYNC);
  2140. }
  2141. buffer_info->skb = skb;
  2142. buffer_info->dma_ptr = dma_ptr;
  2143. buffer_info->buffer_length = buffer_length;
  2144. descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(buffer_info->dma_ptr));
  2145. descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(buffer_info->dma_ptr));
  2146. descriptor->data3 = 0;
  2147. descriptor->data0 = cpu_to_le32((RX_DESC_DATA0_OWN_ |
  2148. (buffer_length & RX_DESC_DATA0_BUF_LENGTH_MASK_)));
  2149. lan743x_rx_update_tail(rx, index);
  2150. return 0;
  2151. }
  2152. static void lan743x_rx_reuse_ring_element(struct lan743x_rx *rx, int index)
  2153. {
  2154. struct lan743x_rx_buffer_info *buffer_info;
  2155. struct lan743x_rx_descriptor *descriptor;
  2156. descriptor = &rx->ring_cpu_ptr[index];
  2157. buffer_info = &rx->buffer_info[index];
  2158. descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(buffer_info->dma_ptr));
  2159. descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(buffer_info->dma_ptr));
  2160. descriptor->data3 = 0;
  2161. descriptor->data0 = cpu_to_le32((RX_DESC_DATA0_OWN_ |
  2162. ((buffer_info->buffer_length) &
  2163. RX_DESC_DATA0_BUF_LENGTH_MASK_)));
  2164. lan743x_rx_update_tail(rx, index);
  2165. }
  2166. static void lan743x_rx_release_ring_element(struct lan743x_rx *rx, int index)
  2167. {
  2168. struct lan743x_rx_buffer_info *buffer_info;
  2169. struct lan743x_rx_descriptor *descriptor;
  2170. descriptor = &rx->ring_cpu_ptr[index];
  2171. buffer_info = &rx->buffer_info[index];
  2172. memset(descriptor, 0, sizeof(*descriptor));
  2173. if (buffer_info->dma_ptr) {
  2174. dma_unmap_single(&rx->adapter->pdev->dev,
  2175. buffer_info->dma_ptr,
  2176. buffer_info->buffer_length,
  2177. DMA_FROM_DEVICE);
  2178. buffer_info->dma_ptr = 0;
  2179. }
  2180. if (buffer_info->skb) {
  2181. dev_kfree_skb(buffer_info->skb);
  2182. buffer_info->skb = NULL;
  2183. }
  2184. memset(buffer_info, 0, sizeof(*buffer_info));
  2185. }
  2186. static struct sk_buff *
  2187. lan743x_rx_trim_skb(struct sk_buff *skb, int frame_length)
  2188. {
  2189. if (skb_linearize(skb)) {
  2190. dev_kfree_skb_irq(skb);
  2191. return NULL;
  2192. }
  2193. frame_length = max_t(int, 0, frame_length - ETH_FCS_LEN);
  2194. if (skb->len > frame_length) {
  2195. skb->tail -= skb->len - frame_length;
  2196. skb->len = frame_length;
  2197. }
  2198. return skb;
  2199. }
  2200. static int lan743x_rx_process_buffer(struct lan743x_rx *rx)
  2201. {
  2202. int current_head_index = le32_to_cpu(*rx->head_cpu_ptr);
  2203. struct lan743x_rx_descriptor *descriptor, *desc_ext;
  2204. struct net_device *netdev = rx->adapter->netdev;
  2205. int result = RX_PROCESS_RESULT_NOTHING_TO_DO;
  2206. struct lan743x_rx_buffer_info *buffer_info;
  2207. int frame_length, buffer_length;
  2208. bool is_ice, is_tce, is_icsm;
  2209. int extension_index = -1;
  2210. bool is_last, is_first;
  2211. struct sk_buff *skb;
  2212. if (current_head_index < 0 || current_head_index >= rx->ring_size)
  2213. goto done;
  2214. if (rx->last_head < 0 || rx->last_head >= rx->ring_size)
  2215. goto done;
  2216. if (rx->last_head == current_head_index)
  2217. goto done;
  2218. descriptor = &rx->ring_cpu_ptr[rx->last_head];
  2219. if (le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_OWN_)
  2220. goto done;
  2221. buffer_info = &rx->buffer_info[rx->last_head];
  2222. is_last = le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_LS_;
  2223. is_first = le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_FS_;
  2224. if (is_last && le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_EXT_) {
  2225. /* extension is expected to follow */
  2226. int index = lan743x_rx_next_index(rx, rx->last_head);
  2227. if (index == current_head_index)
  2228. /* extension not yet available */
  2229. goto done;
  2230. desc_ext = &rx->ring_cpu_ptr[index];
  2231. if (le32_to_cpu(desc_ext->data0) & RX_DESC_DATA0_OWN_)
  2232. /* extension not yet available */
  2233. goto done;
  2234. if (!(le32_to_cpu(desc_ext->data0) & RX_DESC_DATA0_EXT_))
  2235. goto move_forward;
  2236. extension_index = index;
  2237. }
  2238. /* Only the last buffer in a multi-buffer frame contains the total frame
  2239. * length. The chip occasionally sends more buffers than strictly
  2240. * required to reach the total frame length.
  2241. * Handle this by adding all buffers to the skb in their entirety.
  2242. * Once the real frame length is known, trim the skb.
  2243. */
  2244. frame_length =
  2245. RX_DESC_DATA0_FRAME_LENGTH_GET_(le32_to_cpu(descriptor->data0));
  2246. buffer_length = buffer_info->buffer_length;
  2247. is_ice = le32_to_cpu(descriptor->data1) & RX_DESC_DATA1_STATUS_ICE_;
  2248. is_tce = le32_to_cpu(descriptor->data1) & RX_DESC_DATA1_STATUS_TCE_;
  2249. is_icsm = le32_to_cpu(descriptor->data1) & RX_DESC_DATA1_STATUS_ICSM_;
  2250. netdev_dbg(netdev, "%s%schunk: %d/%d",
  2251. is_first ? "first " : " ",
  2252. is_last ? "last " : " ",
  2253. frame_length, buffer_length);
  2254. /* save existing skb, allocate new skb and map to dma */
  2255. skb = buffer_info->skb;
  2256. if (lan743x_rx_init_ring_element(rx, rx->last_head,
  2257. GFP_ATOMIC | GFP_DMA)) {
  2258. /* failed to allocate next skb.
  2259. * Memory is very low.
  2260. * Drop this packet and reuse buffer.
  2261. */
  2262. lan743x_rx_reuse_ring_element(rx, rx->last_head);
  2263. /* drop packet that was being assembled */
  2264. dev_kfree_skb_irq(rx->skb_head);
  2265. rx->skb_head = NULL;
  2266. goto process_extension;
  2267. }
  2268. /* add buffers to skb via skb->frag_list */
  2269. if (is_first) {
  2270. skb_reserve(skb, RX_HEAD_PADDING);
  2271. skb_put(skb, buffer_length - RX_HEAD_PADDING);
  2272. if (rx->skb_head)
  2273. dev_kfree_skb_irq(rx->skb_head);
  2274. rx->skb_head = skb;
  2275. } else if (rx->skb_head) {
  2276. skb_put(skb, buffer_length);
  2277. if (skb_shinfo(rx->skb_head)->frag_list)
  2278. rx->skb_tail->next = skb;
  2279. else
  2280. skb_shinfo(rx->skb_head)->frag_list = skb;
  2281. rx->skb_tail = skb;
  2282. rx->skb_head->len += skb->len;
  2283. rx->skb_head->data_len += skb->len;
  2284. rx->skb_head->truesize += skb->truesize;
  2285. } else {
  2286. /* packet to assemble has already been dropped because one or
  2287. * more of its buffers could not be allocated
  2288. */
  2289. netdev_dbg(netdev, "drop buffer intended for dropped packet");
  2290. dev_kfree_skb_irq(skb);
  2291. }
  2292. process_extension:
  2293. if (extension_index >= 0) {
  2294. u32 ts_sec;
  2295. u32 ts_nsec;
  2296. ts_sec = le32_to_cpu(desc_ext->data1);
  2297. ts_nsec = (le32_to_cpu(desc_ext->data2) &
  2298. RX_DESC_DATA2_TS_NS_MASK_);
  2299. if (rx->skb_head)
  2300. skb_hwtstamps(rx->skb_head)->hwtstamp =
  2301. ktime_set(ts_sec, ts_nsec);
  2302. lan743x_rx_reuse_ring_element(rx, extension_index);
  2303. rx->last_head = extension_index;
  2304. netdev_dbg(netdev, "process extension");
  2305. }
  2306. if (is_last && rx->skb_head)
  2307. rx->skb_head = lan743x_rx_trim_skb(rx->skb_head, frame_length);
  2308. if (is_last && rx->skb_head) {
  2309. rx->skb_head->protocol = eth_type_trans(rx->skb_head,
  2310. rx->adapter->netdev);
  2311. if (rx->adapter->netdev->features & NETIF_F_RXCSUM) {
  2312. if (!is_ice && !is_tce && !is_icsm)
  2313. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2314. }
  2315. netdev_dbg(netdev, "sending %d byte frame to OS",
  2316. rx->skb_head->len);
  2317. napi_gro_receive(&rx->napi, rx->skb_head);
  2318. rx->skb_head = NULL;
  2319. }
  2320. move_forward:
  2321. /* push tail and head forward */
  2322. rx->last_tail = rx->last_head;
  2323. rx->last_head = lan743x_rx_next_index(rx, rx->last_head);
  2324. result = RX_PROCESS_RESULT_BUFFER_RECEIVED;
  2325. done:
  2326. return result;
  2327. }
  2328. static int lan743x_rx_napi_poll(struct napi_struct *napi, int weight)
  2329. {
  2330. struct lan743x_rx *rx = container_of(napi, struct lan743x_rx, napi);
  2331. struct lan743x_adapter *adapter = rx->adapter;
  2332. int result = RX_PROCESS_RESULT_NOTHING_TO_DO;
  2333. u32 rx_tail_flags = 0;
  2334. int count;
  2335. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C) {
  2336. /* clear int status bit before reading packet */
  2337. lan743x_csr_write(adapter, DMAC_INT_STS,
  2338. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2339. }
  2340. for (count = 0; count < weight; count++) {
  2341. result = lan743x_rx_process_buffer(rx);
  2342. if (result == RX_PROCESS_RESULT_NOTHING_TO_DO)
  2343. break;
  2344. }
  2345. rx->frame_count += count;
  2346. if (count == weight || result == RX_PROCESS_RESULT_BUFFER_RECEIVED)
  2347. return weight;
  2348. if (!napi_complete_done(napi, count))
  2349. return count;
  2350. /* re-arm interrupts, must write to rx tail on some chip variants */
  2351. if (rx->vector_flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET)
  2352. rx_tail_flags |= RX_TAIL_SET_TOP_INT_VEC_EN_;
  2353. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET) {
  2354. rx_tail_flags |= RX_TAIL_SET_TOP_INT_EN_;
  2355. } else {
  2356. lan743x_csr_write(adapter, INT_EN_SET,
  2357. INT_BIT_DMA_RX_(rx->channel_number));
  2358. }
  2359. if (rx_tail_flags)
  2360. lan743x_csr_write(adapter, RX_TAIL(rx->channel_number),
  2361. rx_tail_flags | rx->last_tail);
  2362. return count;
  2363. }
  2364. static void lan743x_rx_ring_cleanup(struct lan743x_rx *rx)
  2365. {
  2366. if (rx->buffer_info && rx->ring_cpu_ptr) {
  2367. int index;
  2368. for (index = 0; index < rx->ring_size; index++)
  2369. lan743x_rx_release_ring_element(rx, index);
  2370. }
  2371. if (rx->head_cpu_ptr) {
  2372. dma_free_coherent(&rx->adapter->pdev->dev,
  2373. sizeof(*rx->head_cpu_ptr), rx->head_cpu_ptr,
  2374. rx->head_dma_ptr);
  2375. rx->head_cpu_ptr = NULL;
  2376. rx->head_dma_ptr = 0;
  2377. }
  2378. kfree(rx->buffer_info);
  2379. rx->buffer_info = NULL;
  2380. if (rx->ring_cpu_ptr) {
  2381. dma_free_coherent(&rx->adapter->pdev->dev,
  2382. rx->ring_allocation_size, rx->ring_cpu_ptr,
  2383. rx->ring_dma_ptr);
  2384. rx->ring_allocation_size = 0;
  2385. rx->ring_cpu_ptr = NULL;
  2386. rx->ring_dma_ptr = 0;
  2387. }
  2388. rx->ring_size = 0;
  2389. rx->last_head = 0;
  2390. }
  2391. static int lan743x_rx_ring_init(struct lan743x_rx *rx)
  2392. {
  2393. size_t ring_allocation_size = 0;
  2394. dma_addr_t dma_ptr = 0;
  2395. void *cpu_ptr = NULL;
  2396. int ret = -ENOMEM;
  2397. int index = 0;
  2398. rx->ring_size = LAN743X_RX_RING_SIZE;
  2399. if (rx->ring_size <= 1) {
  2400. ret = -EINVAL;
  2401. goto cleanup;
  2402. }
  2403. if (rx->ring_size & ~RX_CFG_B_RX_RING_LEN_MASK_) {
  2404. ret = -EINVAL;
  2405. goto cleanup;
  2406. }
  2407. if (dma_set_mask_and_coherent(&rx->adapter->pdev->dev,
  2408. DMA_BIT_MASK(64))) {
  2409. dev_warn(&rx->adapter->pdev->dev,
  2410. "lan743x_: No suitable DMA available\n");
  2411. ret = -ENOMEM;
  2412. goto cleanup;
  2413. }
  2414. ring_allocation_size = ALIGN(rx->ring_size *
  2415. sizeof(struct lan743x_rx_descriptor),
  2416. PAGE_SIZE);
  2417. dma_ptr = 0;
  2418. cpu_ptr = dma_alloc_coherent(&rx->adapter->pdev->dev,
  2419. ring_allocation_size, &dma_ptr, GFP_KERNEL);
  2420. if (!cpu_ptr) {
  2421. ret = -ENOMEM;
  2422. goto cleanup;
  2423. }
  2424. rx->ring_allocation_size = ring_allocation_size;
  2425. rx->ring_cpu_ptr = (struct lan743x_rx_descriptor *)cpu_ptr;
  2426. rx->ring_dma_ptr = dma_ptr;
  2427. cpu_ptr = kcalloc(rx->ring_size, sizeof(*rx->buffer_info),
  2428. GFP_KERNEL);
  2429. if (!cpu_ptr) {
  2430. ret = -ENOMEM;
  2431. goto cleanup;
  2432. }
  2433. rx->buffer_info = (struct lan743x_rx_buffer_info *)cpu_ptr;
  2434. dma_ptr = 0;
  2435. cpu_ptr = dma_alloc_coherent(&rx->adapter->pdev->dev,
  2436. sizeof(*rx->head_cpu_ptr), &dma_ptr,
  2437. GFP_KERNEL);
  2438. if (!cpu_ptr) {
  2439. ret = -ENOMEM;
  2440. goto cleanup;
  2441. }
  2442. rx->head_cpu_ptr = cpu_ptr;
  2443. rx->head_dma_ptr = dma_ptr;
  2444. if (rx->head_dma_ptr & 0x3) {
  2445. ret = -ENOMEM;
  2446. goto cleanup;
  2447. }
  2448. rx->last_head = 0;
  2449. for (index = 0; index < rx->ring_size; index++) {
  2450. ret = lan743x_rx_init_ring_element(rx, index, GFP_KERNEL);
  2451. if (ret)
  2452. goto cleanup;
  2453. }
  2454. return 0;
  2455. cleanup:
  2456. netif_warn(rx->adapter, ifup, rx->adapter->netdev,
  2457. "Error allocating memory for LAN743x\n");
  2458. lan743x_rx_ring_cleanup(rx);
  2459. return ret;
  2460. }
  2461. static void lan743x_rx_close(struct lan743x_rx *rx)
  2462. {
  2463. struct lan743x_adapter *adapter = rx->adapter;
  2464. lan743x_csr_write(adapter, FCT_RX_CTL,
  2465. FCT_RX_CTL_DIS_(rx->channel_number));
  2466. lan743x_csr_wait_for_bit(adapter, FCT_RX_CTL,
  2467. FCT_RX_CTL_EN_(rx->channel_number),
  2468. 0, 1000, 20000, 100);
  2469. lan743x_csr_write(adapter, DMAC_CMD,
  2470. DMAC_CMD_STOP_R_(rx->channel_number));
  2471. lan743x_dmac_rx_wait_till_stopped(adapter, rx->channel_number);
  2472. lan743x_csr_write(adapter, DMAC_INT_EN_CLR,
  2473. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2474. lan743x_csr_write(adapter, INT_EN_CLR,
  2475. INT_BIT_DMA_RX_(rx->channel_number));
  2476. napi_disable(&rx->napi);
  2477. netif_napi_del(&rx->napi);
  2478. lan743x_rx_ring_cleanup(rx);
  2479. }
  2480. static int lan743x_rx_open(struct lan743x_rx *rx)
  2481. {
  2482. struct lan743x_adapter *adapter = rx->adapter;
  2483. u32 data = 0;
  2484. int ret;
  2485. rx->frame_count = 0;
  2486. ret = lan743x_rx_ring_init(rx);
  2487. if (ret)
  2488. goto return_error;
  2489. netif_napi_add(adapter->netdev, &rx->napi, lan743x_rx_napi_poll);
  2490. lan743x_csr_write(adapter, DMAC_CMD,
  2491. DMAC_CMD_RX_SWR_(rx->channel_number));
  2492. lan743x_csr_wait_for_bit(adapter, DMAC_CMD,
  2493. DMAC_CMD_RX_SWR_(rx->channel_number),
  2494. 0, 1000, 20000, 100);
  2495. /* set ring base address */
  2496. lan743x_csr_write(adapter,
  2497. RX_BASE_ADDRH(rx->channel_number),
  2498. DMA_ADDR_HIGH32(rx->ring_dma_ptr));
  2499. lan743x_csr_write(adapter,
  2500. RX_BASE_ADDRL(rx->channel_number),
  2501. DMA_ADDR_LOW32(rx->ring_dma_ptr));
  2502. /* set rx write back address */
  2503. lan743x_csr_write(adapter,
  2504. RX_HEAD_WRITEBACK_ADDRH(rx->channel_number),
  2505. DMA_ADDR_HIGH32(rx->head_dma_ptr));
  2506. lan743x_csr_write(adapter,
  2507. RX_HEAD_WRITEBACK_ADDRL(rx->channel_number),
  2508. DMA_ADDR_LOW32(rx->head_dma_ptr));
  2509. data = RX_CFG_A_RX_HP_WB_EN_;
  2510. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  2511. data |= (RX_CFG_A_RX_WB_ON_INT_TMR_ |
  2512. RX_CFG_A_RX_WB_THRES_SET_(0x7) |
  2513. RX_CFG_A_RX_PF_THRES_SET_(16) |
  2514. RX_CFG_A_RX_PF_PRI_THRES_SET_(4));
  2515. }
  2516. /* set RX_CFG_A */
  2517. lan743x_csr_write(adapter,
  2518. RX_CFG_A(rx->channel_number), data);
  2519. /* set RX_CFG_B */
  2520. data = lan743x_csr_read(adapter, RX_CFG_B(rx->channel_number));
  2521. data &= ~RX_CFG_B_RX_PAD_MASK_;
  2522. if (!RX_HEAD_PADDING)
  2523. data |= RX_CFG_B_RX_PAD_0_;
  2524. else
  2525. data |= RX_CFG_B_RX_PAD_2_;
  2526. data &= ~RX_CFG_B_RX_RING_LEN_MASK_;
  2527. data |= ((rx->ring_size) & RX_CFG_B_RX_RING_LEN_MASK_);
  2528. data |= RX_CFG_B_TS_ALL_RX_;
  2529. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))
  2530. data |= RX_CFG_B_RDMABL_512_;
  2531. lan743x_csr_write(adapter, RX_CFG_B(rx->channel_number), data);
  2532. rx->vector_flags = lan743x_intr_get_vector_flags(adapter,
  2533. INT_BIT_DMA_RX_
  2534. (rx->channel_number));
  2535. /* set RX_CFG_C */
  2536. data = 0;
  2537. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR)
  2538. data |= RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_;
  2539. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR)
  2540. data |= RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_;
  2541. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C)
  2542. data |= RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_;
  2543. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C)
  2544. data |= RX_CFG_C_RX_INT_EN_R2C_;
  2545. lan743x_csr_write(adapter, RX_CFG_C(rx->channel_number), data);
  2546. rx->last_tail = ((u32)(rx->ring_size - 1));
  2547. lan743x_csr_write(adapter, RX_TAIL(rx->channel_number),
  2548. rx->last_tail);
  2549. rx->last_head = lan743x_csr_read(adapter, RX_HEAD(rx->channel_number));
  2550. if (rx->last_head) {
  2551. ret = -EIO;
  2552. goto napi_delete;
  2553. }
  2554. napi_enable(&rx->napi);
  2555. lan743x_csr_write(adapter, INT_EN_SET,
  2556. INT_BIT_DMA_RX_(rx->channel_number));
  2557. lan743x_csr_write(adapter, DMAC_INT_STS,
  2558. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2559. lan743x_csr_write(adapter, DMAC_INT_EN_SET,
  2560. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2561. lan743x_csr_write(adapter, DMAC_CMD,
  2562. DMAC_CMD_START_R_(rx->channel_number));
  2563. /* initialize fifo */
  2564. lan743x_csr_write(adapter, FCT_RX_CTL,
  2565. FCT_RX_CTL_RESET_(rx->channel_number));
  2566. lan743x_csr_wait_for_bit(adapter, FCT_RX_CTL,
  2567. FCT_RX_CTL_RESET_(rx->channel_number),
  2568. 0, 1000, 20000, 100);
  2569. lan743x_csr_write(adapter, FCT_FLOW(rx->channel_number),
  2570. FCT_FLOW_CTL_REQ_EN_ |
  2571. FCT_FLOW_CTL_ON_THRESHOLD_SET_(0x2A) |
  2572. FCT_FLOW_CTL_OFF_THRESHOLD_SET_(0xA));
  2573. /* enable fifo */
  2574. lan743x_csr_write(adapter, FCT_RX_CTL,
  2575. FCT_RX_CTL_EN_(rx->channel_number));
  2576. return 0;
  2577. napi_delete:
  2578. netif_napi_del(&rx->napi);
  2579. lan743x_rx_ring_cleanup(rx);
  2580. return_error:
  2581. return ret;
  2582. }
  2583. static int lan743x_netdev_close(struct net_device *netdev)
  2584. {
  2585. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2586. int index;
  2587. for (index = 0; index < adapter->used_tx_channels; index++)
  2588. lan743x_tx_close(&adapter->tx[index]);
  2589. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++)
  2590. lan743x_rx_close(&adapter->rx[index]);
  2591. lan743x_ptp_close(adapter);
  2592. lan743x_phy_close(adapter);
  2593. lan743x_mac_close(adapter);
  2594. lan743x_intr_close(adapter);
  2595. return 0;
  2596. }
  2597. static int lan743x_netdev_open(struct net_device *netdev)
  2598. {
  2599. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2600. int index;
  2601. int ret;
  2602. ret = lan743x_intr_open(adapter);
  2603. if (ret)
  2604. goto return_error;
  2605. ret = lan743x_mac_open(adapter);
  2606. if (ret)
  2607. goto close_intr;
  2608. ret = lan743x_phy_open(adapter);
  2609. if (ret)
  2610. goto close_mac;
  2611. ret = lan743x_ptp_open(adapter);
  2612. if (ret)
  2613. goto close_phy;
  2614. lan743x_rfe_open(adapter);
  2615. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  2616. ret = lan743x_rx_open(&adapter->rx[index]);
  2617. if (ret)
  2618. goto close_rx;
  2619. }
  2620. for (index = 0; index < adapter->used_tx_channels; index++) {
  2621. ret = lan743x_tx_open(&adapter->tx[index]);
  2622. if (ret)
  2623. goto close_tx;
  2624. }
  2625. return 0;
  2626. close_tx:
  2627. for (index = 0; index < adapter->used_tx_channels; index++) {
  2628. if (adapter->tx[index].ring_cpu_ptr)
  2629. lan743x_tx_close(&adapter->tx[index]);
  2630. }
  2631. close_rx:
  2632. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  2633. if (adapter->rx[index].ring_cpu_ptr)
  2634. lan743x_rx_close(&adapter->rx[index]);
  2635. }
  2636. lan743x_ptp_close(adapter);
  2637. close_phy:
  2638. lan743x_phy_close(adapter);
  2639. close_mac:
  2640. lan743x_mac_close(adapter);
  2641. close_intr:
  2642. lan743x_intr_close(adapter);
  2643. return_error:
  2644. netif_warn(adapter, ifup, adapter->netdev,
  2645. "Error opening LAN743x\n");
  2646. return ret;
  2647. }
  2648. static netdev_tx_t lan743x_netdev_xmit_frame(struct sk_buff *skb,
  2649. struct net_device *netdev)
  2650. {
  2651. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2652. u8 ch = 0;
  2653. if (adapter->is_pci11x1x)
  2654. ch = skb->queue_mapping % PCI11X1X_USED_TX_CHANNELS;
  2655. return lan743x_tx_xmit_frame(&adapter->tx[ch], skb);
  2656. }
  2657. static int lan743x_netdev_ioctl(struct net_device *netdev,
  2658. struct ifreq *ifr, int cmd)
  2659. {
  2660. if (!netif_running(netdev))
  2661. return -EINVAL;
  2662. if (cmd == SIOCSHWTSTAMP)
  2663. return lan743x_ptp_ioctl(netdev, ifr, cmd);
  2664. return phy_mii_ioctl(netdev->phydev, ifr, cmd);
  2665. }
  2666. static void lan743x_netdev_set_multicast(struct net_device *netdev)
  2667. {
  2668. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2669. lan743x_rfe_set_multicast(adapter);
  2670. }
  2671. static int lan743x_netdev_change_mtu(struct net_device *netdev, int new_mtu)
  2672. {
  2673. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2674. int ret = 0;
  2675. ret = lan743x_mac_set_mtu(adapter, new_mtu);
  2676. if (!ret)
  2677. netdev->mtu = new_mtu;
  2678. return ret;
  2679. }
  2680. static void lan743x_netdev_get_stats64(struct net_device *netdev,
  2681. struct rtnl_link_stats64 *stats)
  2682. {
  2683. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2684. stats->rx_packets = lan743x_csr_read(adapter, STAT_RX_TOTAL_FRAMES);
  2685. stats->tx_packets = lan743x_csr_read(adapter, STAT_TX_TOTAL_FRAMES);
  2686. stats->rx_bytes = lan743x_csr_read(adapter,
  2687. STAT_RX_UNICAST_BYTE_COUNT) +
  2688. lan743x_csr_read(adapter,
  2689. STAT_RX_BROADCAST_BYTE_COUNT) +
  2690. lan743x_csr_read(adapter,
  2691. STAT_RX_MULTICAST_BYTE_COUNT);
  2692. stats->tx_bytes = lan743x_csr_read(adapter,
  2693. STAT_TX_UNICAST_BYTE_COUNT) +
  2694. lan743x_csr_read(adapter,
  2695. STAT_TX_BROADCAST_BYTE_COUNT) +
  2696. lan743x_csr_read(adapter,
  2697. STAT_TX_MULTICAST_BYTE_COUNT);
  2698. stats->rx_errors = lan743x_csr_read(adapter, STAT_RX_FCS_ERRORS) +
  2699. lan743x_csr_read(adapter,
  2700. STAT_RX_ALIGNMENT_ERRORS) +
  2701. lan743x_csr_read(adapter, STAT_RX_JABBER_ERRORS) +
  2702. lan743x_csr_read(adapter,
  2703. STAT_RX_UNDERSIZE_FRAME_ERRORS) +
  2704. lan743x_csr_read(adapter,
  2705. STAT_RX_OVERSIZE_FRAME_ERRORS);
  2706. stats->tx_errors = lan743x_csr_read(adapter, STAT_TX_FCS_ERRORS) +
  2707. lan743x_csr_read(adapter,
  2708. STAT_TX_EXCESS_DEFERRAL_ERRORS) +
  2709. lan743x_csr_read(adapter, STAT_TX_CARRIER_ERRORS);
  2710. stats->rx_dropped = lan743x_csr_read(adapter,
  2711. STAT_RX_DROPPED_FRAMES);
  2712. stats->tx_dropped = lan743x_csr_read(adapter,
  2713. STAT_TX_EXCESSIVE_COLLISION);
  2714. stats->multicast = lan743x_csr_read(adapter,
  2715. STAT_RX_MULTICAST_FRAMES) +
  2716. lan743x_csr_read(adapter,
  2717. STAT_TX_MULTICAST_FRAMES);
  2718. stats->collisions = lan743x_csr_read(adapter,
  2719. STAT_TX_SINGLE_COLLISIONS) +
  2720. lan743x_csr_read(adapter,
  2721. STAT_TX_MULTIPLE_COLLISIONS) +
  2722. lan743x_csr_read(adapter,
  2723. STAT_TX_LATE_COLLISIONS);
  2724. }
  2725. static int lan743x_netdev_set_mac_address(struct net_device *netdev,
  2726. void *addr)
  2727. {
  2728. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2729. struct sockaddr *sock_addr = addr;
  2730. int ret;
  2731. ret = eth_prepare_mac_addr_change(netdev, sock_addr);
  2732. if (ret)
  2733. return ret;
  2734. eth_hw_addr_set(netdev, sock_addr->sa_data);
  2735. lan743x_mac_set_address(adapter, sock_addr->sa_data);
  2736. lan743x_rfe_update_mac_address(adapter);
  2737. return 0;
  2738. }
  2739. static const struct net_device_ops lan743x_netdev_ops = {
  2740. .ndo_open = lan743x_netdev_open,
  2741. .ndo_stop = lan743x_netdev_close,
  2742. .ndo_start_xmit = lan743x_netdev_xmit_frame,
  2743. .ndo_eth_ioctl = lan743x_netdev_ioctl,
  2744. .ndo_set_rx_mode = lan743x_netdev_set_multicast,
  2745. .ndo_change_mtu = lan743x_netdev_change_mtu,
  2746. .ndo_get_stats64 = lan743x_netdev_get_stats64,
  2747. .ndo_set_mac_address = lan743x_netdev_set_mac_address,
  2748. };
  2749. static void lan743x_hardware_cleanup(struct lan743x_adapter *adapter)
  2750. {
  2751. lan743x_csr_write(adapter, INT_EN_CLR, 0xFFFFFFFF);
  2752. }
  2753. static void lan743x_mdiobus_cleanup(struct lan743x_adapter *adapter)
  2754. {
  2755. mdiobus_unregister(adapter->mdiobus);
  2756. }
  2757. static void lan743x_full_cleanup(struct lan743x_adapter *adapter)
  2758. {
  2759. unregister_netdev(adapter->netdev);
  2760. lan743x_mdiobus_cleanup(adapter);
  2761. lan743x_hardware_cleanup(adapter);
  2762. lan743x_pci_cleanup(adapter);
  2763. }
  2764. static int lan743x_hardware_init(struct lan743x_adapter *adapter,
  2765. struct pci_dev *pdev)
  2766. {
  2767. struct lan743x_tx *tx;
  2768. int index;
  2769. int ret;
  2770. adapter->is_pci11x1x = is_pci11x1x_chip(adapter);
  2771. if (adapter->is_pci11x1x) {
  2772. adapter->max_tx_channels = PCI11X1X_MAX_TX_CHANNELS;
  2773. adapter->used_tx_channels = PCI11X1X_USED_TX_CHANNELS;
  2774. adapter->max_vector_count = PCI11X1X_MAX_VECTOR_COUNT;
  2775. pci11x1x_strap_get_status(adapter);
  2776. spin_lock_init(&adapter->eth_syslock_spinlock);
  2777. mutex_init(&adapter->sgmii_rw_lock);
  2778. } else {
  2779. adapter->max_tx_channels = LAN743X_MAX_TX_CHANNELS;
  2780. adapter->used_tx_channels = LAN743X_USED_TX_CHANNELS;
  2781. adapter->max_vector_count = LAN743X_MAX_VECTOR_COUNT;
  2782. }
  2783. adapter->intr.irq = adapter->pdev->irq;
  2784. lan743x_csr_write(adapter, INT_EN_CLR, 0xFFFFFFFF);
  2785. ret = lan743x_gpio_init(adapter);
  2786. if (ret)
  2787. return ret;
  2788. ret = lan743x_mac_init(adapter);
  2789. if (ret)
  2790. return ret;
  2791. ret = lan743x_phy_init(adapter);
  2792. if (ret)
  2793. return ret;
  2794. ret = lan743x_ptp_init(adapter);
  2795. if (ret)
  2796. return ret;
  2797. lan743x_rfe_update_mac_address(adapter);
  2798. ret = lan743x_dmac_init(adapter);
  2799. if (ret)
  2800. return ret;
  2801. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  2802. adapter->rx[index].adapter = adapter;
  2803. adapter->rx[index].channel_number = index;
  2804. }
  2805. for (index = 0; index < adapter->used_tx_channels; index++) {
  2806. tx = &adapter->tx[index];
  2807. tx->adapter = adapter;
  2808. tx->channel_number = index;
  2809. spin_lock_init(&tx->ring_lock);
  2810. }
  2811. return 0;
  2812. }
  2813. static int lan743x_mdiobus_init(struct lan743x_adapter *adapter)
  2814. {
  2815. u32 sgmii_ctl;
  2816. int ret;
  2817. adapter->mdiobus = devm_mdiobus_alloc(&adapter->pdev->dev);
  2818. if (!(adapter->mdiobus)) {
  2819. ret = -ENOMEM;
  2820. goto return_error;
  2821. }
  2822. adapter->mdiobus->priv = (void *)adapter;
  2823. if (adapter->is_pci11x1x) {
  2824. if (adapter->is_sgmii_en) {
  2825. sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
  2826. sgmii_ctl |= SGMII_CTL_SGMII_ENABLE_;
  2827. sgmii_ctl &= ~SGMII_CTL_SGMII_POWER_DN_;
  2828. lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
  2829. netif_dbg(adapter, drv, adapter->netdev,
  2830. "SGMII operation\n");
  2831. adapter->mdiobus->probe_capabilities = MDIOBUS_C22_C45;
  2832. adapter->mdiobus->read = lan743x_mdiobus_c45_read;
  2833. adapter->mdiobus->write = lan743x_mdiobus_c45_write;
  2834. adapter->mdiobus->name = "lan743x-mdiobus-c45";
  2835. netif_dbg(adapter, drv, adapter->netdev,
  2836. "lan743x-mdiobus-c45\n");
  2837. } else {
  2838. sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
  2839. sgmii_ctl &= ~SGMII_CTL_SGMII_ENABLE_;
  2840. sgmii_ctl |= SGMII_CTL_SGMII_POWER_DN_;
  2841. lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
  2842. netif_dbg(adapter, drv, adapter->netdev,
  2843. "RGMII operation\n");
  2844. // Only C22 support when RGMII I/F
  2845. adapter->mdiobus->probe_capabilities = MDIOBUS_C22;
  2846. adapter->mdiobus->read = lan743x_mdiobus_read;
  2847. adapter->mdiobus->write = lan743x_mdiobus_write;
  2848. adapter->mdiobus->name = "lan743x-mdiobus";
  2849. netif_dbg(adapter, drv, adapter->netdev,
  2850. "lan743x-mdiobus\n");
  2851. }
  2852. } else {
  2853. adapter->mdiobus->read = lan743x_mdiobus_read;
  2854. adapter->mdiobus->write = lan743x_mdiobus_write;
  2855. adapter->mdiobus->name = "lan743x-mdiobus";
  2856. netif_dbg(adapter, drv, adapter->netdev, "lan743x-mdiobus\n");
  2857. }
  2858. snprintf(adapter->mdiobus->id, MII_BUS_ID_SIZE,
  2859. "pci-%s", pci_name(adapter->pdev));
  2860. if ((adapter->csr.id_rev & ID_REV_ID_MASK_) == ID_REV_ID_LAN7430_)
  2861. /* LAN7430 uses internal phy at address 1 */
  2862. adapter->mdiobus->phy_mask = ~(u32)BIT(1);
  2863. /* register mdiobus */
  2864. ret = mdiobus_register(adapter->mdiobus);
  2865. if (ret < 0)
  2866. goto return_error;
  2867. return 0;
  2868. return_error:
  2869. return ret;
  2870. }
  2871. /* lan743x_pcidev_probe - Device Initialization Routine
  2872. * @pdev: PCI device information struct
  2873. * @id: entry in lan743x_pci_tbl
  2874. *
  2875. * Returns 0 on success, negative on failure
  2876. *
  2877. * initializes an adapter identified by a pci_dev structure.
  2878. * The OS initialization, configuring of the adapter private structure,
  2879. * and a hardware reset occur.
  2880. **/
  2881. static int lan743x_pcidev_probe(struct pci_dev *pdev,
  2882. const struct pci_device_id *id)
  2883. {
  2884. struct lan743x_adapter *adapter = NULL;
  2885. struct net_device *netdev = NULL;
  2886. int ret = -ENODEV;
  2887. if (id->device == PCI_DEVICE_ID_SMSC_A011 ||
  2888. id->device == PCI_DEVICE_ID_SMSC_A041) {
  2889. netdev = devm_alloc_etherdev_mqs(&pdev->dev,
  2890. sizeof(struct lan743x_adapter),
  2891. PCI11X1X_USED_TX_CHANNELS,
  2892. LAN743X_USED_RX_CHANNELS);
  2893. } else {
  2894. netdev = devm_alloc_etherdev_mqs(&pdev->dev,
  2895. sizeof(struct lan743x_adapter),
  2896. LAN743X_USED_TX_CHANNELS,
  2897. LAN743X_USED_RX_CHANNELS);
  2898. }
  2899. if (!netdev)
  2900. goto return_error;
  2901. SET_NETDEV_DEV(netdev, &pdev->dev);
  2902. pci_set_drvdata(pdev, netdev);
  2903. adapter = netdev_priv(netdev);
  2904. adapter->netdev = netdev;
  2905. adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  2906. NETIF_MSG_LINK | NETIF_MSG_IFUP |
  2907. NETIF_MSG_IFDOWN | NETIF_MSG_TX_QUEUED;
  2908. netdev->max_mtu = LAN743X_MAX_FRAME_SIZE;
  2909. of_get_mac_address(pdev->dev.of_node, adapter->mac_address);
  2910. ret = lan743x_pci_init(adapter, pdev);
  2911. if (ret)
  2912. goto return_error;
  2913. ret = lan743x_csr_init(adapter);
  2914. if (ret)
  2915. goto cleanup_pci;
  2916. ret = lan743x_hardware_init(adapter, pdev);
  2917. if (ret)
  2918. goto cleanup_pci;
  2919. ret = lan743x_mdiobus_init(adapter);
  2920. if (ret)
  2921. goto cleanup_hardware;
  2922. adapter->netdev->netdev_ops = &lan743x_netdev_ops;
  2923. adapter->netdev->ethtool_ops = &lan743x_ethtool_ops;
  2924. adapter->netdev->features = NETIF_F_SG | NETIF_F_TSO |
  2925. NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  2926. adapter->netdev->hw_features = adapter->netdev->features;
  2927. /* carrier off reporting is important to ethtool even BEFORE open */
  2928. netif_carrier_off(netdev);
  2929. ret = register_netdev(adapter->netdev);
  2930. if (ret < 0)
  2931. goto cleanup_mdiobus;
  2932. return 0;
  2933. cleanup_mdiobus:
  2934. lan743x_mdiobus_cleanup(adapter);
  2935. cleanup_hardware:
  2936. lan743x_hardware_cleanup(adapter);
  2937. cleanup_pci:
  2938. lan743x_pci_cleanup(adapter);
  2939. return_error:
  2940. pr_warn("Initialization failed\n");
  2941. return ret;
  2942. }
  2943. /**
  2944. * lan743x_pcidev_remove - Device Removal Routine
  2945. * @pdev: PCI device information struct
  2946. *
  2947. * this is called by the PCI subsystem to alert the driver
  2948. * that it should release a PCI device. This could be caused by a
  2949. * Hot-Plug event, or because the driver is going to be removed from
  2950. * memory.
  2951. **/
  2952. static void lan743x_pcidev_remove(struct pci_dev *pdev)
  2953. {
  2954. struct net_device *netdev = pci_get_drvdata(pdev);
  2955. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2956. lan743x_full_cleanup(adapter);
  2957. }
  2958. static void lan743x_pcidev_shutdown(struct pci_dev *pdev)
  2959. {
  2960. struct net_device *netdev = pci_get_drvdata(pdev);
  2961. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2962. rtnl_lock();
  2963. netif_device_detach(netdev);
  2964. /* close netdev when netdev is at running state.
  2965. * For instance, it is true when system goes to sleep by pm-suspend
  2966. * However, it is false when system goes to sleep by suspend GUI menu
  2967. */
  2968. if (netif_running(netdev))
  2969. lan743x_netdev_close(netdev);
  2970. rtnl_unlock();
  2971. #ifdef CONFIG_PM
  2972. pci_save_state(pdev);
  2973. #endif
  2974. /* clean up lan743x portion */
  2975. lan743x_hardware_cleanup(adapter);
  2976. }
  2977. #ifdef CONFIG_PM_SLEEP
  2978. static u16 lan743x_pm_wakeframe_crc16(const u8 *buf, int len)
  2979. {
  2980. return bitrev16(crc16(0xFFFF, buf, len));
  2981. }
  2982. static void lan743x_pm_set_wol(struct lan743x_adapter *adapter)
  2983. {
  2984. const u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };
  2985. const u8 ipv6_multicast[3] = { 0x33, 0x33 };
  2986. const u8 arp_type[2] = { 0x08, 0x06 };
  2987. int mask_index;
  2988. u32 sopass;
  2989. u32 pmtctl;
  2990. u32 wucsr;
  2991. u32 macrx;
  2992. u16 crc;
  2993. for (mask_index = 0; mask_index < MAC_NUM_OF_WUF_CFG; mask_index++)
  2994. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index), 0);
  2995. /* clear wake settings */
  2996. pmtctl = lan743x_csr_read(adapter, PMT_CTL);
  2997. pmtctl |= PMT_CTL_WUPS_MASK_;
  2998. pmtctl &= ~(PMT_CTL_GPIO_WAKEUP_EN_ | PMT_CTL_EEE_WAKEUP_EN_ |
  2999. PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_ |
  3000. PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ | PMT_CTL_ETH_PHY_WAKE_EN_);
  3001. macrx = lan743x_csr_read(adapter, MAC_RX);
  3002. wucsr = 0;
  3003. mask_index = 0;
  3004. pmtctl |= PMT_CTL_ETH_PHY_D3_COLD_OVR_ | PMT_CTL_ETH_PHY_D3_OVR_;
  3005. if (adapter->wolopts & WAKE_PHY) {
  3006. pmtctl |= PMT_CTL_ETH_PHY_EDPD_PLL_CTL_;
  3007. pmtctl |= PMT_CTL_ETH_PHY_WAKE_EN_;
  3008. }
  3009. if (adapter->wolopts & WAKE_MAGIC) {
  3010. wucsr |= MAC_WUCSR_MPEN_;
  3011. macrx |= MAC_RX_RXEN_;
  3012. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3013. }
  3014. if (adapter->wolopts & WAKE_UCAST) {
  3015. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_PFDA_EN_;
  3016. macrx |= MAC_RX_RXEN_;
  3017. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3018. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3019. }
  3020. if (adapter->wolopts & WAKE_BCAST) {
  3021. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_BCST_EN_;
  3022. macrx |= MAC_RX_RXEN_;
  3023. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3024. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3025. }
  3026. if (adapter->wolopts & WAKE_MCAST) {
  3027. /* IPv4 multicast */
  3028. crc = lan743x_pm_wakeframe_crc16(ipv4_multicast, 3);
  3029. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index),
  3030. MAC_WUF_CFG_EN_ | MAC_WUF_CFG_TYPE_MCAST_ |
  3031. (0 << MAC_WUF_CFG_OFFSET_SHIFT_) |
  3032. (crc & MAC_WUF_CFG_CRC16_MASK_));
  3033. lan743x_csr_write(adapter, MAC_WUF_MASK0(mask_index), 7);
  3034. lan743x_csr_write(adapter, MAC_WUF_MASK1(mask_index), 0);
  3035. lan743x_csr_write(adapter, MAC_WUF_MASK2(mask_index), 0);
  3036. lan743x_csr_write(adapter, MAC_WUF_MASK3(mask_index), 0);
  3037. mask_index++;
  3038. /* IPv6 multicast */
  3039. crc = lan743x_pm_wakeframe_crc16(ipv6_multicast, 2);
  3040. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index),
  3041. MAC_WUF_CFG_EN_ | MAC_WUF_CFG_TYPE_MCAST_ |
  3042. (0 << MAC_WUF_CFG_OFFSET_SHIFT_) |
  3043. (crc & MAC_WUF_CFG_CRC16_MASK_));
  3044. lan743x_csr_write(adapter, MAC_WUF_MASK0(mask_index), 3);
  3045. lan743x_csr_write(adapter, MAC_WUF_MASK1(mask_index), 0);
  3046. lan743x_csr_write(adapter, MAC_WUF_MASK2(mask_index), 0);
  3047. lan743x_csr_write(adapter, MAC_WUF_MASK3(mask_index), 0);
  3048. mask_index++;
  3049. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_WAKE_EN_;
  3050. macrx |= MAC_RX_RXEN_;
  3051. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3052. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3053. }
  3054. if (adapter->wolopts & WAKE_ARP) {
  3055. /* set MAC_WUF_CFG & WUF_MASK
  3056. * for packettype (offset 12,13) = ARP (0x0806)
  3057. */
  3058. crc = lan743x_pm_wakeframe_crc16(arp_type, 2);
  3059. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index),
  3060. MAC_WUF_CFG_EN_ | MAC_WUF_CFG_TYPE_ALL_ |
  3061. (0 << MAC_WUF_CFG_OFFSET_SHIFT_) |
  3062. (crc & MAC_WUF_CFG_CRC16_MASK_));
  3063. lan743x_csr_write(adapter, MAC_WUF_MASK0(mask_index), 0x3000);
  3064. lan743x_csr_write(adapter, MAC_WUF_MASK1(mask_index), 0);
  3065. lan743x_csr_write(adapter, MAC_WUF_MASK2(mask_index), 0);
  3066. lan743x_csr_write(adapter, MAC_WUF_MASK3(mask_index), 0);
  3067. mask_index++;
  3068. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_WAKE_EN_;
  3069. macrx |= MAC_RX_RXEN_;
  3070. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3071. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3072. }
  3073. if (adapter->wolopts & WAKE_MAGICSECURE) {
  3074. sopass = *(u32 *)adapter->sopass;
  3075. lan743x_csr_write(adapter, MAC_MP_SO_LO, sopass);
  3076. sopass = *(u16 *)&adapter->sopass[4];
  3077. lan743x_csr_write(adapter, MAC_MP_SO_HI, sopass);
  3078. wucsr |= MAC_MP_SO_EN_;
  3079. }
  3080. lan743x_csr_write(adapter, MAC_WUCSR, wucsr);
  3081. lan743x_csr_write(adapter, PMT_CTL, pmtctl);
  3082. lan743x_csr_write(adapter, MAC_RX, macrx);
  3083. }
  3084. static int lan743x_pm_suspend(struct device *dev)
  3085. {
  3086. struct pci_dev *pdev = to_pci_dev(dev);
  3087. struct net_device *netdev = pci_get_drvdata(pdev);
  3088. struct lan743x_adapter *adapter = netdev_priv(netdev);
  3089. u32 data;
  3090. lan743x_pcidev_shutdown(pdev);
  3091. /* clear all wakes */
  3092. lan743x_csr_write(adapter, MAC_WUCSR, 0);
  3093. lan743x_csr_write(adapter, MAC_WUCSR2, 0);
  3094. lan743x_csr_write(adapter, MAC_WK_SRC, 0xFFFFFFFF);
  3095. if (adapter->wolopts)
  3096. lan743x_pm_set_wol(adapter);
  3097. if (adapter->is_pci11x1x) {
  3098. /* Save HW_CFG to config again in PM resume */
  3099. data = lan743x_csr_read(adapter, HW_CFG);
  3100. adapter->hw_cfg = data;
  3101. data |= (HW_CFG_RST_PROTECT_PCIE_ |
  3102. HW_CFG_D3_RESET_DIS_ |
  3103. HW_CFG_D3_VAUX_OVR_ |
  3104. HW_CFG_HOT_RESET_DIS_ |
  3105. HW_CFG_RST_PROTECT_);
  3106. lan743x_csr_write(adapter, HW_CFG, data);
  3107. }
  3108. /* Host sets PME_En, put D3hot */
  3109. return pci_prepare_to_sleep(pdev);
  3110. }
  3111. static int lan743x_pm_resume(struct device *dev)
  3112. {
  3113. struct pci_dev *pdev = to_pci_dev(dev);
  3114. struct net_device *netdev = pci_get_drvdata(pdev);
  3115. struct lan743x_adapter *adapter = netdev_priv(netdev);
  3116. int ret;
  3117. pci_set_power_state(pdev, PCI_D0);
  3118. pci_restore_state(pdev);
  3119. pci_save_state(pdev);
  3120. /* Restore HW_CFG that was saved during pm suspend */
  3121. if (adapter->is_pci11x1x)
  3122. lan743x_csr_write(adapter, HW_CFG, adapter->hw_cfg);
  3123. ret = lan743x_hardware_init(adapter, pdev);
  3124. if (ret) {
  3125. netif_err(adapter, probe, adapter->netdev,
  3126. "lan743x_hardware_init returned %d\n", ret);
  3127. lan743x_pci_cleanup(adapter);
  3128. return ret;
  3129. }
  3130. /* open netdev when netdev is at running state while resume.
  3131. * For instance, it is true when system wakesup after pm-suspend
  3132. * However, it is false when system wakes up after suspend GUI menu
  3133. */
  3134. if (netif_running(netdev))
  3135. lan743x_netdev_open(netdev);
  3136. netif_device_attach(netdev);
  3137. ret = lan743x_csr_read(adapter, MAC_WK_SRC);
  3138. netif_info(adapter, drv, adapter->netdev,
  3139. "Wakeup source : 0x%08X\n", ret);
  3140. return 0;
  3141. }
  3142. static const struct dev_pm_ops lan743x_pm_ops = {
  3143. SET_SYSTEM_SLEEP_PM_OPS(lan743x_pm_suspend, lan743x_pm_resume)
  3144. };
  3145. #endif /* CONFIG_PM_SLEEP */
  3146. static const struct pci_device_id lan743x_pcidev_tbl[] = {
  3147. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_LAN7430) },
  3148. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_LAN7431) },
  3149. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_A011) },
  3150. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_A041) },
  3151. { 0, }
  3152. };
  3153. MODULE_DEVICE_TABLE(pci, lan743x_pcidev_tbl);
  3154. static struct pci_driver lan743x_pcidev_driver = {
  3155. .name = DRIVER_NAME,
  3156. .id_table = lan743x_pcidev_tbl,
  3157. .probe = lan743x_pcidev_probe,
  3158. .remove = lan743x_pcidev_remove,
  3159. #ifdef CONFIG_PM_SLEEP
  3160. .driver.pm = &lan743x_pm_ops,
  3161. #endif
  3162. .shutdown = lan743x_pcidev_shutdown,
  3163. };
  3164. module_pci_driver(lan743x_pcidev_driver);
  3165. MODULE_AUTHOR(DRIVER_AUTHOR);
  3166. MODULE_DESCRIPTION(DRIVER_DESC);
  3167. MODULE_LICENSE("GPL");