mvmdio.c 12 KB

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  1. /*
  2. * Driver for the MDIO interface of Marvell network interfaces.
  3. *
  4. * Since the MDIO interface of Marvell network interfaces is shared
  5. * between all network interfaces, having a single driver allows to
  6. * handle concurrent accesses properly (you may have four Ethernet
  7. * ports, but they in fact share the same SMI interface to access
  8. * the MDIO bus). This driver is currently used by the mvneta and
  9. * mv643xx_eth drivers.
  10. *
  11. * Copyright (C) 2012 Marvell
  12. *
  13. * Thomas Petazzoni <[email protected]>
  14. *
  15. * This file is licensed under the terms of the GNU General Public
  16. * License version 2. This program is licensed "as is" without any
  17. * warranty of any kind, whether express or implied.
  18. */
  19. #include <linux/acpi.h>
  20. #include <linux/acpi_mdio.h>
  21. #include <linux/clk.h>
  22. #include <linux/delay.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/io.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/of_device.h>
  28. #include <linux/of_mdio.h>
  29. #include <linux/phy.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/sched.h>
  32. #include <linux/wait.h>
  33. #define MVMDIO_SMI_DATA_SHIFT 0
  34. #define MVMDIO_SMI_PHY_ADDR_SHIFT 16
  35. #define MVMDIO_SMI_PHY_REG_SHIFT 21
  36. #define MVMDIO_SMI_READ_OPERATION BIT(26)
  37. #define MVMDIO_SMI_WRITE_OPERATION 0
  38. #define MVMDIO_SMI_READ_VALID BIT(27)
  39. #define MVMDIO_SMI_BUSY BIT(28)
  40. #define MVMDIO_ERR_INT_CAUSE 0x007C
  41. #define MVMDIO_ERR_INT_SMI_DONE 0x00000010
  42. #define MVMDIO_ERR_INT_MASK 0x0080
  43. #define MVMDIO_XSMI_MGNT_REG 0x0
  44. #define MVMDIO_XSMI_PHYADDR_SHIFT 16
  45. #define MVMDIO_XSMI_DEVADDR_SHIFT 21
  46. #define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
  47. #define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
  48. #define MVMDIO_XSMI_READ_VALID BIT(29)
  49. #define MVMDIO_XSMI_BUSY BIT(30)
  50. #define MVMDIO_XSMI_ADDR_REG 0x8
  51. /*
  52. * SMI Timeout measurements:
  53. * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
  54. * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
  55. */
  56. #define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */
  57. #define MVMDIO_SMI_POLL_INTERVAL_MIN 45
  58. #define MVMDIO_SMI_POLL_INTERVAL_MAX 55
  59. #define MVMDIO_XSMI_POLL_INTERVAL_MIN 150
  60. #define MVMDIO_XSMI_POLL_INTERVAL_MAX 160
  61. struct orion_mdio_dev {
  62. void __iomem *regs;
  63. struct clk *clk[4];
  64. /*
  65. * If we have access to the error interrupt pin (which is
  66. * somewhat misnamed as it not only reflects internal errors
  67. * but also reflects SMI completion), use that to wait for
  68. * SMI access completion instead of polling the SMI busy bit.
  69. */
  70. int err_interrupt;
  71. wait_queue_head_t smi_busy_wait;
  72. };
  73. enum orion_mdio_bus_type {
  74. BUS_TYPE_SMI,
  75. BUS_TYPE_XSMI
  76. };
  77. struct orion_mdio_ops {
  78. int (*is_done)(struct orion_mdio_dev *);
  79. unsigned int poll_interval_min;
  80. unsigned int poll_interval_max;
  81. };
  82. /* Wait for the SMI unit to be ready for another operation
  83. */
  84. static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
  85. struct mii_bus *bus)
  86. {
  87. struct orion_mdio_dev *dev = bus->priv;
  88. unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);
  89. unsigned long end = jiffies + timeout;
  90. int timedout = 0;
  91. while (1) {
  92. if (ops->is_done(dev))
  93. return 0;
  94. else if (timedout)
  95. break;
  96. if (dev->err_interrupt <= 0) {
  97. usleep_range(ops->poll_interval_min,
  98. ops->poll_interval_max);
  99. if (time_is_before_jiffies(end))
  100. ++timedout;
  101. } else {
  102. /* wait_event_timeout does not guarantee a delay of at
  103. * least one whole jiffie, so timeout must be no less
  104. * than two.
  105. */
  106. if (timeout < 2)
  107. timeout = 2;
  108. wait_event_timeout(dev->smi_busy_wait,
  109. ops->is_done(dev), timeout);
  110. ++timedout;
  111. }
  112. }
  113. dev_err(bus->parent, "Timeout: SMI busy for too long\n");
  114. return -ETIMEDOUT;
  115. }
  116. static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
  117. {
  118. return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
  119. }
  120. static const struct orion_mdio_ops orion_mdio_smi_ops = {
  121. .is_done = orion_mdio_smi_is_done,
  122. .poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,
  123. .poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,
  124. };
  125. static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
  126. int regnum)
  127. {
  128. struct orion_mdio_dev *dev = bus->priv;
  129. u32 val;
  130. int ret;
  131. if (regnum & MII_ADDR_C45)
  132. return -EOPNOTSUPP;
  133. ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
  134. if (ret < 0)
  135. return ret;
  136. writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
  137. (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
  138. MVMDIO_SMI_READ_OPERATION),
  139. dev->regs);
  140. ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
  141. if (ret < 0)
  142. return ret;
  143. val = readl(dev->regs);
  144. if (!(val & MVMDIO_SMI_READ_VALID)) {
  145. dev_err(bus->parent, "SMI bus read not valid\n");
  146. return -ENODEV;
  147. }
  148. return val & GENMASK(15, 0);
  149. }
  150. static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
  151. int regnum, u16 value)
  152. {
  153. struct orion_mdio_dev *dev = bus->priv;
  154. int ret;
  155. if (regnum & MII_ADDR_C45)
  156. return -EOPNOTSUPP;
  157. ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
  158. if (ret < 0)
  159. return ret;
  160. writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
  161. (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
  162. MVMDIO_SMI_WRITE_OPERATION |
  163. (value << MVMDIO_SMI_DATA_SHIFT)),
  164. dev->regs);
  165. return 0;
  166. }
  167. static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
  168. {
  169. return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
  170. }
  171. static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
  172. .is_done = orion_mdio_xsmi_is_done,
  173. .poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,
  174. .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,
  175. };
  176. static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id,
  177. int regnum)
  178. {
  179. struct orion_mdio_dev *dev = bus->priv;
  180. u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
  181. int ret;
  182. if (!(regnum & MII_ADDR_C45))
  183. return -EOPNOTSUPP;
  184. ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
  185. if (ret < 0)
  186. return ret;
  187. writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
  188. writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
  189. (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
  190. MVMDIO_XSMI_READ_OPERATION,
  191. dev->regs + MVMDIO_XSMI_MGNT_REG);
  192. ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
  193. if (ret < 0)
  194. return ret;
  195. if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
  196. MVMDIO_XSMI_READ_VALID)) {
  197. dev_err(bus->parent, "XSMI bus read not valid\n");
  198. return -ENODEV;
  199. }
  200. return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
  201. }
  202. static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id,
  203. int regnum, u16 value)
  204. {
  205. struct orion_mdio_dev *dev = bus->priv;
  206. u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
  207. int ret;
  208. if (!(regnum & MII_ADDR_C45))
  209. return -EOPNOTSUPP;
  210. ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
  211. if (ret < 0)
  212. return ret;
  213. writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
  214. writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
  215. (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
  216. MVMDIO_XSMI_WRITE_OPERATION | value,
  217. dev->regs + MVMDIO_XSMI_MGNT_REG);
  218. return 0;
  219. }
  220. static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
  221. {
  222. struct orion_mdio_dev *dev = dev_id;
  223. if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
  224. MVMDIO_ERR_INT_SMI_DONE) {
  225. writel(~MVMDIO_ERR_INT_SMI_DONE,
  226. dev->regs + MVMDIO_ERR_INT_CAUSE);
  227. wake_up(&dev->smi_busy_wait);
  228. return IRQ_HANDLED;
  229. }
  230. return IRQ_NONE;
  231. }
  232. static int orion_mdio_probe(struct platform_device *pdev)
  233. {
  234. enum orion_mdio_bus_type type;
  235. struct resource *r;
  236. struct mii_bus *bus;
  237. struct orion_mdio_dev *dev;
  238. int i, ret;
  239. type = (enum orion_mdio_bus_type)device_get_match_data(&pdev->dev);
  240. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  241. if (!r) {
  242. dev_err(&pdev->dev, "No SMI register address given\n");
  243. return -ENODEV;
  244. }
  245. bus = devm_mdiobus_alloc_size(&pdev->dev,
  246. sizeof(struct orion_mdio_dev));
  247. if (!bus)
  248. return -ENOMEM;
  249. switch (type) {
  250. case BUS_TYPE_SMI:
  251. bus->read = orion_mdio_smi_read;
  252. bus->write = orion_mdio_smi_write;
  253. break;
  254. case BUS_TYPE_XSMI:
  255. bus->read = orion_mdio_xsmi_read;
  256. bus->write = orion_mdio_xsmi_write;
  257. break;
  258. }
  259. bus->name = "orion_mdio_bus";
  260. snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
  261. dev_name(&pdev->dev));
  262. bus->parent = &pdev->dev;
  263. dev = bus->priv;
  264. dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  265. if (!dev->regs) {
  266. dev_err(&pdev->dev, "Unable to remap SMI register\n");
  267. return -ENODEV;
  268. }
  269. init_waitqueue_head(&dev->smi_busy_wait);
  270. if (pdev->dev.of_node) {
  271. for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
  272. dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
  273. if (PTR_ERR(dev->clk[i]) == -EPROBE_DEFER) {
  274. ret = -EPROBE_DEFER;
  275. goto out_clk;
  276. }
  277. if (IS_ERR(dev->clk[i]))
  278. break;
  279. clk_prepare_enable(dev->clk[i]);
  280. }
  281. if (!IS_ERR(of_clk_get(pdev->dev.of_node,
  282. ARRAY_SIZE(dev->clk))))
  283. dev_warn(&pdev->dev,
  284. "unsupported number of clocks, limiting to the first "
  285. __stringify(ARRAY_SIZE(dev->clk)) "\n");
  286. } else {
  287. dev->clk[0] = clk_get(&pdev->dev, NULL);
  288. if (PTR_ERR(dev->clk[0]) == -EPROBE_DEFER) {
  289. ret = -EPROBE_DEFER;
  290. goto out_clk;
  291. }
  292. if (!IS_ERR(dev->clk[0]))
  293. clk_prepare_enable(dev->clk[0]);
  294. }
  295. dev->err_interrupt = platform_get_irq_optional(pdev, 0);
  296. if (dev->err_interrupt > 0 &&
  297. resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
  298. dev_err(&pdev->dev,
  299. "disabling interrupt, resource size is too small\n");
  300. dev->err_interrupt = 0;
  301. }
  302. if (dev->err_interrupt > 0) {
  303. ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
  304. orion_mdio_err_irq,
  305. IRQF_SHARED, pdev->name, dev);
  306. if (ret)
  307. goto out_mdio;
  308. writel(MVMDIO_ERR_INT_SMI_DONE,
  309. dev->regs + MVMDIO_ERR_INT_MASK);
  310. } else if (dev->err_interrupt == -EPROBE_DEFER) {
  311. ret = -EPROBE_DEFER;
  312. goto out_mdio;
  313. }
  314. /* For the platforms not supporting DT/ACPI fall-back
  315. * to mdiobus_register via of_mdiobus_register.
  316. */
  317. if (is_acpi_node(pdev->dev.fwnode))
  318. ret = acpi_mdiobus_register(bus, pdev->dev.fwnode);
  319. else
  320. ret = of_mdiobus_register(bus, pdev->dev.of_node);
  321. if (ret < 0) {
  322. dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
  323. goto out_mdio;
  324. }
  325. platform_set_drvdata(pdev, bus);
  326. return 0;
  327. out_mdio:
  328. if (dev->err_interrupt > 0)
  329. writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
  330. out_clk:
  331. for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
  332. if (IS_ERR(dev->clk[i]))
  333. break;
  334. clk_disable_unprepare(dev->clk[i]);
  335. clk_put(dev->clk[i]);
  336. }
  337. return ret;
  338. }
  339. static int orion_mdio_remove(struct platform_device *pdev)
  340. {
  341. struct mii_bus *bus = platform_get_drvdata(pdev);
  342. struct orion_mdio_dev *dev = bus->priv;
  343. int i;
  344. if (dev->err_interrupt > 0)
  345. writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
  346. mdiobus_unregister(bus);
  347. for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
  348. if (IS_ERR(dev->clk[i]))
  349. break;
  350. clk_disable_unprepare(dev->clk[i]);
  351. clk_put(dev->clk[i]);
  352. }
  353. return 0;
  354. }
  355. static const struct of_device_id orion_mdio_match[] = {
  356. { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
  357. { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
  358. { }
  359. };
  360. MODULE_DEVICE_TABLE(of, orion_mdio_match);
  361. #ifdef CONFIG_ACPI
  362. static const struct acpi_device_id orion_mdio_acpi_match[] = {
  363. { "MRVL0100", BUS_TYPE_SMI },
  364. { "MRVL0101", BUS_TYPE_XSMI },
  365. { },
  366. };
  367. MODULE_DEVICE_TABLE(acpi, orion_mdio_acpi_match);
  368. #endif
  369. static struct platform_driver orion_mdio_driver = {
  370. .probe = orion_mdio_probe,
  371. .remove = orion_mdio_remove,
  372. .driver = {
  373. .name = "orion-mdio",
  374. .of_match_table = orion_mdio_match,
  375. .acpi_match_table = ACPI_PTR(orion_mdio_acpi_match),
  376. },
  377. };
  378. module_platform_driver(orion_mdio_driver);
  379. MODULE_DESCRIPTION("Marvell MDIO interface driver");
  380. MODULE_AUTHOR("Thomas Petazzoni <[email protected]>");
  381. MODULE_LICENSE("GPL");
  382. MODULE_ALIAS("platform:orion-mdio");