jme.c 73 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
  4. *
  5. * Copyright 2008 JMicron Technology Corporation
  6. * https://www.jmicron.com/
  7. * Copyright (c) 2009 - 2010 Guo-Fu Tseng <[email protected]>
  8. *
  9. * Author: Guo-Fu Tseng <[email protected]>
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/pci.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/etherdevice.h>
  17. #include <linux/ethtool.h>
  18. #include <linux/mii.h>
  19. #include <linux/crc32.h>
  20. #include <linux/delay.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/in.h>
  23. #include <linux/ip.h>
  24. #include <linux/ipv6.h>
  25. #include <linux/tcp.h>
  26. #include <linux/udp.h>
  27. #include <linux/if_vlan.h>
  28. #include <linux/slab.h>
  29. #include <linux/jiffies.h>
  30. #include <net/ip6_checksum.h>
  31. #include "jme.h"
  32. static int force_pseudohp = -1;
  33. static int no_pseudohp = -1;
  34. static int no_extplug = -1;
  35. module_param(force_pseudohp, int, 0);
  36. MODULE_PARM_DESC(force_pseudohp,
  37. "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
  38. module_param(no_pseudohp, int, 0);
  39. MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
  40. module_param(no_extplug, int, 0);
  41. MODULE_PARM_DESC(no_extplug,
  42. "Do not use external plug signal for pseudo hot-plug.");
  43. static int
  44. jme_mdio_read(struct net_device *netdev, int phy, int reg)
  45. {
  46. struct jme_adapter *jme = netdev_priv(netdev);
  47. int i, val, again = (reg == MII_BMSR) ? 1 : 0;
  48. read_again:
  49. jwrite32(jme, JME_SMI, SMI_OP_REQ |
  50. smi_phy_addr(phy) |
  51. smi_reg_addr(reg));
  52. wmb();
  53. for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  54. udelay(20);
  55. val = jread32(jme, JME_SMI);
  56. if ((val & SMI_OP_REQ) == 0)
  57. break;
  58. }
  59. if (i == 0) {
  60. pr_err("phy(%d) read timeout : %d\n", phy, reg);
  61. return 0;
  62. }
  63. if (again--)
  64. goto read_again;
  65. return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
  66. }
  67. static void
  68. jme_mdio_write(struct net_device *netdev,
  69. int phy, int reg, int val)
  70. {
  71. struct jme_adapter *jme = netdev_priv(netdev);
  72. int i;
  73. jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
  74. ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
  75. smi_phy_addr(phy) | smi_reg_addr(reg));
  76. wmb();
  77. for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  78. udelay(20);
  79. if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
  80. break;
  81. }
  82. if (i == 0)
  83. pr_err("phy(%d) write timeout : %d\n", phy, reg);
  84. }
  85. static inline void
  86. jme_reset_phy_processor(struct jme_adapter *jme)
  87. {
  88. u32 val;
  89. jme_mdio_write(jme->dev,
  90. jme->mii_if.phy_id,
  91. MII_ADVERTISE, ADVERTISE_ALL |
  92. ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  93. if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
  94. jme_mdio_write(jme->dev,
  95. jme->mii_if.phy_id,
  96. MII_CTRL1000,
  97. ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  98. val = jme_mdio_read(jme->dev,
  99. jme->mii_if.phy_id,
  100. MII_BMCR);
  101. jme_mdio_write(jme->dev,
  102. jme->mii_if.phy_id,
  103. MII_BMCR, val | BMCR_RESET);
  104. }
  105. static void
  106. jme_setup_wakeup_frame(struct jme_adapter *jme,
  107. const u32 *mask, u32 crc, int fnr)
  108. {
  109. int i;
  110. /*
  111. * Setup CRC pattern
  112. */
  113. jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
  114. wmb();
  115. jwrite32(jme, JME_WFODP, crc);
  116. wmb();
  117. /*
  118. * Setup Mask
  119. */
  120. for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
  121. jwrite32(jme, JME_WFOI,
  122. ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
  123. (fnr & WFOI_FRAME_SEL));
  124. wmb();
  125. jwrite32(jme, JME_WFODP, mask[i]);
  126. wmb();
  127. }
  128. }
  129. static inline void
  130. jme_mac_rxclk_off(struct jme_adapter *jme)
  131. {
  132. jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
  133. jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
  134. }
  135. static inline void
  136. jme_mac_rxclk_on(struct jme_adapter *jme)
  137. {
  138. jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
  139. jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
  140. }
  141. static inline void
  142. jme_mac_txclk_off(struct jme_adapter *jme)
  143. {
  144. jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
  145. jwrite32f(jme, JME_GHC, jme->reg_ghc);
  146. }
  147. static inline void
  148. jme_mac_txclk_on(struct jme_adapter *jme)
  149. {
  150. u32 speed = jme->reg_ghc & GHC_SPEED;
  151. if (speed == GHC_SPEED_1000M)
  152. jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
  153. else
  154. jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
  155. jwrite32f(jme, JME_GHC, jme->reg_ghc);
  156. }
  157. static inline void
  158. jme_reset_ghc_speed(struct jme_adapter *jme)
  159. {
  160. jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
  161. jwrite32f(jme, JME_GHC, jme->reg_ghc);
  162. }
  163. static inline void
  164. jme_reset_250A2_workaround(struct jme_adapter *jme)
  165. {
  166. jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
  167. GPREG1_RSSPATCH);
  168. jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
  169. }
  170. static inline void
  171. jme_assert_ghc_reset(struct jme_adapter *jme)
  172. {
  173. jme->reg_ghc |= GHC_SWRST;
  174. jwrite32f(jme, JME_GHC, jme->reg_ghc);
  175. }
  176. static inline void
  177. jme_clear_ghc_reset(struct jme_adapter *jme)
  178. {
  179. jme->reg_ghc &= ~GHC_SWRST;
  180. jwrite32f(jme, JME_GHC, jme->reg_ghc);
  181. }
  182. static void
  183. jme_reset_mac_processor(struct jme_adapter *jme)
  184. {
  185. static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
  186. u32 crc = 0xCDCDCDCD;
  187. u32 gpreg0;
  188. int i;
  189. jme_reset_ghc_speed(jme);
  190. jme_reset_250A2_workaround(jme);
  191. jme_mac_rxclk_on(jme);
  192. jme_mac_txclk_on(jme);
  193. udelay(1);
  194. jme_assert_ghc_reset(jme);
  195. udelay(1);
  196. jme_mac_rxclk_off(jme);
  197. jme_mac_txclk_off(jme);
  198. udelay(1);
  199. jme_clear_ghc_reset(jme);
  200. udelay(1);
  201. jme_mac_rxclk_on(jme);
  202. jme_mac_txclk_on(jme);
  203. udelay(1);
  204. jme_mac_rxclk_off(jme);
  205. jme_mac_txclk_off(jme);
  206. jwrite32(jme, JME_RXDBA_LO, 0x00000000);
  207. jwrite32(jme, JME_RXDBA_HI, 0x00000000);
  208. jwrite32(jme, JME_RXQDC, 0x00000000);
  209. jwrite32(jme, JME_RXNDA, 0x00000000);
  210. jwrite32(jme, JME_TXDBA_LO, 0x00000000);
  211. jwrite32(jme, JME_TXDBA_HI, 0x00000000);
  212. jwrite32(jme, JME_TXQDC, 0x00000000);
  213. jwrite32(jme, JME_TXNDA, 0x00000000);
  214. jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
  215. jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
  216. for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
  217. jme_setup_wakeup_frame(jme, mask, crc, i);
  218. if (jme->fpgaver)
  219. gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
  220. else
  221. gpreg0 = GPREG0_DEFAULT;
  222. jwrite32(jme, JME_GPREG0, gpreg0);
  223. }
  224. static inline void
  225. jme_clear_pm_enable_wol(struct jme_adapter *jme)
  226. {
  227. jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
  228. }
  229. static inline void
  230. jme_clear_pm_disable_wol(struct jme_adapter *jme)
  231. {
  232. jwrite32(jme, JME_PMCS, PMCS_STMASK);
  233. }
  234. static int
  235. jme_reload_eeprom(struct jme_adapter *jme)
  236. {
  237. u32 val;
  238. int i;
  239. val = jread32(jme, JME_SMBCSR);
  240. if (val & SMBCSR_EEPROMD) {
  241. val |= SMBCSR_CNACK;
  242. jwrite32(jme, JME_SMBCSR, val);
  243. val |= SMBCSR_RELOAD;
  244. jwrite32(jme, JME_SMBCSR, val);
  245. mdelay(12);
  246. for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
  247. mdelay(1);
  248. if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
  249. break;
  250. }
  251. if (i == 0) {
  252. pr_err("eeprom reload timeout\n");
  253. return -EIO;
  254. }
  255. }
  256. return 0;
  257. }
  258. static void
  259. jme_load_macaddr(struct net_device *netdev)
  260. {
  261. struct jme_adapter *jme = netdev_priv(netdev);
  262. unsigned char macaddr[ETH_ALEN];
  263. u32 val;
  264. spin_lock_bh(&jme->macaddr_lock);
  265. val = jread32(jme, JME_RXUMA_LO);
  266. macaddr[0] = (val >> 0) & 0xFF;
  267. macaddr[1] = (val >> 8) & 0xFF;
  268. macaddr[2] = (val >> 16) & 0xFF;
  269. macaddr[3] = (val >> 24) & 0xFF;
  270. val = jread32(jme, JME_RXUMA_HI);
  271. macaddr[4] = (val >> 0) & 0xFF;
  272. macaddr[5] = (val >> 8) & 0xFF;
  273. eth_hw_addr_set(netdev, macaddr);
  274. spin_unlock_bh(&jme->macaddr_lock);
  275. }
  276. static inline void
  277. jme_set_rx_pcc(struct jme_adapter *jme, int p)
  278. {
  279. switch (p) {
  280. case PCC_OFF:
  281. jwrite32(jme, JME_PCCRX0,
  282. ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
  283. ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
  284. break;
  285. case PCC_P1:
  286. jwrite32(jme, JME_PCCRX0,
  287. ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
  288. ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
  289. break;
  290. case PCC_P2:
  291. jwrite32(jme, JME_PCCRX0,
  292. ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
  293. ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
  294. break;
  295. case PCC_P3:
  296. jwrite32(jme, JME_PCCRX0,
  297. ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
  298. ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
  299. break;
  300. default:
  301. break;
  302. }
  303. wmb();
  304. if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
  305. netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
  306. }
  307. static void
  308. jme_start_irq(struct jme_adapter *jme)
  309. {
  310. register struct dynpcc_info *dpi = &(jme->dpi);
  311. jme_set_rx_pcc(jme, PCC_P1);
  312. dpi->cur = PCC_P1;
  313. dpi->attempt = PCC_P1;
  314. dpi->cnt = 0;
  315. jwrite32(jme, JME_PCCTX,
  316. ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
  317. ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
  318. PCCTXQ0_EN
  319. );
  320. /*
  321. * Enable Interrupts
  322. */
  323. jwrite32(jme, JME_IENS, INTR_ENABLE);
  324. }
  325. static inline void
  326. jme_stop_irq(struct jme_adapter *jme)
  327. {
  328. /*
  329. * Disable Interrupts
  330. */
  331. jwrite32f(jme, JME_IENC, INTR_ENABLE);
  332. }
  333. static u32
  334. jme_linkstat_from_phy(struct jme_adapter *jme)
  335. {
  336. u32 phylink, bmsr;
  337. phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
  338. bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
  339. if (bmsr & BMSR_ANCOMP)
  340. phylink |= PHY_LINK_AUTONEG_COMPLETE;
  341. return phylink;
  342. }
  343. static inline void
  344. jme_set_phyfifo_5level(struct jme_adapter *jme)
  345. {
  346. jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
  347. }
  348. static inline void
  349. jme_set_phyfifo_8level(struct jme_adapter *jme)
  350. {
  351. jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
  352. }
  353. static int
  354. jme_check_link(struct net_device *netdev, int testonly)
  355. {
  356. struct jme_adapter *jme = netdev_priv(netdev);
  357. u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
  358. char linkmsg[64];
  359. int rc = 0;
  360. linkmsg[0] = '\0';
  361. if (jme->fpgaver)
  362. phylink = jme_linkstat_from_phy(jme);
  363. else
  364. phylink = jread32(jme, JME_PHY_LINK);
  365. if (phylink & PHY_LINK_UP) {
  366. if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
  367. /*
  368. * If we did not enable AN
  369. * Speed/Duplex Info should be obtained from SMI
  370. */
  371. phylink = PHY_LINK_UP;
  372. bmcr = jme_mdio_read(jme->dev,
  373. jme->mii_if.phy_id,
  374. MII_BMCR);
  375. phylink |= ((bmcr & BMCR_SPEED1000) &&
  376. (bmcr & BMCR_SPEED100) == 0) ?
  377. PHY_LINK_SPEED_1000M :
  378. (bmcr & BMCR_SPEED100) ?
  379. PHY_LINK_SPEED_100M :
  380. PHY_LINK_SPEED_10M;
  381. phylink |= (bmcr & BMCR_FULLDPLX) ?
  382. PHY_LINK_DUPLEX : 0;
  383. strcat(linkmsg, "Forced: ");
  384. } else {
  385. /*
  386. * Keep polling for speed/duplex resolve complete
  387. */
  388. while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
  389. --cnt) {
  390. udelay(1);
  391. if (jme->fpgaver)
  392. phylink = jme_linkstat_from_phy(jme);
  393. else
  394. phylink = jread32(jme, JME_PHY_LINK);
  395. }
  396. if (!cnt)
  397. pr_err("Waiting speed resolve timeout\n");
  398. strcat(linkmsg, "ANed: ");
  399. }
  400. if (jme->phylink == phylink) {
  401. rc = 1;
  402. goto out;
  403. }
  404. if (testonly)
  405. goto out;
  406. jme->phylink = phylink;
  407. /*
  408. * The speed/duplex setting of jme->reg_ghc already cleared
  409. * by jme_reset_mac_processor()
  410. */
  411. switch (phylink & PHY_LINK_SPEED_MASK) {
  412. case PHY_LINK_SPEED_10M:
  413. jme->reg_ghc |= GHC_SPEED_10M;
  414. strcat(linkmsg, "10 Mbps, ");
  415. break;
  416. case PHY_LINK_SPEED_100M:
  417. jme->reg_ghc |= GHC_SPEED_100M;
  418. strcat(linkmsg, "100 Mbps, ");
  419. break;
  420. case PHY_LINK_SPEED_1000M:
  421. jme->reg_ghc |= GHC_SPEED_1000M;
  422. strcat(linkmsg, "1000 Mbps, ");
  423. break;
  424. default:
  425. break;
  426. }
  427. if (phylink & PHY_LINK_DUPLEX) {
  428. jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
  429. jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
  430. jme->reg_ghc |= GHC_DPX;
  431. } else {
  432. jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
  433. TXMCS_BACKOFF |
  434. TXMCS_CARRIERSENSE |
  435. TXMCS_COLLISION);
  436. jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
  437. }
  438. jwrite32(jme, JME_GHC, jme->reg_ghc);
  439. if (is_buggy250(jme->pdev->device, jme->chiprev)) {
  440. jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
  441. GPREG1_RSSPATCH);
  442. if (!(phylink & PHY_LINK_DUPLEX))
  443. jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
  444. switch (phylink & PHY_LINK_SPEED_MASK) {
  445. case PHY_LINK_SPEED_10M:
  446. jme_set_phyfifo_8level(jme);
  447. jme->reg_gpreg1 |= GPREG1_RSSPATCH;
  448. break;
  449. case PHY_LINK_SPEED_100M:
  450. jme_set_phyfifo_5level(jme);
  451. jme->reg_gpreg1 |= GPREG1_RSSPATCH;
  452. break;
  453. case PHY_LINK_SPEED_1000M:
  454. jme_set_phyfifo_8level(jme);
  455. break;
  456. default:
  457. break;
  458. }
  459. }
  460. jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
  461. strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
  462. "Full-Duplex, " :
  463. "Half-Duplex, ");
  464. strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
  465. "MDI-X" :
  466. "MDI");
  467. netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
  468. netif_carrier_on(netdev);
  469. } else {
  470. if (testonly)
  471. goto out;
  472. netif_info(jme, link, jme->dev, "Link is down\n");
  473. jme->phylink = 0;
  474. netif_carrier_off(netdev);
  475. }
  476. out:
  477. return rc;
  478. }
  479. static int
  480. jme_setup_tx_resources(struct jme_adapter *jme)
  481. {
  482. struct jme_ring *txring = &(jme->txring[0]);
  483. txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
  484. TX_RING_ALLOC_SIZE(jme->tx_ring_size),
  485. &(txring->dmaalloc),
  486. GFP_ATOMIC);
  487. if (!txring->alloc)
  488. goto err_set_null;
  489. /*
  490. * 16 Bytes align
  491. */
  492. txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
  493. RING_DESC_ALIGN);
  494. txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
  495. txring->next_to_use = 0;
  496. atomic_set(&txring->next_to_clean, 0);
  497. atomic_set(&txring->nr_free, jme->tx_ring_size);
  498. txring->bufinf = kcalloc(jme->tx_ring_size,
  499. sizeof(struct jme_buffer_info),
  500. GFP_ATOMIC);
  501. if (unlikely(!(txring->bufinf)))
  502. goto err_free_txring;
  503. return 0;
  504. err_free_txring:
  505. dma_free_coherent(&(jme->pdev->dev),
  506. TX_RING_ALLOC_SIZE(jme->tx_ring_size),
  507. txring->alloc,
  508. txring->dmaalloc);
  509. err_set_null:
  510. txring->desc = NULL;
  511. txring->dmaalloc = 0;
  512. txring->dma = 0;
  513. txring->bufinf = NULL;
  514. return -ENOMEM;
  515. }
  516. static void
  517. jme_free_tx_resources(struct jme_adapter *jme)
  518. {
  519. int i;
  520. struct jme_ring *txring = &(jme->txring[0]);
  521. struct jme_buffer_info *txbi;
  522. if (txring->alloc) {
  523. if (txring->bufinf) {
  524. for (i = 0 ; i < jme->tx_ring_size ; ++i) {
  525. txbi = txring->bufinf + i;
  526. if (txbi->skb) {
  527. dev_kfree_skb(txbi->skb);
  528. txbi->skb = NULL;
  529. }
  530. txbi->mapping = 0;
  531. txbi->len = 0;
  532. txbi->nr_desc = 0;
  533. txbi->start_xmit = 0;
  534. }
  535. kfree(txring->bufinf);
  536. }
  537. dma_free_coherent(&(jme->pdev->dev),
  538. TX_RING_ALLOC_SIZE(jme->tx_ring_size),
  539. txring->alloc,
  540. txring->dmaalloc);
  541. txring->alloc = NULL;
  542. txring->desc = NULL;
  543. txring->dmaalloc = 0;
  544. txring->dma = 0;
  545. txring->bufinf = NULL;
  546. }
  547. txring->next_to_use = 0;
  548. atomic_set(&txring->next_to_clean, 0);
  549. atomic_set(&txring->nr_free, 0);
  550. }
  551. static inline void
  552. jme_enable_tx_engine(struct jme_adapter *jme)
  553. {
  554. /*
  555. * Select Queue 0
  556. */
  557. jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
  558. wmb();
  559. /*
  560. * Setup TX Queue 0 DMA Bass Address
  561. */
  562. jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
  563. jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
  564. jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
  565. /*
  566. * Setup TX Descptor Count
  567. */
  568. jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
  569. /*
  570. * Enable TX Engine
  571. */
  572. wmb();
  573. jwrite32f(jme, JME_TXCS, jme->reg_txcs |
  574. TXCS_SELECT_QUEUE0 |
  575. TXCS_ENABLE);
  576. /*
  577. * Start clock for TX MAC Processor
  578. */
  579. jme_mac_txclk_on(jme);
  580. }
  581. static inline void
  582. jme_disable_tx_engine(struct jme_adapter *jme)
  583. {
  584. int i;
  585. u32 val;
  586. /*
  587. * Disable TX Engine
  588. */
  589. jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
  590. wmb();
  591. val = jread32(jme, JME_TXCS);
  592. for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
  593. mdelay(1);
  594. val = jread32(jme, JME_TXCS);
  595. rmb();
  596. }
  597. if (!i)
  598. pr_err("Disable TX engine timeout\n");
  599. /*
  600. * Stop clock for TX MAC Processor
  601. */
  602. jme_mac_txclk_off(jme);
  603. }
  604. static void
  605. jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
  606. {
  607. struct jme_ring *rxring = &(jme->rxring[0]);
  608. register struct rxdesc *rxdesc = rxring->desc;
  609. struct jme_buffer_info *rxbi = rxring->bufinf;
  610. rxdesc += i;
  611. rxbi += i;
  612. rxdesc->dw[0] = 0;
  613. rxdesc->dw[1] = 0;
  614. rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
  615. rxdesc->desc1.bufaddrl = cpu_to_le32(
  616. (__u64)rxbi->mapping & 0xFFFFFFFFUL);
  617. rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
  618. if (jme->dev->features & NETIF_F_HIGHDMA)
  619. rxdesc->desc1.flags = RXFLAG_64BIT;
  620. wmb();
  621. rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
  622. }
  623. static int
  624. jme_make_new_rx_buf(struct jme_adapter *jme, int i)
  625. {
  626. struct jme_ring *rxring = &(jme->rxring[0]);
  627. struct jme_buffer_info *rxbi = rxring->bufinf + i;
  628. struct sk_buff *skb;
  629. dma_addr_t mapping;
  630. skb = netdev_alloc_skb(jme->dev,
  631. jme->dev->mtu + RX_EXTRA_LEN);
  632. if (unlikely(!skb))
  633. return -ENOMEM;
  634. mapping = dma_map_page(&jme->pdev->dev, virt_to_page(skb->data),
  635. offset_in_page(skb->data), skb_tailroom(skb),
  636. DMA_FROM_DEVICE);
  637. if (unlikely(dma_mapping_error(&jme->pdev->dev, mapping))) {
  638. dev_kfree_skb(skb);
  639. return -ENOMEM;
  640. }
  641. if (likely(rxbi->mapping))
  642. dma_unmap_page(&jme->pdev->dev, rxbi->mapping, rxbi->len,
  643. DMA_FROM_DEVICE);
  644. rxbi->skb = skb;
  645. rxbi->len = skb_tailroom(skb);
  646. rxbi->mapping = mapping;
  647. return 0;
  648. }
  649. static void
  650. jme_free_rx_buf(struct jme_adapter *jme, int i)
  651. {
  652. struct jme_ring *rxring = &(jme->rxring[0]);
  653. struct jme_buffer_info *rxbi = rxring->bufinf;
  654. rxbi += i;
  655. if (rxbi->skb) {
  656. dma_unmap_page(&jme->pdev->dev, rxbi->mapping, rxbi->len,
  657. DMA_FROM_DEVICE);
  658. dev_kfree_skb(rxbi->skb);
  659. rxbi->skb = NULL;
  660. rxbi->mapping = 0;
  661. rxbi->len = 0;
  662. }
  663. }
  664. static void
  665. jme_free_rx_resources(struct jme_adapter *jme)
  666. {
  667. int i;
  668. struct jme_ring *rxring = &(jme->rxring[0]);
  669. if (rxring->alloc) {
  670. if (rxring->bufinf) {
  671. for (i = 0 ; i < jme->rx_ring_size ; ++i)
  672. jme_free_rx_buf(jme, i);
  673. kfree(rxring->bufinf);
  674. }
  675. dma_free_coherent(&(jme->pdev->dev),
  676. RX_RING_ALLOC_SIZE(jme->rx_ring_size),
  677. rxring->alloc,
  678. rxring->dmaalloc);
  679. rxring->alloc = NULL;
  680. rxring->desc = NULL;
  681. rxring->dmaalloc = 0;
  682. rxring->dma = 0;
  683. rxring->bufinf = NULL;
  684. }
  685. rxring->next_to_use = 0;
  686. atomic_set(&rxring->next_to_clean, 0);
  687. }
  688. static int
  689. jme_setup_rx_resources(struct jme_adapter *jme)
  690. {
  691. int i;
  692. struct jme_ring *rxring = &(jme->rxring[0]);
  693. rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
  694. RX_RING_ALLOC_SIZE(jme->rx_ring_size),
  695. &(rxring->dmaalloc),
  696. GFP_ATOMIC);
  697. if (!rxring->alloc)
  698. goto err_set_null;
  699. /*
  700. * 16 Bytes align
  701. */
  702. rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
  703. RING_DESC_ALIGN);
  704. rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
  705. rxring->next_to_use = 0;
  706. atomic_set(&rxring->next_to_clean, 0);
  707. rxring->bufinf = kcalloc(jme->rx_ring_size,
  708. sizeof(struct jme_buffer_info),
  709. GFP_ATOMIC);
  710. if (unlikely(!(rxring->bufinf)))
  711. goto err_free_rxring;
  712. /*
  713. * Initiallize Receive Descriptors
  714. */
  715. for (i = 0 ; i < jme->rx_ring_size ; ++i) {
  716. if (unlikely(jme_make_new_rx_buf(jme, i))) {
  717. jme_free_rx_resources(jme);
  718. return -ENOMEM;
  719. }
  720. jme_set_clean_rxdesc(jme, i);
  721. }
  722. return 0;
  723. err_free_rxring:
  724. dma_free_coherent(&(jme->pdev->dev),
  725. RX_RING_ALLOC_SIZE(jme->rx_ring_size),
  726. rxring->alloc,
  727. rxring->dmaalloc);
  728. err_set_null:
  729. rxring->desc = NULL;
  730. rxring->dmaalloc = 0;
  731. rxring->dma = 0;
  732. rxring->bufinf = NULL;
  733. return -ENOMEM;
  734. }
  735. static inline void
  736. jme_enable_rx_engine(struct jme_adapter *jme)
  737. {
  738. /*
  739. * Select Queue 0
  740. */
  741. jwrite32(jme, JME_RXCS, jme->reg_rxcs |
  742. RXCS_QUEUESEL_Q0);
  743. wmb();
  744. /*
  745. * Setup RX DMA Bass Address
  746. */
  747. jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
  748. jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
  749. jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
  750. /*
  751. * Setup RX Descriptor Count
  752. */
  753. jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
  754. /*
  755. * Setup Unicast Filter
  756. */
  757. jme_set_unicastaddr(jme->dev);
  758. jme_set_multi(jme->dev);
  759. /*
  760. * Enable RX Engine
  761. */
  762. wmb();
  763. jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
  764. RXCS_QUEUESEL_Q0 |
  765. RXCS_ENABLE |
  766. RXCS_QST);
  767. /*
  768. * Start clock for RX MAC Processor
  769. */
  770. jme_mac_rxclk_on(jme);
  771. }
  772. static inline void
  773. jme_restart_rx_engine(struct jme_adapter *jme)
  774. {
  775. /*
  776. * Start RX Engine
  777. */
  778. jwrite32(jme, JME_RXCS, jme->reg_rxcs |
  779. RXCS_QUEUESEL_Q0 |
  780. RXCS_ENABLE |
  781. RXCS_QST);
  782. }
  783. static inline void
  784. jme_disable_rx_engine(struct jme_adapter *jme)
  785. {
  786. int i;
  787. u32 val;
  788. /*
  789. * Disable RX Engine
  790. */
  791. jwrite32(jme, JME_RXCS, jme->reg_rxcs);
  792. wmb();
  793. val = jread32(jme, JME_RXCS);
  794. for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
  795. mdelay(1);
  796. val = jread32(jme, JME_RXCS);
  797. rmb();
  798. }
  799. if (!i)
  800. pr_err("Disable RX engine timeout\n");
  801. /*
  802. * Stop clock for RX MAC Processor
  803. */
  804. jme_mac_rxclk_off(jme);
  805. }
  806. static u16
  807. jme_udpsum(struct sk_buff *skb)
  808. {
  809. u16 csum = 0xFFFFu;
  810. if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
  811. return csum;
  812. if (skb->protocol != htons(ETH_P_IP))
  813. return csum;
  814. skb_set_network_header(skb, ETH_HLEN);
  815. if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
  816. (skb->len < (ETH_HLEN +
  817. (ip_hdr(skb)->ihl << 2) +
  818. sizeof(struct udphdr)))) {
  819. skb_reset_network_header(skb);
  820. return csum;
  821. }
  822. skb_set_transport_header(skb,
  823. ETH_HLEN + (ip_hdr(skb)->ihl << 2));
  824. csum = udp_hdr(skb)->check;
  825. skb_reset_transport_header(skb);
  826. skb_reset_network_header(skb);
  827. return csum;
  828. }
  829. static int
  830. jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
  831. {
  832. if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
  833. return false;
  834. if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
  835. == RXWBFLAG_TCPON)) {
  836. if (flags & RXWBFLAG_IPV4)
  837. netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
  838. return false;
  839. }
  840. if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
  841. == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
  842. if (flags & RXWBFLAG_IPV4)
  843. netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
  844. return false;
  845. }
  846. if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
  847. == RXWBFLAG_IPV4)) {
  848. netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
  849. return false;
  850. }
  851. return true;
  852. }
  853. static void
  854. jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
  855. {
  856. struct jme_ring *rxring = &(jme->rxring[0]);
  857. struct rxdesc *rxdesc = rxring->desc;
  858. struct jme_buffer_info *rxbi = rxring->bufinf;
  859. struct sk_buff *skb;
  860. int framesize;
  861. rxdesc += idx;
  862. rxbi += idx;
  863. skb = rxbi->skb;
  864. dma_sync_single_for_cpu(&jme->pdev->dev, rxbi->mapping, rxbi->len,
  865. DMA_FROM_DEVICE);
  866. if (unlikely(jme_make_new_rx_buf(jme, idx))) {
  867. dma_sync_single_for_device(&jme->pdev->dev, rxbi->mapping,
  868. rxbi->len, DMA_FROM_DEVICE);
  869. ++(NET_STAT(jme).rx_dropped);
  870. } else {
  871. framesize = le16_to_cpu(rxdesc->descwb.framesize)
  872. - RX_PREPAD_SIZE;
  873. skb_reserve(skb, RX_PREPAD_SIZE);
  874. skb_put(skb, framesize);
  875. skb->protocol = eth_type_trans(skb, jme->dev);
  876. if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
  877. skb->ip_summed = CHECKSUM_UNNECESSARY;
  878. else
  879. skb_checksum_none_assert(skb);
  880. if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
  881. u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
  882. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
  883. NET_STAT(jme).rx_bytes += 4;
  884. }
  885. jme->jme_rx(skb);
  886. if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
  887. cpu_to_le16(RXWBFLAG_DEST_MUL))
  888. ++(NET_STAT(jme).multicast);
  889. NET_STAT(jme).rx_bytes += framesize;
  890. ++(NET_STAT(jme).rx_packets);
  891. }
  892. jme_set_clean_rxdesc(jme, idx);
  893. }
  894. static int
  895. jme_process_receive(struct jme_adapter *jme, int limit)
  896. {
  897. struct jme_ring *rxring = &(jme->rxring[0]);
  898. struct rxdesc *rxdesc;
  899. int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
  900. if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
  901. goto out_inc;
  902. if (unlikely(atomic_read(&jme->link_changing) != 1))
  903. goto out_inc;
  904. if (unlikely(!netif_carrier_ok(jme->dev)))
  905. goto out_inc;
  906. i = atomic_read(&rxring->next_to_clean);
  907. while (limit > 0) {
  908. rxdesc = rxring->desc;
  909. rxdesc += i;
  910. if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
  911. !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
  912. goto out;
  913. --limit;
  914. rmb();
  915. desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
  916. if (unlikely(desccnt > 1 ||
  917. rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
  918. if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
  919. ++(NET_STAT(jme).rx_crc_errors);
  920. else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
  921. ++(NET_STAT(jme).rx_fifo_errors);
  922. else
  923. ++(NET_STAT(jme).rx_errors);
  924. if (desccnt > 1)
  925. limit -= desccnt - 1;
  926. for (j = i, ccnt = desccnt ; ccnt-- ; ) {
  927. jme_set_clean_rxdesc(jme, j);
  928. j = (j + 1) & (mask);
  929. }
  930. } else {
  931. jme_alloc_and_feed_skb(jme, i);
  932. }
  933. i = (i + desccnt) & (mask);
  934. }
  935. out:
  936. atomic_set(&rxring->next_to_clean, i);
  937. out_inc:
  938. atomic_inc(&jme->rx_cleaning);
  939. return limit > 0 ? limit : 0;
  940. }
  941. static void
  942. jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
  943. {
  944. if (likely(atmp == dpi->cur)) {
  945. dpi->cnt = 0;
  946. return;
  947. }
  948. if (dpi->attempt == atmp) {
  949. ++(dpi->cnt);
  950. } else {
  951. dpi->attempt = atmp;
  952. dpi->cnt = 0;
  953. }
  954. }
  955. static void
  956. jme_dynamic_pcc(struct jme_adapter *jme)
  957. {
  958. register struct dynpcc_info *dpi = &(jme->dpi);
  959. if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
  960. jme_attempt_pcc(dpi, PCC_P3);
  961. else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
  962. dpi->intr_cnt > PCC_INTR_THRESHOLD)
  963. jme_attempt_pcc(dpi, PCC_P2);
  964. else
  965. jme_attempt_pcc(dpi, PCC_P1);
  966. if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
  967. if (dpi->attempt < dpi->cur)
  968. tasklet_schedule(&jme->rxclean_task);
  969. jme_set_rx_pcc(jme, dpi->attempt);
  970. dpi->cur = dpi->attempt;
  971. dpi->cnt = 0;
  972. }
  973. }
  974. static void
  975. jme_start_pcc_timer(struct jme_adapter *jme)
  976. {
  977. struct dynpcc_info *dpi = &(jme->dpi);
  978. dpi->last_bytes = NET_STAT(jme).rx_bytes;
  979. dpi->last_pkts = NET_STAT(jme).rx_packets;
  980. dpi->intr_cnt = 0;
  981. jwrite32(jme, JME_TMCSR,
  982. TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
  983. }
  984. static inline void
  985. jme_stop_pcc_timer(struct jme_adapter *jme)
  986. {
  987. jwrite32(jme, JME_TMCSR, 0);
  988. }
  989. static void
  990. jme_shutdown_nic(struct jme_adapter *jme)
  991. {
  992. u32 phylink;
  993. phylink = jme_linkstat_from_phy(jme);
  994. if (!(phylink & PHY_LINK_UP)) {
  995. /*
  996. * Disable all interrupt before issue timer
  997. */
  998. jme_stop_irq(jme);
  999. jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
  1000. }
  1001. }
  1002. static void
  1003. jme_pcc_tasklet(struct tasklet_struct *t)
  1004. {
  1005. struct jme_adapter *jme = from_tasklet(jme, t, pcc_task);
  1006. struct net_device *netdev = jme->dev;
  1007. if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
  1008. jme_shutdown_nic(jme);
  1009. return;
  1010. }
  1011. if (unlikely(!netif_carrier_ok(netdev) ||
  1012. (atomic_read(&jme->link_changing) != 1)
  1013. )) {
  1014. jme_stop_pcc_timer(jme);
  1015. return;
  1016. }
  1017. if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
  1018. jme_dynamic_pcc(jme);
  1019. jme_start_pcc_timer(jme);
  1020. }
  1021. static inline void
  1022. jme_polling_mode(struct jme_adapter *jme)
  1023. {
  1024. jme_set_rx_pcc(jme, PCC_OFF);
  1025. }
  1026. static inline void
  1027. jme_interrupt_mode(struct jme_adapter *jme)
  1028. {
  1029. jme_set_rx_pcc(jme, PCC_P1);
  1030. }
  1031. static inline int
  1032. jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
  1033. {
  1034. u32 apmc;
  1035. apmc = jread32(jme, JME_APMC);
  1036. return apmc & JME_APMC_PSEUDO_HP_EN;
  1037. }
  1038. static void
  1039. jme_start_shutdown_timer(struct jme_adapter *jme)
  1040. {
  1041. u32 apmc;
  1042. apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
  1043. apmc &= ~JME_APMC_EPIEN_CTRL;
  1044. if (!no_extplug) {
  1045. jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
  1046. wmb();
  1047. }
  1048. jwrite32f(jme, JME_APMC, apmc);
  1049. jwrite32f(jme, JME_TIMER2, 0);
  1050. set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
  1051. jwrite32(jme, JME_TMCSR,
  1052. TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
  1053. }
  1054. static void
  1055. jme_stop_shutdown_timer(struct jme_adapter *jme)
  1056. {
  1057. u32 apmc;
  1058. jwrite32f(jme, JME_TMCSR, 0);
  1059. jwrite32f(jme, JME_TIMER2, 0);
  1060. clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
  1061. apmc = jread32(jme, JME_APMC);
  1062. apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
  1063. jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
  1064. wmb();
  1065. jwrite32f(jme, JME_APMC, apmc);
  1066. }
  1067. static void jme_link_change_work(struct work_struct *work)
  1068. {
  1069. struct jme_adapter *jme = container_of(work, struct jme_adapter, linkch_task);
  1070. struct net_device *netdev = jme->dev;
  1071. int rc;
  1072. while (!atomic_dec_and_test(&jme->link_changing)) {
  1073. atomic_inc(&jme->link_changing);
  1074. netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
  1075. while (atomic_read(&jme->link_changing) != 1)
  1076. netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
  1077. }
  1078. if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
  1079. goto out;
  1080. jme->old_mtu = netdev->mtu;
  1081. netif_stop_queue(netdev);
  1082. if (jme_pseudo_hotplug_enabled(jme))
  1083. jme_stop_shutdown_timer(jme);
  1084. jme_stop_pcc_timer(jme);
  1085. tasklet_disable(&jme->txclean_task);
  1086. tasklet_disable(&jme->rxclean_task);
  1087. tasklet_disable(&jme->rxempty_task);
  1088. if (netif_carrier_ok(netdev)) {
  1089. jme_disable_rx_engine(jme);
  1090. jme_disable_tx_engine(jme);
  1091. jme_reset_mac_processor(jme);
  1092. jme_free_rx_resources(jme);
  1093. jme_free_tx_resources(jme);
  1094. if (test_bit(JME_FLAG_POLL, &jme->flags))
  1095. jme_polling_mode(jme);
  1096. netif_carrier_off(netdev);
  1097. }
  1098. jme_check_link(netdev, 0);
  1099. if (netif_carrier_ok(netdev)) {
  1100. rc = jme_setup_rx_resources(jme);
  1101. if (rc) {
  1102. pr_err("Allocating resources for RX error, Device STOPPED!\n");
  1103. goto out_enable_tasklet;
  1104. }
  1105. rc = jme_setup_tx_resources(jme);
  1106. if (rc) {
  1107. pr_err("Allocating resources for TX error, Device STOPPED!\n");
  1108. goto err_out_free_rx_resources;
  1109. }
  1110. jme_enable_rx_engine(jme);
  1111. jme_enable_tx_engine(jme);
  1112. netif_start_queue(netdev);
  1113. if (test_bit(JME_FLAG_POLL, &jme->flags))
  1114. jme_interrupt_mode(jme);
  1115. jme_start_pcc_timer(jme);
  1116. } else if (jme_pseudo_hotplug_enabled(jme)) {
  1117. jme_start_shutdown_timer(jme);
  1118. }
  1119. goto out_enable_tasklet;
  1120. err_out_free_rx_resources:
  1121. jme_free_rx_resources(jme);
  1122. out_enable_tasklet:
  1123. tasklet_enable(&jme->txclean_task);
  1124. tasklet_enable(&jme->rxclean_task);
  1125. tasklet_enable(&jme->rxempty_task);
  1126. out:
  1127. atomic_inc(&jme->link_changing);
  1128. }
  1129. static void
  1130. jme_rx_clean_tasklet(struct tasklet_struct *t)
  1131. {
  1132. struct jme_adapter *jme = from_tasklet(jme, t, rxclean_task);
  1133. struct dynpcc_info *dpi = &(jme->dpi);
  1134. jme_process_receive(jme, jme->rx_ring_size);
  1135. ++(dpi->intr_cnt);
  1136. }
  1137. static int
  1138. jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
  1139. {
  1140. struct jme_adapter *jme = jme_napi_priv(holder);
  1141. int rest;
  1142. rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
  1143. while (atomic_read(&jme->rx_empty) > 0) {
  1144. atomic_dec(&jme->rx_empty);
  1145. ++(NET_STAT(jme).rx_dropped);
  1146. jme_restart_rx_engine(jme);
  1147. }
  1148. atomic_inc(&jme->rx_empty);
  1149. if (rest) {
  1150. JME_RX_COMPLETE(netdev, holder);
  1151. jme_interrupt_mode(jme);
  1152. }
  1153. JME_NAPI_WEIGHT_SET(budget, rest);
  1154. return JME_NAPI_WEIGHT_VAL(budget) - rest;
  1155. }
  1156. static void
  1157. jme_rx_empty_tasklet(struct tasklet_struct *t)
  1158. {
  1159. struct jme_adapter *jme = from_tasklet(jme, t, rxempty_task);
  1160. if (unlikely(atomic_read(&jme->link_changing) != 1))
  1161. return;
  1162. if (unlikely(!netif_carrier_ok(jme->dev)))
  1163. return;
  1164. netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
  1165. jme_rx_clean_tasklet(&jme->rxclean_task);
  1166. while (atomic_read(&jme->rx_empty) > 0) {
  1167. atomic_dec(&jme->rx_empty);
  1168. ++(NET_STAT(jme).rx_dropped);
  1169. jme_restart_rx_engine(jme);
  1170. }
  1171. atomic_inc(&jme->rx_empty);
  1172. }
  1173. static void
  1174. jme_wake_queue_if_stopped(struct jme_adapter *jme)
  1175. {
  1176. struct jme_ring *txring = &(jme->txring[0]);
  1177. smp_wmb();
  1178. if (unlikely(netif_queue_stopped(jme->dev) &&
  1179. atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
  1180. netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
  1181. netif_wake_queue(jme->dev);
  1182. }
  1183. }
  1184. static void jme_tx_clean_tasklet(struct tasklet_struct *t)
  1185. {
  1186. struct jme_adapter *jme = from_tasklet(jme, t, txclean_task);
  1187. struct jme_ring *txring = &(jme->txring[0]);
  1188. struct txdesc *txdesc = txring->desc;
  1189. struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
  1190. int i, j, cnt = 0, max, err, mask;
  1191. tx_dbg(jme, "Into txclean\n");
  1192. if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
  1193. goto out;
  1194. if (unlikely(atomic_read(&jme->link_changing) != 1))
  1195. goto out;
  1196. if (unlikely(!netif_carrier_ok(jme->dev)))
  1197. goto out;
  1198. max = jme->tx_ring_size - atomic_read(&txring->nr_free);
  1199. mask = jme->tx_ring_mask;
  1200. for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
  1201. ctxbi = txbi + i;
  1202. if (likely(ctxbi->skb &&
  1203. !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
  1204. tx_dbg(jme, "txclean: %d+%d@%lu\n",
  1205. i, ctxbi->nr_desc, jiffies);
  1206. err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
  1207. for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
  1208. ttxbi = txbi + ((i + j) & (mask));
  1209. txdesc[(i + j) & (mask)].dw[0] = 0;
  1210. dma_unmap_page(&jme->pdev->dev,
  1211. ttxbi->mapping, ttxbi->len,
  1212. DMA_TO_DEVICE);
  1213. ttxbi->mapping = 0;
  1214. ttxbi->len = 0;
  1215. }
  1216. dev_kfree_skb(ctxbi->skb);
  1217. cnt += ctxbi->nr_desc;
  1218. if (unlikely(err)) {
  1219. ++(NET_STAT(jme).tx_carrier_errors);
  1220. } else {
  1221. ++(NET_STAT(jme).tx_packets);
  1222. NET_STAT(jme).tx_bytes += ctxbi->len;
  1223. }
  1224. ctxbi->skb = NULL;
  1225. ctxbi->len = 0;
  1226. ctxbi->start_xmit = 0;
  1227. } else {
  1228. break;
  1229. }
  1230. i = (i + ctxbi->nr_desc) & mask;
  1231. ctxbi->nr_desc = 0;
  1232. }
  1233. tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
  1234. atomic_set(&txring->next_to_clean, i);
  1235. atomic_add(cnt, &txring->nr_free);
  1236. jme_wake_queue_if_stopped(jme);
  1237. out:
  1238. atomic_inc(&jme->tx_cleaning);
  1239. }
  1240. static void
  1241. jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
  1242. {
  1243. /*
  1244. * Disable interrupt
  1245. */
  1246. jwrite32f(jme, JME_IENC, INTR_ENABLE);
  1247. if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
  1248. /*
  1249. * Link change event is critical
  1250. * all other events are ignored
  1251. */
  1252. jwrite32(jme, JME_IEVE, intrstat);
  1253. schedule_work(&jme->linkch_task);
  1254. goto out_reenable;
  1255. }
  1256. if (intrstat & INTR_TMINTR) {
  1257. jwrite32(jme, JME_IEVE, INTR_TMINTR);
  1258. tasklet_schedule(&jme->pcc_task);
  1259. }
  1260. if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
  1261. jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
  1262. tasklet_schedule(&jme->txclean_task);
  1263. }
  1264. if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
  1265. jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
  1266. INTR_PCCRX0 |
  1267. INTR_RX0EMP)) |
  1268. INTR_RX0);
  1269. }
  1270. if (test_bit(JME_FLAG_POLL, &jme->flags)) {
  1271. if (intrstat & INTR_RX0EMP)
  1272. atomic_inc(&jme->rx_empty);
  1273. if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
  1274. if (likely(JME_RX_SCHEDULE_PREP(jme))) {
  1275. jme_polling_mode(jme);
  1276. JME_RX_SCHEDULE(jme);
  1277. }
  1278. }
  1279. } else {
  1280. if (intrstat & INTR_RX0EMP) {
  1281. atomic_inc(&jme->rx_empty);
  1282. tasklet_hi_schedule(&jme->rxempty_task);
  1283. } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
  1284. tasklet_hi_schedule(&jme->rxclean_task);
  1285. }
  1286. }
  1287. out_reenable:
  1288. /*
  1289. * Re-enable interrupt
  1290. */
  1291. jwrite32f(jme, JME_IENS, INTR_ENABLE);
  1292. }
  1293. static irqreturn_t
  1294. jme_intr(int irq, void *dev_id)
  1295. {
  1296. struct net_device *netdev = dev_id;
  1297. struct jme_adapter *jme = netdev_priv(netdev);
  1298. u32 intrstat;
  1299. intrstat = jread32(jme, JME_IEVE);
  1300. /*
  1301. * Check if it's really an interrupt for us
  1302. */
  1303. if (unlikely((intrstat & INTR_ENABLE) == 0))
  1304. return IRQ_NONE;
  1305. /*
  1306. * Check if the device still exist
  1307. */
  1308. if (unlikely(intrstat == ~((typeof(intrstat))0)))
  1309. return IRQ_NONE;
  1310. jme_intr_msi(jme, intrstat);
  1311. return IRQ_HANDLED;
  1312. }
  1313. static irqreturn_t
  1314. jme_msi(int irq, void *dev_id)
  1315. {
  1316. struct net_device *netdev = dev_id;
  1317. struct jme_adapter *jme = netdev_priv(netdev);
  1318. u32 intrstat;
  1319. intrstat = jread32(jme, JME_IEVE);
  1320. jme_intr_msi(jme, intrstat);
  1321. return IRQ_HANDLED;
  1322. }
  1323. static void
  1324. jme_reset_link(struct jme_adapter *jme)
  1325. {
  1326. jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
  1327. }
  1328. static void
  1329. jme_restart_an(struct jme_adapter *jme)
  1330. {
  1331. u32 bmcr;
  1332. spin_lock_bh(&jme->phy_lock);
  1333. bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
  1334. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  1335. jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
  1336. spin_unlock_bh(&jme->phy_lock);
  1337. }
  1338. static int
  1339. jme_request_irq(struct jme_adapter *jme)
  1340. {
  1341. int rc;
  1342. struct net_device *netdev = jme->dev;
  1343. irq_handler_t handler = jme_intr;
  1344. int irq_flags = IRQF_SHARED;
  1345. if (!pci_enable_msi(jme->pdev)) {
  1346. set_bit(JME_FLAG_MSI, &jme->flags);
  1347. handler = jme_msi;
  1348. irq_flags = 0;
  1349. }
  1350. rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
  1351. netdev);
  1352. if (rc) {
  1353. netdev_err(netdev,
  1354. "Unable to request %s interrupt (return: %d)\n",
  1355. test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
  1356. rc);
  1357. if (test_bit(JME_FLAG_MSI, &jme->flags)) {
  1358. pci_disable_msi(jme->pdev);
  1359. clear_bit(JME_FLAG_MSI, &jme->flags);
  1360. }
  1361. } else {
  1362. netdev->irq = jme->pdev->irq;
  1363. }
  1364. return rc;
  1365. }
  1366. static void
  1367. jme_free_irq(struct jme_adapter *jme)
  1368. {
  1369. free_irq(jme->pdev->irq, jme->dev);
  1370. if (test_bit(JME_FLAG_MSI, &jme->flags)) {
  1371. pci_disable_msi(jme->pdev);
  1372. clear_bit(JME_FLAG_MSI, &jme->flags);
  1373. jme->dev->irq = jme->pdev->irq;
  1374. }
  1375. }
  1376. static inline void
  1377. jme_new_phy_on(struct jme_adapter *jme)
  1378. {
  1379. u32 reg;
  1380. reg = jread32(jme, JME_PHY_PWR);
  1381. reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
  1382. PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
  1383. jwrite32(jme, JME_PHY_PWR, reg);
  1384. pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
  1385. reg &= ~PE1_GPREG0_PBG;
  1386. reg |= PE1_GPREG0_ENBG;
  1387. pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
  1388. }
  1389. static inline void
  1390. jme_new_phy_off(struct jme_adapter *jme)
  1391. {
  1392. u32 reg;
  1393. reg = jread32(jme, JME_PHY_PWR);
  1394. reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
  1395. PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
  1396. jwrite32(jme, JME_PHY_PWR, reg);
  1397. pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
  1398. reg &= ~PE1_GPREG0_PBG;
  1399. reg |= PE1_GPREG0_PDD3COLD;
  1400. pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
  1401. }
  1402. static inline void
  1403. jme_phy_on(struct jme_adapter *jme)
  1404. {
  1405. u32 bmcr;
  1406. bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
  1407. bmcr &= ~BMCR_PDOWN;
  1408. jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
  1409. if (new_phy_power_ctrl(jme->chip_main_rev))
  1410. jme_new_phy_on(jme);
  1411. }
  1412. static inline void
  1413. jme_phy_off(struct jme_adapter *jme)
  1414. {
  1415. u32 bmcr;
  1416. bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
  1417. bmcr |= BMCR_PDOWN;
  1418. jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
  1419. if (new_phy_power_ctrl(jme->chip_main_rev))
  1420. jme_new_phy_off(jme);
  1421. }
  1422. static int
  1423. jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
  1424. {
  1425. u32 phy_addr;
  1426. phy_addr = JM_PHY_SPEC_REG_READ | specreg;
  1427. jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
  1428. phy_addr);
  1429. return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
  1430. JM_PHY_SPEC_DATA_REG);
  1431. }
  1432. static void
  1433. jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
  1434. {
  1435. u32 phy_addr;
  1436. phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
  1437. jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
  1438. phy_data);
  1439. jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
  1440. phy_addr);
  1441. }
  1442. static int
  1443. jme_phy_calibration(struct jme_adapter *jme)
  1444. {
  1445. u32 ctrl1000, phy_data;
  1446. jme_phy_off(jme);
  1447. jme_phy_on(jme);
  1448. /* Enabel PHY test mode 1 */
  1449. ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
  1450. ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
  1451. ctrl1000 |= PHY_GAD_TEST_MODE_1;
  1452. jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
  1453. phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
  1454. phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
  1455. phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
  1456. JM_PHY_EXT_COMM_2_CALI_ENABLE;
  1457. jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
  1458. msleep(20);
  1459. phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
  1460. phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
  1461. JM_PHY_EXT_COMM_2_CALI_MODE_0 |
  1462. JM_PHY_EXT_COMM_2_CALI_LATCH);
  1463. jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
  1464. /* Disable PHY test mode */
  1465. ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
  1466. ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
  1467. jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
  1468. return 0;
  1469. }
  1470. static int
  1471. jme_phy_setEA(struct jme_adapter *jme)
  1472. {
  1473. u32 phy_comm0 = 0, phy_comm1 = 0;
  1474. u8 nic_ctrl;
  1475. pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
  1476. if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
  1477. return 0;
  1478. switch (jme->pdev->device) {
  1479. case PCI_DEVICE_ID_JMICRON_JMC250:
  1480. if (((jme->chip_main_rev == 5) &&
  1481. ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
  1482. (jme->chip_sub_rev == 3))) ||
  1483. (jme->chip_main_rev >= 6)) {
  1484. phy_comm0 = 0x008A;
  1485. phy_comm1 = 0x4109;
  1486. }
  1487. if ((jme->chip_main_rev == 3) &&
  1488. ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
  1489. phy_comm0 = 0xE088;
  1490. break;
  1491. case PCI_DEVICE_ID_JMICRON_JMC260:
  1492. if (((jme->chip_main_rev == 5) &&
  1493. ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
  1494. (jme->chip_sub_rev == 3))) ||
  1495. (jme->chip_main_rev >= 6)) {
  1496. phy_comm0 = 0x008A;
  1497. phy_comm1 = 0x4109;
  1498. }
  1499. if ((jme->chip_main_rev == 3) &&
  1500. ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
  1501. phy_comm0 = 0xE088;
  1502. if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
  1503. phy_comm0 = 0x608A;
  1504. if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
  1505. phy_comm0 = 0x408A;
  1506. break;
  1507. default:
  1508. return -ENODEV;
  1509. }
  1510. if (phy_comm0)
  1511. jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
  1512. if (phy_comm1)
  1513. jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
  1514. return 0;
  1515. }
  1516. static int
  1517. jme_open(struct net_device *netdev)
  1518. {
  1519. struct jme_adapter *jme = netdev_priv(netdev);
  1520. int rc;
  1521. jme_clear_pm_disable_wol(jme);
  1522. JME_NAPI_ENABLE(jme);
  1523. tasklet_setup(&jme->txclean_task, jme_tx_clean_tasklet);
  1524. tasklet_setup(&jme->rxclean_task, jme_rx_clean_tasklet);
  1525. tasklet_setup(&jme->rxempty_task, jme_rx_empty_tasklet);
  1526. rc = jme_request_irq(jme);
  1527. if (rc)
  1528. goto err_out;
  1529. jme_start_irq(jme);
  1530. jme_phy_on(jme);
  1531. if (test_bit(JME_FLAG_SSET, &jme->flags))
  1532. jme_set_link_ksettings(netdev, &jme->old_cmd);
  1533. else
  1534. jme_reset_phy_processor(jme);
  1535. jme_phy_calibration(jme);
  1536. jme_phy_setEA(jme);
  1537. jme_reset_link(jme);
  1538. return 0;
  1539. err_out:
  1540. netif_stop_queue(netdev);
  1541. netif_carrier_off(netdev);
  1542. return rc;
  1543. }
  1544. static void
  1545. jme_set_100m_half(struct jme_adapter *jme)
  1546. {
  1547. u32 bmcr, tmp;
  1548. jme_phy_on(jme);
  1549. bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
  1550. tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
  1551. BMCR_SPEED1000 | BMCR_FULLDPLX);
  1552. tmp |= BMCR_SPEED100;
  1553. if (bmcr != tmp)
  1554. jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
  1555. if (jme->fpgaver)
  1556. jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
  1557. else
  1558. jwrite32(jme, JME_GHC, GHC_SPEED_100M);
  1559. }
  1560. #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
  1561. static void
  1562. jme_wait_link(struct jme_adapter *jme)
  1563. {
  1564. u32 phylink, to = JME_WAIT_LINK_TIME;
  1565. msleep(1000);
  1566. phylink = jme_linkstat_from_phy(jme);
  1567. while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
  1568. usleep_range(10000, 11000);
  1569. phylink = jme_linkstat_from_phy(jme);
  1570. }
  1571. }
  1572. static void
  1573. jme_powersave_phy(struct jme_adapter *jme)
  1574. {
  1575. if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
  1576. jme_set_100m_half(jme);
  1577. if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
  1578. jme_wait_link(jme);
  1579. jme_clear_pm_enable_wol(jme);
  1580. } else {
  1581. jme_phy_off(jme);
  1582. }
  1583. }
  1584. static int
  1585. jme_close(struct net_device *netdev)
  1586. {
  1587. struct jme_adapter *jme = netdev_priv(netdev);
  1588. netif_stop_queue(netdev);
  1589. netif_carrier_off(netdev);
  1590. jme_stop_irq(jme);
  1591. jme_free_irq(jme);
  1592. JME_NAPI_DISABLE(jme);
  1593. cancel_work_sync(&jme->linkch_task);
  1594. tasklet_kill(&jme->txclean_task);
  1595. tasklet_kill(&jme->rxclean_task);
  1596. tasklet_kill(&jme->rxempty_task);
  1597. jme_disable_rx_engine(jme);
  1598. jme_disable_tx_engine(jme);
  1599. jme_reset_mac_processor(jme);
  1600. jme_free_rx_resources(jme);
  1601. jme_free_tx_resources(jme);
  1602. jme->phylink = 0;
  1603. jme_phy_off(jme);
  1604. return 0;
  1605. }
  1606. static int
  1607. jme_alloc_txdesc(struct jme_adapter *jme,
  1608. struct sk_buff *skb)
  1609. {
  1610. struct jme_ring *txring = &(jme->txring[0]);
  1611. int idx, nr_alloc, mask = jme->tx_ring_mask;
  1612. idx = txring->next_to_use;
  1613. nr_alloc = skb_shinfo(skb)->nr_frags + 2;
  1614. if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
  1615. return -1;
  1616. atomic_sub(nr_alloc, &txring->nr_free);
  1617. txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
  1618. return idx;
  1619. }
  1620. static int
  1621. jme_fill_tx_map(struct pci_dev *pdev,
  1622. struct txdesc *txdesc,
  1623. struct jme_buffer_info *txbi,
  1624. struct page *page,
  1625. u32 page_offset,
  1626. u32 len,
  1627. bool hidma)
  1628. {
  1629. dma_addr_t dmaaddr;
  1630. dmaaddr = dma_map_page(&pdev->dev, page, page_offset, len,
  1631. DMA_TO_DEVICE);
  1632. if (unlikely(dma_mapping_error(&pdev->dev, dmaaddr)))
  1633. return -EINVAL;
  1634. dma_sync_single_for_device(&pdev->dev, dmaaddr, len, DMA_TO_DEVICE);
  1635. txdesc->dw[0] = 0;
  1636. txdesc->dw[1] = 0;
  1637. txdesc->desc2.flags = TXFLAG_OWN;
  1638. txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
  1639. txdesc->desc2.datalen = cpu_to_le16(len);
  1640. txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
  1641. txdesc->desc2.bufaddrl = cpu_to_le32(
  1642. (__u64)dmaaddr & 0xFFFFFFFFUL);
  1643. txbi->mapping = dmaaddr;
  1644. txbi->len = len;
  1645. return 0;
  1646. }
  1647. static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count)
  1648. {
  1649. struct jme_ring *txring = &(jme->txring[0]);
  1650. struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
  1651. int mask = jme->tx_ring_mask;
  1652. int j;
  1653. for (j = 0 ; j < count ; j++) {
  1654. ctxbi = txbi + ((startidx + j + 2) & (mask));
  1655. dma_unmap_page(&jme->pdev->dev, ctxbi->mapping, ctxbi->len,
  1656. DMA_TO_DEVICE);
  1657. ctxbi->mapping = 0;
  1658. ctxbi->len = 0;
  1659. }
  1660. }
  1661. static int
  1662. jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
  1663. {
  1664. struct jme_ring *txring = &(jme->txring[0]);
  1665. struct txdesc *txdesc = txring->desc, *ctxdesc;
  1666. struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
  1667. bool hidma = jme->dev->features & NETIF_F_HIGHDMA;
  1668. int i, nr_frags = skb_shinfo(skb)->nr_frags;
  1669. int mask = jme->tx_ring_mask;
  1670. u32 len;
  1671. int ret = 0;
  1672. for (i = 0 ; i < nr_frags ; ++i) {
  1673. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1674. ctxdesc = txdesc + ((idx + i + 2) & (mask));
  1675. ctxbi = txbi + ((idx + i + 2) & (mask));
  1676. ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
  1677. skb_frag_page(frag), skb_frag_off(frag),
  1678. skb_frag_size(frag), hidma);
  1679. if (ret) {
  1680. jme_drop_tx_map(jme, idx, i);
  1681. goto out;
  1682. }
  1683. }
  1684. len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
  1685. ctxdesc = txdesc + ((idx + 1) & (mask));
  1686. ctxbi = txbi + ((idx + 1) & (mask));
  1687. ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
  1688. offset_in_page(skb->data), len, hidma);
  1689. if (ret)
  1690. jme_drop_tx_map(jme, idx, i);
  1691. out:
  1692. return ret;
  1693. }
  1694. static int
  1695. jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
  1696. {
  1697. *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
  1698. if (*mss) {
  1699. *flags |= TXFLAG_LSEN;
  1700. if (skb->protocol == htons(ETH_P_IP)) {
  1701. struct iphdr *iph = ip_hdr(skb);
  1702. iph->check = 0;
  1703. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  1704. iph->daddr, 0,
  1705. IPPROTO_TCP,
  1706. 0);
  1707. } else {
  1708. tcp_v6_gso_csum_prep(skb);
  1709. }
  1710. return 0;
  1711. }
  1712. return 1;
  1713. }
  1714. static void
  1715. jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
  1716. {
  1717. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1718. u8 ip_proto;
  1719. switch (skb->protocol) {
  1720. case htons(ETH_P_IP):
  1721. ip_proto = ip_hdr(skb)->protocol;
  1722. break;
  1723. case htons(ETH_P_IPV6):
  1724. ip_proto = ipv6_hdr(skb)->nexthdr;
  1725. break;
  1726. default:
  1727. ip_proto = 0;
  1728. break;
  1729. }
  1730. switch (ip_proto) {
  1731. case IPPROTO_TCP:
  1732. *flags |= TXFLAG_TCPCS;
  1733. break;
  1734. case IPPROTO_UDP:
  1735. *flags |= TXFLAG_UDPCS;
  1736. break;
  1737. default:
  1738. netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
  1739. break;
  1740. }
  1741. }
  1742. }
  1743. static inline void
  1744. jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
  1745. {
  1746. if (skb_vlan_tag_present(skb)) {
  1747. *flags |= TXFLAG_TAGON;
  1748. *vlan = cpu_to_le16(skb_vlan_tag_get(skb));
  1749. }
  1750. }
  1751. static int
  1752. jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
  1753. {
  1754. struct jme_ring *txring = &(jme->txring[0]);
  1755. struct txdesc *txdesc;
  1756. struct jme_buffer_info *txbi;
  1757. u8 flags;
  1758. int ret = 0;
  1759. txdesc = (struct txdesc *)txring->desc + idx;
  1760. txbi = txring->bufinf + idx;
  1761. txdesc->dw[0] = 0;
  1762. txdesc->dw[1] = 0;
  1763. txdesc->dw[2] = 0;
  1764. txdesc->dw[3] = 0;
  1765. txdesc->desc1.pktsize = cpu_to_le16(skb->len);
  1766. /*
  1767. * Set OWN bit at final.
  1768. * When kernel transmit faster than NIC.
  1769. * And NIC trying to send this descriptor before we tell
  1770. * it to start sending this TX queue.
  1771. * Other fields are already filled correctly.
  1772. */
  1773. wmb();
  1774. flags = TXFLAG_OWN | TXFLAG_INT;
  1775. /*
  1776. * Set checksum flags while not tso
  1777. */
  1778. if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
  1779. jme_tx_csum(jme, skb, &flags);
  1780. jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
  1781. ret = jme_map_tx_skb(jme, skb, idx);
  1782. if (ret)
  1783. return ret;
  1784. txdesc->desc1.flags = flags;
  1785. /*
  1786. * Set tx buffer info after telling NIC to send
  1787. * For better tx_clean timing
  1788. */
  1789. wmb();
  1790. txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
  1791. txbi->skb = skb;
  1792. txbi->len = skb->len;
  1793. txbi->start_xmit = jiffies;
  1794. if (!txbi->start_xmit)
  1795. txbi->start_xmit = (0UL-1);
  1796. return 0;
  1797. }
  1798. static void
  1799. jme_stop_queue_if_full(struct jme_adapter *jme)
  1800. {
  1801. struct jme_ring *txring = &(jme->txring[0]);
  1802. struct jme_buffer_info *txbi = txring->bufinf;
  1803. int idx = atomic_read(&txring->next_to_clean);
  1804. txbi += idx;
  1805. smp_wmb();
  1806. if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
  1807. netif_stop_queue(jme->dev);
  1808. netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
  1809. smp_wmb();
  1810. if (atomic_read(&txring->nr_free)
  1811. >= (jme->tx_wake_threshold)) {
  1812. netif_wake_queue(jme->dev);
  1813. netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
  1814. }
  1815. }
  1816. if (unlikely(txbi->start_xmit &&
  1817. time_is_before_eq_jiffies(txbi->start_xmit + TX_TIMEOUT) &&
  1818. txbi->skb)) {
  1819. netif_stop_queue(jme->dev);
  1820. netif_info(jme, tx_queued, jme->dev,
  1821. "TX Queue Stopped %d@%lu\n", idx, jiffies);
  1822. }
  1823. }
  1824. /*
  1825. * This function is already protected by netif_tx_lock()
  1826. */
  1827. static netdev_tx_t
  1828. jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  1829. {
  1830. struct jme_adapter *jme = netdev_priv(netdev);
  1831. int idx;
  1832. if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) {
  1833. dev_kfree_skb_any(skb);
  1834. ++(NET_STAT(jme).tx_dropped);
  1835. return NETDEV_TX_OK;
  1836. }
  1837. idx = jme_alloc_txdesc(jme, skb);
  1838. if (unlikely(idx < 0)) {
  1839. netif_stop_queue(netdev);
  1840. netif_err(jme, tx_err, jme->dev,
  1841. "BUG! Tx ring full when queue awake!\n");
  1842. return NETDEV_TX_BUSY;
  1843. }
  1844. if (jme_fill_tx_desc(jme, skb, idx))
  1845. return NETDEV_TX_OK;
  1846. jwrite32(jme, JME_TXCS, jme->reg_txcs |
  1847. TXCS_SELECT_QUEUE0 |
  1848. TXCS_QUEUE0S |
  1849. TXCS_ENABLE);
  1850. tx_dbg(jme, "xmit: %d+%d@%lu\n",
  1851. idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
  1852. jme_stop_queue_if_full(jme);
  1853. return NETDEV_TX_OK;
  1854. }
  1855. static void
  1856. jme_set_unicastaddr(struct net_device *netdev)
  1857. {
  1858. struct jme_adapter *jme = netdev_priv(netdev);
  1859. u32 val;
  1860. val = (netdev->dev_addr[3] & 0xff) << 24 |
  1861. (netdev->dev_addr[2] & 0xff) << 16 |
  1862. (netdev->dev_addr[1] & 0xff) << 8 |
  1863. (netdev->dev_addr[0] & 0xff);
  1864. jwrite32(jme, JME_RXUMA_LO, val);
  1865. val = (netdev->dev_addr[5] & 0xff) << 8 |
  1866. (netdev->dev_addr[4] & 0xff);
  1867. jwrite32(jme, JME_RXUMA_HI, val);
  1868. }
  1869. static int
  1870. jme_set_macaddr(struct net_device *netdev, void *p)
  1871. {
  1872. struct jme_adapter *jme = netdev_priv(netdev);
  1873. struct sockaddr *addr = p;
  1874. if (netif_running(netdev))
  1875. return -EBUSY;
  1876. spin_lock_bh(&jme->macaddr_lock);
  1877. eth_hw_addr_set(netdev, addr->sa_data);
  1878. jme_set_unicastaddr(netdev);
  1879. spin_unlock_bh(&jme->macaddr_lock);
  1880. return 0;
  1881. }
  1882. static void
  1883. jme_set_multi(struct net_device *netdev)
  1884. {
  1885. struct jme_adapter *jme = netdev_priv(netdev);
  1886. u32 mc_hash[2] = {};
  1887. spin_lock_bh(&jme->rxmcs_lock);
  1888. jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
  1889. if (netdev->flags & IFF_PROMISC) {
  1890. jme->reg_rxmcs |= RXMCS_ALLFRAME;
  1891. } else if (netdev->flags & IFF_ALLMULTI) {
  1892. jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
  1893. } else if (netdev->flags & IFF_MULTICAST) {
  1894. struct netdev_hw_addr *ha;
  1895. int bit_nr;
  1896. jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
  1897. netdev_for_each_mc_addr(ha, netdev) {
  1898. bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
  1899. mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
  1900. }
  1901. jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
  1902. jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
  1903. }
  1904. wmb();
  1905. jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
  1906. spin_unlock_bh(&jme->rxmcs_lock);
  1907. }
  1908. static int
  1909. jme_change_mtu(struct net_device *netdev, int new_mtu)
  1910. {
  1911. struct jme_adapter *jme = netdev_priv(netdev);
  1912. netdev->mtu = new_mtu;
  1913. netdev_update_features(netdev);
  1914. jme_restart_rx_engine(jme);
  1915. jme_reset_link(jme);
  1916. return 0;
  1917. }
  1918. static void
  1919. jme_tx_timeout(struct net_device *netdev, unsigned int txqueue)
  1920. {
  1921. struct jme_adapter *jme = netdev_priv(netdev);
  1922. jme->phylink = 0;
  1923. jme_reset_phy_processor(jme);
  1924. if (test_bit(JME_FLAG_SSET, &jme->flags))
  1925. jme_set_link_ksettings(netdev, &jme->old_cmd);
  1926. /*
  1927. * Force to Reset the link again
  1928. */
  1929. jme_reset_link(jme);
  1930. }
  1931. static void
  1932. jme_get_drvinfo(struct net_device *netdev,
  1933. struct ethtool_drvinfo *info)
  1934. {
  1935. struct jme_adapter *jme = netdev_priv(netdev);
  1936. strscpy(info->driver, DRV_NAME, sizeof(info->driver));
  1937. strscpy(info->version, DRV_VERSION, sizeof(info->version));
  1938. strscpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info));
  1939. }
  1940. static int
  1941. jme_get_regs_len(struct net_device *netdev)
  1942. {
  1943. return JME_REG_LEN;
  1944. }
  1945. static void
  1946. mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
  1947. {
  1948. int i;
  1949. for (i = 0 ; i < len ; i += 4)
  1950. p[i >> 2] = jread32(jme, reg + i);
  1951. }
  1952. static void
  1953. mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
  1954. {
  1955. int i;
  1956. u16 *p16 = (u16 *)p;
  1957. for (i = 0 ; i < reg_nr ; ++i)
  1958. p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
  1959. }
  1960. static void
  1961. jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
  1962. {
  1963. struct jme_adapter *jme = netdev_priv(netdev);
  1964. u32 *p32 = (u32 *)p;
  1965. memset(p, 0xFF, JME_REG_LEN);
  1966. regs->version = 1;
  1967. mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
  1968. p32 += 0x100 >> 2;
  1969. mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
  1970. p32 += 0x100 >> 2;
  1971. mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
  1972. p32 += 0x100 >> 2;
  1973. mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
  1974. p32 += 0x100 >> 2;
  1975. mdio_memcpy(jme, p32, JME_PHY_REG_NR);
  1976. }
  1977. static int jme_get_coalesce(struct net_device *netdev,
  1978. struct ethtool_coalesce *ecmd,
  1979. struct kernel_ethtool_coalesce *kernel_coal,
  1980. struct netlink_ext_ack *extack)
  1981. {
  1982. struct jme_adapter *jme = netdev_priv(netdev);
  1983. ecmd->tx_coalesce_usecs = PCC_TX_TO;
  1984. ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
  1985. if (test_bit(JME_FLAG_POLL, &jme->flags)) {
  1986. ecmd->use_adaptive_rx_coalesce = false;
  1987. ecmd->rx_coalesce_usecs = 0;
  1988. ecmd->rx_max_coalesced_frames = 0;
  1989. return 0;
  1990. }
  1991. ecmd->use_adaptive_rx_coalesce = true;
  1992. switch (jme->dpi.cur) {
  1993. case PCC_P1:
  1994. ecmd->rx_coalesce_usecs = PCC_P1_TO;
  1995. ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
  1996. break;
  1997. case PCC_P2:
  1998. ecmd->rx_coalesce_usecs = PCC_P2_TO;
  1999. ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
  2000. break;
  2001. case PCC_P3:
  2002. ecmd->rx_coalesce_usecs = PCC_P3_TO;
  2003. ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
  2004. break;
  2005. default:
  2006. break;
  2007. }
  2008. return 0;
  2009. }
  2010. static int jme_set_coalesce(struct net_device *netdev,
  2011. struct ethtool_coalesce *ecmd,
  2012. struct kernel_ethtool_coalesce *kernel_coal,
  2013. struct netlink_ext_ack *extack)
  2014. {
  2015. struct jme_adapter *jme = netdev_priv(netdev);
  2016. struct dynpcc_info *dpi = &(jme->dpi);
  2017. if (netif_running(netdev))
  2018. return -EBUSY;
  2019. if (ecmd->use_adaptive_rx_coalesce &&
  2020. test_bit(JME_FLAG_POLL, &jme->flags)) {
  2021. clear_bit(JME_FLAG_POLL, &jme->flags);
  2022. jme->jme_rx = netif_rx;
  2023. dpi->cur = PCC_P1;
  2024. dpi->attempt = PCC_P1;
  2025. dpi->cnt = 0;
  2026. jme_set_rx_pcc(jme, PCC_P1);
  2027. jme_interrupt_mode(jme);
  2028. } else if (!(ecmd->use_adaptive_rx_coalesce) &&
  2029. !(test_bit(JME_FLAG_POLL, &jme->flags))) {
  2030. set_bit(JME_FLAG_POLL, &jme->flags);
  2031. jme->jme_rx = netif_receive_skb;
  2032. jme_interrupt_mode(jme);
  2033. }
  2034. return 0;
  2035. }
  2036. static void
  2037. jme_get_pauseparam(struct net_device *netdev,
  2038. struct ethtool_pauseparam *ecmd)
  2039. {
  2040. struct jme_adapter *jme = netdev_priv(netdev);
  2041. u32 val;
  2042. ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
  2043. ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
  2044. spin_lock_bh(&jme->phy_lock);
  2045. val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
  2046. spin_unlock_bh(&jme->phy_lock);
  2047. ecmd->autoneg =
  2048. (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
  2049. }
  2050. static int
  2051. jme_set_pauseparam(struct net_device *netdev,
  2052. struct ethtool_pauseparam *ecmd)
  2053. {
  2054. struct jme_adapter *jme = netdev_priv(netdev);
  2055. u32 val;
  2056. if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
  2057. (ecmd->tx_pause != 0)) {
  2058. if (ecmd->tx_pause)
  2059. jme->reg_txpfc |= TXPFC_PF_EN;
  2060. else
  2061. jme->reg_txpfc &= ~TXPFC_PF_EN;
  2062. jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
  2063. }
  2064. spin_lock_bh(&jme->rxmcs_lock);
  2065. if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
  2066. (ecmd->rx_pause != 0)) {
  2067. if (ecmd->rx_pause)
  2068. jme->reg_rxmcs |= RXMCS_FLOWCTRL;
  2069. else
  2070. jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
  2071. jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
  2072. }
  2073. spin_unlock_bh(&jme->rxmcs_lock);
  2074. spin_lock_bh(&jme->phy_lock);
  2075. val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
  2076. if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
  2077. (ecmd->autoneg != 0)) {
  2078. if (ecmd->autoneg)
  2079. val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2080. else
  2081. val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2082. jme_mdio_write(jme->dev, jme->mii_if.phy_id,
  2083. MII_ADVERTISE, val);
  2084. }
  2085. spin_unlock_bh(&jme->phy_lock);
  2086. return 0;
  2087. }
  2088. static void
  2089. jme_get_wol(struct net_device *netdev,
  2090. struct ethtool_wolinfo *wol)
  2091. {
  2092. struct jme_adapter *jme = netdev_priv(netdev);
  2093. wol->supported = WAKE_MAGIC | WAKE_PHY;
  2094. wol->wolopts = 0;
  2095. if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
  2096. wol->wolopts |= WAKE_PHY;
  2097. if (jme->reg_pmcs & PMCS_MFEN)
  2098. wol->wolopts |= WAKE_MAGIC;
  2099. }
  2100. static int
  2101. jme_set_wol(struct net_device *netdev,
  2102. struct ethtool_wolinfo *wol)
  2103. {
  2104. struct jme_adapter *jme = netdev_priv(netdev);
  2105. if (wol->wolopts & (WAKE_MAGICSECURE |
  2106. WAKE_UCAST |
  2107. WAKE_MCAST |
  2108. WAKE_BCAST |
  2109. WAKE_ARP))
  2110. return -EOPNOTSUPP;
  2111. jme->reg_pmcs = 0;
  2112. if (wol->wolopts & WAKE_PHY)
  2113. jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
  2114. if (wol->wolopts & WAKE_MAGIC)
  2115. jme->reg_pmcs |= PMCS_MFEN;
  2116. return 0;
  2117. }
  2118. static int
  2119. jme_get_link_ksettings(struct net_device *netdev,
  2120. struct ethtool_link_ksettings *cmd)
  2121. {
  2122. struct jme_adapter *jme = netdev_priv(netdev);
  2123. spin_lock_bh(&jme->phy_lock);
  2124. mii_ethtool_get_link_ksettings(&jme->mii_if, cmd);
  2125. spin_unlock_bh(&jme->phy_lock);
  2126. return 0;
  2127. }
  2128. static int
  2129. jme_set_link_ksettings(struct net_device *netdev,
  2130. const struct ethtool_link_ksettings *cmd)
  2131. {
  2132. struct jme_adapter *jme = netdev_priv(netdev);
  2133. int rc, fdc = 0;
  2134. if (cmd->base.speed == SPEED_1000 &&
  2135. cmd->base.autoneg != AUTONEG_ENABLE)
  2136. return -EINVAL;
  2137. /*
  2138. * Check If user changed duplex only while force_media.
  2139. * Hardware would not generate link change interrupt.
  2140. */
  2141. if (jme->mii_if.force_media &&
  2142. cmd->base.autoneg != AUTONEG_ENABLE &&
  2143. (jme->mii_if.full_duplex != cmd->base.duplex))
  2144. fdc = 1;
  2145. spin_lock_bh(&jme->phy_lock);
  2146. rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd);
  2147. spin_unlock_bh(&jme->phy_lock);
  2148. if (!rc) {
  2149. if (fdc)
  2150. jme_reset_link(jme);
  2151. jme->old_cmd = *cmd;
  2152. set_bit(JME_FLAG_SSET, &jme->flags);
  2153. }
  2154. return rc;
  2155. }
  2156. static int
  2157. jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  2158. {
  2159. int rc;
  2160. struct jme_adapter *jme = netdev_priv(netdev);
  2161. struct mii_ioctl_data *mii_data = if_mii(rq);
  2162. unsigned int duplex_chg;
  2163. if (cmd == SIOCSMIIREG) {
  2164. u16 val = mii_data->val_in;
  2165. if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
  2166. (val & BMCR_SPEED1000))
  2167. return -EINVAL;
  2168. }
  2169. spin_lock_bh(&jme->phy_lock);
  2170. rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
  2171. spin_unlock_bh(&jme->phy_lock);
  2172. if (!rc && (cmd == SIOCSMIIREG)) {
  2173. if (duplex_chg)
  2174. jme_reset_link(jme);
  2175. jme_get_link_ksettings(netdev, &jme->old_cmd);
  2176. set_bit(JME_FLAG_SSET, &jme->flags);
  2177. }
  2178. return rc;
  2179. }
  2180. static u32
  2181. jme_get_link(struct net_device *netdev)
  2182. {
  2183. struct jme_adapter *jme = netdev_priv(netdev);
  2184. return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
  2185. }
  2186. static u32
  2187. jme_get_msglevel(struct net_device *netdev)
  2188. {
  2189. struct jme_adapter *jme = netdev_priv(netdev);
  2190. return jme->msg_enable;
  2191. }
  2192. static void
  2193. jme_set_msglevel(struct net_device *netdev, u32 value)
  2194. {
  2195. struct jme_adapter *jme = netdev_priv(netdev);
  2196. jme->msg_enable = value;
  2197. }
  2198. static netdev_features_t
  2199. jme_fix_features(struct net_device *netdev, netdev_features_t features)
  2200. {
  2201. if (netdev->mtu > 1900)
  2202. features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK);
  2203. return features;
  2204. }
  2205. static int
  2206. jme_set_features(struct net_device *netdev, netdev_features_t features)
  2207. {
  2208. struct jme_adapter *jme = netdev_priv(netdev);
  2209. spin_lock_bh(&jme->rxmcs_lock);
  2210. if (features & NETIF_F_RXCSUM)
  2211. jme->reg_rxmcs |= RXMCS_CHECKSUM;
  2212. else
  2213. jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
  2214. jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
  2215. spin_unlock_bh(&jme->rxmcs_lock);
  2216. return 0;
  2217. }
  2218. #ifdef CONFIG_NET_POLL_CONTROLLER
  2219. static void jme_netpoll(struct net_device *dev)
  2220. {
  2221. unsigned long flags;
  2222. local_irq_save(flags);
  2223. jme_intr(dev->irq, dev);
  2224. local_irq_restore(flags);
  2225. }
  2226. #endif
  2227. static int
  2228. jme_nway_reset(struct net_device *netdev)
  2229. {
  2230. struct jme_adapter *jme = netdev_priv(netdev);
  2231. jme_restart_an(jme);
  2232. return 0;
  2233. }
  2234. static u8
  2235. jme_smb_read(struct jme_adapter *jme, unsigned int addr)
  2236. {
  2237. u32 val;
  2238. int to;
  2239. val = jread32(jme, JME_SMBCSR);
  2240. to = JME_SMB_BUSY_TIMEOUT;
  2241. while ((val & SMBCSR_BUSY) && --to) {
  2242. msleep(1);
  2243. val = jread32(jme, JME_SMBCSR);
  2244. }
  2245. if (!to) {
  2246. netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
  2247. return 0xFF;
  2248. }
  2249. jwrite32(jme, JME_SMBINTF,
  2250. ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
  2251. SMBINTF_HWRWN_READ |
  2252. SMBINTF_HWCMD);
  2253. val = jread32(jme, JME_SMBINTF);
  2254. to = JME_SMB_BUSY_TIMEOUT;
  2255. while ((val & SMBINTF_HWCMD) && --to) {
  2256. msleep(1);
  2257. val = jread32(jme, JME_SMBINTF);
  2258. }
  2259. if (!to) {
  2260. netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
  2261. return 0xFF;
  2262. }
  2263. return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
  2264. }
  2265. static void
  2266. jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
  2267. {
  2268. u32 val;
  2269. int to;
  2270. val = jread32(jme, JME_SMBCSR);
  2271. to = JME_SMB_BUSY_TIMEOUT;
  2272. while ((val & SMBCSR_BUSY) && --to) {
  2273. msleep(1);
  2274. val = jread32(jme, JME_SMBCSR);
  2275. }
  2276. if (!to) {
  2277. netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
  2278. return;
  2279. }
  2280. jwrite32(jme, JME_SMBINTF,
  2281. ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
  2282. ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
  2283. SMBINTF_HWRWN_WRITE |
  2284. SMBINTF_HWCMD);
  2285. val = jread32(jme, JME_SMBINTF);
  2286. to = JME_SMB_BUSY_TIMEOUT;
  2287. while ((val & SMBINTF_HWCMD) && --to) {
  2288. msleep(1);
  2289. val = jread32(jme, JME_SMBINTF);
  2290. }
  2291. if (!to) {
  2292. netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
  2293. return;
  2294. }
  2295. mdelay(2);
  2296. }
  2297. static int
  2298. jme_get_eeprom_len(struct net_device *netdev)
  2299. {
  2300. struct jme_adapter *jme = netdev_priv(netdev);
  2301. u32 val;
  2302. val = jread32(jme, JME_SMBCSR);
  2303. return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
  2304. }
  2305. static int
  2306. jme_get_eeprom(struct net_device *netdev,
  2307. struct ethtool_eeprom *eeprom, u8 *data)
  2308. {
  2309. struct jme_adapter *jme = netdev_priv(netdev);
  2310. int i, offset = eeprom->offset, len = eeprom->len;
  2311. /*
  2312. * ethtool will check the boundary for us
  2313. */
  2314. eeprom->magic = JME_EEPROM_MAGIC;
  2315. for (i = 0 ; i < len ; ++i)
  2316. data[i] = jme_smb_read(jme, i + offset);
  2317. return 0;
  2318. }
  2319. static int
  2320. jme_set_eeprom(struct net_device *netdev,
  2321. struct ethtool_eeprom *eeprom, u8 *data)
  2322. {
  2323. struct jme_adapter *jme = netdev_priv(netdev);
  2324. int i, offset = eeprom->offset, len = eeprom->len;
  2325. if (eeprom->magic != JME_EEPROM_MAGIC)
  2326. return -EINVAL;
  2327. /*
  2328. * ethtool will check the boundary for us
  2329. */
  2330. for (i = 0 ; i < len ; ++i)
  2331. jme_smb_write(jme, i + offset, data[i]);
  2332. return 0;
  2333. }
  2334. static const struct ethtool_ops jme_ethtool_ops = {
  2335. .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
  2336. ETHTOOL_COALESCE_MAX_FRAMES |
  2337. ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
  2338. .get_drvinfo = jme_get_drvinfo,
  2339. .get_regs_len = jme_get_regs_len,
  2340. .get_regs = jme_get_regs,
  2341. .get_coalesce = jme_get_coalesce,
  2342. .set_coalesce = jme_set_coalesce,
  2343. .get_pauseparam = jme_get_pauseparam,
  2344. .set_pauseparam = jme_set_pauseparam,
  2345. .get_wol = jme_get_wol,
  2346. .set_wol = jme_set_wol,
  2347. .get_link = jme_get_link,
  2348. .get_msglevel = jme_get_msglevel,
  2349. .set_msglevel = jme_set_msglevel,
  2350. .nway_reset = jme_nway_reset,
  2351. .get_eeprom_len = jme_get_eeprom_len,
  2352. .get_eeprom = jme_get_eeprom,
  2353. .set_eeprom = jme_set_eeprom,
  2354. .get_link_ksettings = jme_get_link_ksettings,
  2355. .set_link_ksettings = jme_set_link_ksettings,
  2356. };
  2357. static int
  2358. jme_pci_dma64(struct pci_dev *pdev)
  2359. {
  2360. if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
  2361. !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
  2362. return 1;
  2363. if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
  2364. !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)))
  2365. return 1;
  2366. if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
  2367. return 0;
  2368. return -1;
  2369. }
  2370. static inline void
  2371. jme_phy_init(struct jme_adapter *jme)
  2372. {
  2373. u16 reg26;
  2374. reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
  2375. jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
  2376. }
  2377. static inline void
  2378. jme_check_hw_ver(struct jme_adapter *jme)
  2379. {
  2380. u32 chipmode;
  2381. chipmode = jread32(jme, JME_CHIPMODE);
  2382. jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
  2383. jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
  2384. jme->chip_main_rev = jme->chiprev & 0xF;
  2385. jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
  2386. }
  2387. static const struct net_device_ops jme_netdev_ops = {
  2388. .ndo_open = jme_open,
  2389. .ndo_stop = jme_close,
  2390. .ndo_validate_addr = eth_validate_addr,
  2391. .ndo_eth_ioctl = jme_ioctl,
  2392. .ndo_start_xmit = jme_start_xmit,
  2393. .ndo_set_mac_address = jme_set_macaddr,
  2394. .ndo_set_rx_mode = jme_set_multi,
  2395. .ndo_change_mtu = jme_change_mtu,
  2396. .ndo_tx_timeout = jme_tx_timeout,
  2397. .ndo_fix_features = jme_fix_features,
  2398. .ndo_set_features = jme_set_features,
  2399. #ifdef CONFIG_NET_POLL_CONTROLLER
  2400. .ndo_poll_controller = jme_netpoll,
  2401. #endif
  2402. };
  2403. static int
  2404. jme_init_one(struct pci_dev *pdev,
  2405. const struct pci_device_id *ent)
  2406. {
  2407. int rc = 0, using_dac, i;
  2408. struct net_device *netdev;
  2409. struct jme_adapter *jme;
  2410. u16 bmcr, bmsr;
  2411. u32 apmc;
  2412. /*
  2413. * set up PCI device basics
  2414. */
  2415. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  2416. PCIE_LINK_STATE_CLKPM);
  2417. rc = pci_enable_device(pdev);
  2418. if (rc) {
  2419. pr_err("Cannot enable PCI device\n");
  2420. goto err_out;
  2421. }
  2422. using_dac = jme_pci_dma64(pdev);
  2423. if (using_dac < 0) {
  2424. pr_err("Cannot set PCI DMA Mask\n");
  2425. rc = -EIO;
  2426. goto err_out_disable_pdev;
  2427. }
  2428. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  2429. pr_err("No PCI resource region found\n");
  2430. rc = -ENOMEM;
  2431. goto err_out_disable_pdev;
  2432. }
  2433. rc = pci_request_regions(pdev, DRV_NAME);
  2434. if (rc) {
  2435. pr_err("Cannot obtain PCI resource region\n");
  2436. goto err_out_disable_pdev;
  2437. }
  2438. pci_set_master(pdev);
  2439. /*
  2440. * alloc and init net device
  2441. */
  2442. netdev = alloc_etherdev(sizeof(*jme));
  2443. if (!netdev) {
  2444. rc = -ENOMEM;
  2445. goto err_out_release_regions;
  2446. }
  2447. netdev->netdev_ops = &jme_netdev_ops;
  2448. netdev->ethtool_ops = &jme_ethtool_ops;
  2449. netdev->watchdog_timeo = TX_TIMEOUT;
  2450. netdev->hw_features = NETIF_F_IP_CSUM |
  2451. NETIF_F_IPV6_CSUM |
  2452. NETIF_F_SG |
  2453. NETIF_F_TSO |
  2454. NETIF_F_TSO6 |
  2455. NETIF_F_RXCSUM;
  2456. netdev->features = NETIF_F_IP_CSUM |
  2457. NETIF_F_IPV6_CSUM |
  2458. NETIF_F_SG |
  2459. NETIF_F_TSO |
  2460. NETIF_F_TSO6 |
  2461. NETIF_F_HW_VLAN_CTAG_TX |
  2462. NETIF_F_HW_VLAN_CTAG_RX;
  2463. if (using_dac)
  2464. netdev->features |= NETIF_F_HIGHDMA;
  2465. /* MTU range: 1280 - 9202*/
  2466. netdev->min_mtu = IPV6_MIN_MTU;
  2467. netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN;
  2468. SET_NETDEV_DEV(netdev, &pdev->dev);
  2469. pci_set_drvdata(pdev, netdev);
  2470. /*
  2471. * init adapter info
  2472. */
  2473. jme = netdev_priv(netdev);
  2474. jme->pdev = pdev;
  2475. jme->dev = netdev;
  2476. jme->jme_rx = netif_rx;
  2477. jme->old_mtu = netdev->mtu = 1500;
  2478. jme->phylink = 0;
  2479. jme->tx_ring_size = 1 << 10;
  2480. jme->tx_ring_mask = jme->tx_ring_size - 1;
  2481. jme->tx_wake_threshold = 1 << 9;
  2482. jme->rx_ring_size = 1 << 9;
  2483. jme->rx_ring_mask = jme->rx_ring_size - 1;
  2484. jme->msg_enable = JME_DEF_MSG_ENABLE;
  2485. jme->regs = ioremap(pci_resource_start(pdev, 0),
  2486. pci_resource_len(pdev, 0));
  2487. if (!(jme->regs)) {
  2488. pr_err("Mapping PCI resource region error\n");
  2489. rc = -ENOMEM;
  2490. goto err_out_free_netdev;
  2491. }
  2492. if (no_pseudohp) {
  2493. apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
  2494. jwrite32(jme, JME_APMC, apmc);
  2495. } else if (force_pseudohp) {
  2496. apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
  2497. jwrite32(jme, JME_APMC, apmc);
  2498. }
  2499. netif_napi_add(netdev, &jme->napi, jme_poll);
  2500. spin_lock_init(&jme->phy_lock);
  2501. spin_lock_init(&jme->macaddr_lock);
  2502. spin_lock_init(&jme->rxmcs_lock);
  2503. atomic_set(&jme->link_changing, 1);
  2504. atomic_set(&jme->rx_cleaning, 1);
  2505. atomic_set(&jme->tx_cleaning, 1);
  2506. atomic_set(&jme->rx_empty, 1);
  2507. tasklet_setup(&jme->pcc_task, jme_pcc_tasklet);
  2508. INIT_WORK(&jme->linkch_task, jme_link_change_work);
  2509. jme->dpi.cur = PCC_P1;
  2510. jme->reg_ghc = 0;
  2511. jme->reg_rxcs = RXCS_DEFAULT;
  2512. jme->reg_rxmcs = RXMCS_DEFAULT;
  2513. jme->reg_txpfc = 0;
  2514. jme->reg_pmcs = PMCS_MFEN;
  2515. jme->reg_gpreg1 = GPREG1_DEFAULT;
  2516. if (jme->reg_rxmcs & RXMCS_CHECKSUM)
  2517. netdev->features |= NETIF_F_RXCSUM;
  2518. /*
  2519. * Get Max Read Req Size from PCI Config Space
  2520. */
  2521. pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
  2522. jme->mrrs &= PCI_DCSR_MRRS_MASK;
  2523. switch (jme->mrrs) {
  2524. case MRRS_128B:
  2525. jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
  2526. break;
  2527. case MRRS_256B:
  2528. jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
  2529. break;
  2530. default:
  2531. jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
  2532. break;
  2533. }
  2534. /*
  2535. * Must check before reset_mac_processor
  2536. */
  2537. jme_check_hw_ver(jme);
  2538. jme->mii_if.dev = netdev;
  2539. if (jme->fpgaver) {
  2540. jme->mii_if.phy_id = 0;
  2541. for (i = 1 ; i < 32 ; ++i) {
  2542. bmcr = jme_mdio_read(netdev, i, MII_BMCR);
  2543. bmsr = jme_mdio_read(netdev, i, MII_BMSR);
  2544. if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
  2545. jme->mii_if.phy_id = i;
  2546. break;
  2547. }
  2548. }
  2549. if (!jme->mii_if.phy_id) {
  2550. rc = -EIO;
  2551. pr_err("Can not find phy_id\n");
  2552. goto err_out_unmap;
  2553. }
  2554. jme->reg_ghc |= GHC_LINK_POLL;
  2555. } else {
  2556. jme->mii_if.phy_id = 1;
  2557. }
  2558. if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
  2559. jme->mii_if.supports_gmii = true;
  2560. else
  2561. jme->mii_if.supports_gmii = false;
  2562. jme->mii_if.phy_id_mask = 0x1F;
  2563. jme->mii_if.reg_num_mask = 0x1F;
  2564. jme->mii_if.mdio_read = jme_mdio_read;
  2565. jme->mii_if.mdio_write = jme_mdio_write;
  2566. jme_clear_pm_disable_wol(jme);
  2567. device_init_wakeup(&pdev->dev, true);
  2568. jme_set_phyfifo_5level(jme);
  2569. jme->pcirev = pdev->revision;
  2570. if (!jme->fpgaver)
  2571. jme_phy_init(jme);
  2572. jme_phy_off(jme);
  2573. /*
  2574. * Reset MAC processor and reload EEPROM for MAC Address
  2575. */
  2576. jme_reset_mac_processor(jme);
  2577. rc = jme_reload_eeprom(jme);
  2578. if (rc) {
  2579. pr_err("Reload eeprom for reading MAC Address error\n");
  2580. goto err_out_unmap;
  2581. }
  2582. jme_load_macaddr(netdev);
  2583. /*
  2584. * Tell stack that we are not ready to work until open()
  2585. */
  2586. netif_carrier_off(netdev);
  2587. rc = register_netdev(netdev);
  2588. if (rc) {
  2589. pr_err("Cannot register net device\n");
  2590. goto err_out_unmap;
  2591. }
  2592. netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
  2593. (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
  2594. "JMC250 Gigabit Ethernet" :
  2595. (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
  2596. "JMC260 Fast Ethernet" : "Unknown",
  2597. (jme->fpgaver != 0) ? " (FPGA)" : "",
  2598. (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
  2599. jme->pcirev, netdev->dev_addr);
  2600. return 0;
  2601. err_out_unmap:
  2602. iounmap(jme->regs);
  2603. err_out_free_netdev:
  2604. free_netdev(netdev);
  2605. err_out_release_regions:
  2606. pci_release_regions(pdev);
  2607. err_out_disable_pdev:
  2608. pci_disable_device(pdev);
  2609. err_out:
  2610. return rc;
  2611. }
  2612. static void
  2613. jme_remove_one(struct pci_dev *pdev)
  2614. {
  2615. struct net_device *netdev = pci_get_drvdata(pdev);
  2616. struct jme_adapter *jme = netdev_priv(netdev);
  2617. unregister_netdev(netdev);
  2618. iounmap(jme->regs);
  2619. free_netdev(netdev);
  2620. pci_release_regions(pdev);
  2621. pci_disable_device(pdev);
  2622. }
  2623. static void
  2624. jme_shutdown(struct pci_dev *pdev)
  2625. {
  2626. struct net_device *netdev = pci_get_drvdata(pdev);
  2627. struct jme_adapter *jme = netdev_priv(netdev);
  2628. jme_powersave_phy(jme);
  2629. pci_pme_active(pdev, true);
  2630. }
  2631. #ifdef CONFIG_PM_SLEEP
  2632. static int
  2633. jme_suspend(struct device *dev)
  2634. {
  2635. struct net_device *netdev = dev_get_drvdata(dev);
  2636. struct jme_adapter *jme = netdev_priv(netdev);
  2637. if (!netif_running(netdev))
  2638. return 0;
  2639. atomic_dec(&jme->link_changing);
  2640. netif_device_detach(netdev);
  2641. netif_stop_queue(netdev);
  2642. jme_stop_irq(jme);
  2643. tasklet_disable(&jme->txclean_task);
  2644. tasklet_disable(&jme->rxclean_task);
  2645. tasklet_disable(&jme->rxempty_task);
  2646. if (netif_carrier_ok(netdev)) {
  2647. if (test_bit(JME_FLAG_POLL, &jme->flags))
  2648. jme_polling_mode(jme);
  2649. jme_stop_pcc_timer(jme);
  2650. jme_disable_rx_engine(jme);
  2651. jme_disable_tx_engine(jme);
  2652. jme_reset_mac_processor(jme);
  2653. jme_free_rx_resources(jme);
  2654. jme_free_tx_resources(jme);
  2655. netif_carrier_off(netdev);
  2656. jme->phylink = 0;
  2657. }
  2658. tasklet_enable(&jme->txclean_task);
  2659. tasklet_enable(&jme->rxclean_task);
  2660. tasklet_enable(&jme->rxempty_task);
  2661. jme_powersave_phy(jme);
  2662. return 0;
  2663. }
  2664. static int
  2665. jme_resume(struct device *dev)
  2666. {
  2667. struct net_device *netdev = dev_get_drvdata(dev);
  2668. struct jme_adapter *jme = netdev_priv(netdev);
  2669. if (!netif_running(netdev))
  2670. return 0;
  2671. jme_clear_pm_disable_wol(jme);
  2672. jme_phy_on(jme);
  2673. if (test_bit(JME_FLAG_SSET, &jme->flags))
  2674. jme_set_link_ksettings(netdev, &jme->old_cmd);
  2675. else
  2676. jme_reset_phy_processor(jme);
  2677. jme_phy_calibration(jme);
  2678. jme_phy_setEA(jme);
  2679. netif_device_attach(netdev);
  2680. atomic_inc(&jme->link_changing);
  2681. jme_reset_link(jme);
  2682. jme_start_irq(jme);
  2683. return 0;
  2684. }
  2685. static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
  2686. #define JME_PM_OPS (&jme_pm_ops)
  2687. #else
  2688. #define JME_PM_OPS NULL
  2689. #endif
  2690. static const struct pci_device_id jme_pci_tbl[] = {
  2691. { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
  2692. { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
  2693. { }
  2694. };
  2695. static struct pci_driver jme_driver = {
  2696. .name = DRV_NAME,
  2697. .id_table = jme_pci_tbl,
  2698. .probe = jme_init_one,
  2699. .remove = jme_remove_one,
  2700. .shutdown = jme_shutdown,
  2701. .driver.pm = JME_PM_OPS,
  2702. };
  2703. static int __init
  2704. jme_init_module(void)
  2705. {
  2706. pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
  2707. return pci_register_driver(&jme_driver);
  2708. }
  2709. static void __exit
  2710. jme_cleanup_module(void)
  2711. {
  2712. pci_unregister_driver(&jme_driver);
  2713. }
  2714. module_init(jme_init_module);
  2715. module_exit(jme_cleanup_module);
  2716. MODULE_AUTHOR("Guo-Fu Tseng <[email protected]>");
  2717. MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
  2718. MODULE_LICENSE("GPL");
  2719. MODULE_VERSION(DRV_VERSION);
  2720. MODULE_DEVICE_TABLE(pci, jme_pci_tbl);