dl2k.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  3. /*
  4. Copyright (c) 2001, 2002 by D-Link Corporation
  5. Written by Edward Peng.<[email protected]>
  6. Created 03-May-2001, base on Linux' sundance.c.
  7. */
  8. #include "dl2k.h"
  9. #include <linux/dma-mapping.h>
  10. #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
  11. #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
  12. #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
  13. #define dr32(reg) ioread32(ioaddr + (reg))
  14. #define dr16(reg) ioread16(ioaddr + (reg))
  15. #define dr8(reg) ioread8(ioaddr + (reg))
  16. #define MAX_UNITS 8
  17. static int mtu[MAX_UNITS];
  18. static int vlan[MAX_UNITS];
  19. static int jumbo[MAX_UNITS];
  20. static char *media[MAX_UNITS];
  21. static int tx_flow=-1;
  22. static int rx_flow=-1;
  23. static int copy_thresh;
  24. static int rx_coalesce=10; /* Rx frame count each interrupt */
  25. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  26. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  27. MODULE_AUTHOR ("Edward Peng");
  28. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  29. MODULE_LICENSE("GPL");
  30. module_param_array(mtu, int, NULL, 0);
  31. module_param_array(media, charp, NULL, 0);
  32. module_param_array(vlan, int, NULL, 0);
  33. module_param_array(jumbo, int, NULL, 0);
  34. module_param(tx_flow, int, 0);
  35. module_param(rx_flow, int, 0);
  36. module_param(copy_thresh, int, 0);
  37. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  38. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  39. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  40. /* Enable the default interrupts */
  41. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  42. UpdateStats | LinkEvent)
  43. static void dl2k_enable_int(struct netdev_private *np)
  44. {
  45. void __iomem *ioaddr = np->ioaddr;
  46. dw16(IntEnable, DEFAULT_INTR);
  47. }
  48. static const int max_intrloop = 50;
  49. static const int multicast_filter_limit = 0x40;
  50. static int rio_open (struct net_device *dev);
  51. static void rio_timer (struct timer_list *t);
  52. static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
  53. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  54. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  55. static void rio_free_tx (struct net_device *dev, int irq);
  56. static void tx_error (struct net_device *dev, int tx_status);
  57. static int receive_packet (struct net_device *dev);
  58. static void rio_error (struct net_device *dev, int int_status);
  59. static void set_multicast (struct net_device *dev);
  60. static struct net_device_stats *get_stats (struct net_device *dev);
  61. static int clear_stats (struct net_device *dev);
  62. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  63. static int rio_close (struct net_device *dev);
  64. static int find_miiphy (struct net_device *dev);
  65. static int parse_eeprom (struct net_device *dev);
  66. static int read_eeprom (struct netdev_private *, int eep_addr);
  67. static int mii_wait_link (struct net_device *dev, int wait);
  68. static int mii_set_media (struct net_device *dev);
  69. static int mii_get_media (struct net_device *dev);
  70. static int mii_set_media_pcs (struct net_device *dev);
  71. static int mii_get_media_pcs (struct net_device *dev);
  72. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  73. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  74. u16 data);
  75. static const struct ethtool_ops ethtool_ops;
  76. static const struct net_device_ops netdev_ops = {
  77. .ndo_open = rio_open,
  78. .ndo_start_xmit = start_xmit,
  79. .ndo_stop = rio_close,
  80. .ndo_get_stats = get_stats,
  81. .ndo_validate_addr = eth_validate_addr,
  82. .ndo_set_mac_address = eth_mac_addr,
  83. .ndo_set_rx_mode = set_multicast,
  84. .ndo_eth_ioctl = rio_ioctl,
  85. .ndo_tx_timeout = rio_tx_timeout,
  86. };
  87. static int
  88. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  89. {
  90. struct net_device *dev;
  91. struct netdev_private *np;
  92. static int card_idx;
  93. int chip_idx = ent->driver_data;
  94. int err, irq;
  95. void __iomem *ioaddr;
  96. void *ring_space;
  97. dma_addr_t ring_dma;
  98. err = pci_enable_device (pdev);
  99. if (err)
  100. return err;
  101. irq = pdev->irq;
  102. err = pci_request_regions (pdev, "dl2k");
  103. if (err)
  104. goto err_out_disable;
  105. pci_set_master (pdev);
  106. err = -ENOMEM;
  107. dev = alloc_etherdev (sizeof (*np));
  108. if (!dev)
  109. goto err_out_res;
  110. SET_NETDEV_DEV(dev, &pdev->dev);
  111. np = netdev_priv(dev);
  112. /* IO registers range. */
  113. ioaddr = pci_iomap(pdev, 0, 0);
  114. if (!ioaddr)
  115. goto err_out_dev;
  116. np->eeprom_addr = ioaddr;
  117. #ifdef MEM_MAPPING
  118. /* MM registers range. */
  119. ioaddr = pci_iomap(pdev, 1, 0);
  120. if (!ioaddr)
  121. goto err_out_iounmap;
  122. #endif
  123. np->ioaddr = ioaddr;
  124. np->chip_id = chip_idx;
  125. np->pdev = pdev;
  126. spin_lock_init (&np->tx_lock);
  127. spin_lock_init (&np->rx_lock);
  128. /* Parse manual configuration */
  129. np->an_enable = 1;
  130. np->tx_coalesce = 1;
  131. if (card_idx < MAX_UNITS) {
  132. if (media[card_idx] != NULL) {
  133. np->an_enable = 0;
  134. if (strcmp (media[card_idx], "auto") == 0 ||
  135. strcmp (media[card_idx], "autosense") == 0 ||
  136. strcmp (media[card_idx], "0") == 0 ) {
  137. np->an_enable = 2;
  138. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  139. strcmp (media[card_idx], "4") == 0) {
  140. np->speed = 100;
  141. np->full_duplex = 1;
  142. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  143. strcmp (media[card_idx], "3") == 0) {
  144. np->speed = 100;
  145. np->full_duplex = 0;
  146. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  147. strcmp (media[card_idx], "2") == 0) {
  148. np->speed = 10;
  149. np->full_duplex = 1;
  150. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  151. strcmp (media[card_idx], "1") == 0) {
  152. np->speed = 10;
  153. np->full_duplex = 0;
  154. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  155. strcmp (media[card_idx], "6") == 0) {
  156. np->speed=1000;
  157. np->full_duplex=1;
  158. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  159. strcmp (media[card_idx], "5") == 0) {
  160. np->speed = 1000;
  161. np->full_duplex = 0;
  162. } else {
  163. np->an_enable = 1;
  164. }
  165. }
  166. if (jumbo[card_idx] != 0) {
  167. np->jumbo = 1;
  168. dev->mtu = MAX_JUMBO;
  169. } else {
  170. np->jumbo = 0;
  171. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  172. dev->mtu = mtu[card_idx];
  173. }
  174. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  175. vlan[card_idx] : 0;
  176. if (rx_coalesce > 0 && rx_timeout > 0) {
  177. np->rx_coalesce = rx_coalesce;
  178. np->rx_timeout = rx_timeout;
  179. np->coalesce = 1;
  180. }
  181. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  182. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  183. if (tx_coalesce < 1)
  184. tx_coalesce = 1;
  185. else if (tx_coalesce > TX_RING_SIZE-1)
  186. tx_coalesce = TX_RING_SIZE - 1;
  187. }
  188. dev->netdev_ops = &netdev_ops;
  189. dev->watchdog_timeo = TX_TIMEOUT;
  190. dev->ethtool_ops = &ethtool_ops;
  191. #if 0
  192. dev->features = NETIF_F_IP_CSUM;
  193. #endif
  194. /* MTU range: 68 - 1536 or 8000 */
  195. dev->min_mtu = ETH_MIN_MTU;
  196. dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
  197. pci_set_drvdata (pdev, dev);
  198. ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
  199. GFP_KERNEL);
  200. if (!ring_space)
  201. goto err_out_iounmap;
  202. np->tx_ring = ring_space;
  203. np->tx_ring_dma = ring_dma;
  204. ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
  205. GFP_KERNEL);
  206. if (!ring_space)
  207. goto err_out_unmap_tx;
  208. np->rx_ring = ring_space;
  209. np->rx_ring_dma = ring_dma;
  210. /* Parse eeprom data */
  211. parse_eeprom (dev);
  212. /* Find PHY address */
  213. err = find_miiphy (dev);
  214. if (err)
  215. goto err_out_unmap_rx;
  216. /* Fiber device? */
  217. np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
  218. np->link_status = 0;
  219. /* Set media and reset PHY */
  220. if (np->phy_media) {
  221. /* default Auto-Negotiation for fiber deivices */
  222. if (np->an_enable == 2) {
  223. np->an_enable = 1;
  224. }
  225. } else {
  226. /* Auto-Negotiation is mandatory for 1000BASE-T,
  227. IEEE 802.3ab Annex 28D page 14 */
  228. if (np->speed == 1000)
  229. np->an_enable = 1;
  230. }
  231. err = register_netdev (dev);
  232. if (err)
  233. goto err_out_unmap_rx;
  234. card_idx++;
  235. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  236. dev->name, np->name, dev->dev_addr, irq);
  237. if (tx_coalesce > 1)
  238. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  239. tx_coalesce);
  240. if (np->coalesce)
  241. printk(KERN_INFO
  242. "rx_coalesce:\t%d packets\n"
  243. "rx_timeout: \t%d ns\n",
  244. np->rx_coalesce, np->rx_timeout*640);
  245. if (np->vlan)
  246. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  247. return 0;
  248. err_out_unmap_rx:
  249. dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
  250. np->rx_ring_dma);
  251. err_out_unmap_tx:
  252. dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
  253. np->tx_ring_dma);
  254. err_out_iounmap:
  255. #ifdef MEM_MAPPING
  256. pci_iounmap(pdev, np->ioaddr);
  257. #endif
  258. pci_iounmap(pdev, np->eeprom_addr);
  259. err_out_dev:
  260. free_netdev (dev);
  261. err_out_res:
  262. pci_release_regions (pdev);
  263. err_out_disable:
  264. pci_disable_device (pdev);
  265. return err;
  266. }
  267. static int
  268. find_miiphy (struct net_device *dev)
  269. {
  270. struct netdev_private *np = netdev_priv(dev);
  271. int i, phy_found = 0;
  272. np->phy_addr = 1;
  273. for (i = 31; i >= 0; i--) {
  274. int mii_status = mii_read (dev, i, 1);
  275. if (mii_status != 0xffff && mii_status != 0x0000) {
  276. np->phy_addr = i;
  277. phy_found++;
  278. }
  279. }
  280. if (!phy_found) {
  281. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  282. return -ENODEV;
  283. }
  284. return 0;
  285. }
  286. static int
  287. parse_eeprom (struct net_device *dev)
  288. {
  289. struct netdev_private *np = netdev_priv(dev);
  290. void __iomem *ioaddr = np->ioaddr;
  291. int i, j;
  292. u8 sromdata[256];
  293. u8 *psib;
  294. u32 crc;
  295. PSROM_t psrom = (PSROM_t) sromdata;
  296. int cid, next;
  297. for (i = 0; i < 128; i++)
  298. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
  299. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  300. /* Check CRC */
  301. crc = ~ether_crc_le (256 - 4, sromdata);
  302. if (psrom->crc != cpu_to_le32(crc)) {
  303. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  304. dev->name);
  305. return -1;
  306. }
  307. }
  308. /* Set MAC address */
  309. eth_hw_addr_set(dev, psrom->mac_addr);
  310. if (np->chip_id == CHIP_IP1000A) {
  311. np->led_mode = psrom->led_mode;
  312. return 0;
  313. }
  314. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  315. return 0;
  316. }
  317. /* Parse Software Information Block */
  318. i = 0x30;
  319. psib = (u8 *) sromdata;
  320. do {
  321. cid = psib[i++];
  322. next = psib[i++];
  323. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  324. printk (KERN_ERR "Cell data error\n");
  325. return -1;
  326. }
  327. switch (cid) {
  328. case 0: /* Format version */
  329. break;
  330. case 1: /* End of cell */
  331. return 0;
  332. case 2: /* Duplex Polarity */
  333. np->duplex_polarity = psib[i];
  334. dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
  335. break;
  336. case 3: /* Wake Polarity */
  337. np->wake_polarity = psib[i];
  338. break;
  339. case 9: /* Adapter description */
  340. j = (next - i > 255) ? 255 : next - i;
  341. memcpy (np->name, &(psib[i]), j);
  342. break;
  343. case 4:
  344. case 5:
  345. case 6:
  346. case 7:
  347. case 8: /* Reversed */
  348. break;
  349. default: /* Unknown cell */
  350. return -1;
  351. }
  352. i = next;
  353. } while (1);
  354. return 0;
  355. }
  356. static void rio_set_led_mode(struct net_device *dev)
  357. {
  358. struct netdev_private *np = netdev_priv(dev);
  359. void __iomem *ioaddr = np->ioaddr;
  360. u32 mode;
  361. if (np->chip_id != CHIP_IP1000A)
  362. return;
  363. mode = dr32(ASICCtrl);
  364. mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
  365. if (np->led_mode & 0x01)
  366. mode |= IPG_AC_LED_MODE;
  367. if (np->led_mode & 0x02)
  368. mode |= IPG_AC_LED_MODE_BIT_1;
  369. if (np->led_mode & 0x08)
  370. mode |= IPG_AC_LED_SPEED;
  371. dw32(ASICCtrl, mode);
  372. }
  373. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  374. {
  375. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  376. }
  377. static void free_list(struct net_device *dev)
  378. {
  379. struct netdev_private *np = netdev_priv(dev);
  380. struct sk_buff *skb;
  381. int i;
  382. /* Free all the skbuffs in the queue. */
  383. for (i = 0; i < RX_RING_SIZE; i++) {
  384. skb = np->rx_skbuff[i];
  385. if (skb) {
  386. dma_unmap_single(&np->pdev->dev,
  387. desc_to_dma(&np->rx_ring[i]),
  388. skb->len, DMA_FROM_DEVICE);
  389. dev_kfree_skb(skb);
  390. np->rx_skbuff[i] = NULL;
  391. }
  392. np->rx_ring[i].status = 0;
  393. np->rx_ring[i].fraginfo = 0;
  394. }
  395. for (i = 0; i < TX_RING_SIZE; i++) {
  396. skb = np->tx_skbuff[i];
  397. if (skb) {
  398. dma_unmap_single(&np->pdev->dev,
  399. desc_to_dma(&np->tx_ring[i]),
  400. skb->len, DMA_TO_DEVICE);
  401. dev_kfree_skb(skb);
  402. np->tx_skbuff[i] = NULL;
  403. }
  404. }
  405. }
  406. static void rio_reset_ring(struct netdev_private *np)
  407. {
  408. int i;
  409. np->cur_rx = 0;
  410. np->cur_tx = 0;
  411. np->old_rx = 0;
  412. np->old_tx = 0;
  413. for (i = 0; i < TX_RING_SIZE; i++)
  414. np->tx_ring[i].status = cpu_to_le64(TFDDone);
  415. for (i = 0; i < RX_RING_SIZE; i++)
  416. np->rx_ring[i].status = 0;
  417. }
  418. /* allocate and initialize Tx and Rx descriptors */
  419. static int alloc_list(struct net_device *dev)
  420. {
  421. struct netdev_private *np = netdev_priv(dev);
  422. int i;
  423. rio_reset_ring(np);
  424. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  425. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  426. for (i = 0; i < TX_RING_SIZE; i++) {
  427. np->tx_skbuff[i] = NULL;
  428. np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
  429. ((i + 1) % TX_RING_SIZE) *
  430. sizeof(struct netdev_desc));
  431. }
  432. /* Initialize Rx descriptors & allocate buffers */
  433. for (i = 0; i < RX_RING_SIZE; i++) {
  434. /* Allocated fixed size of skbuff */
  435. struct sk_buff *skb;
  436. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  437. np->rx_skbuff[i] = skb;
  438. if (!skb) {
  439. free_list(dev);
  440. return -ENOMEM;
  441. }
  442. np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
  443. ((i + 1) % RX_RING_SIZE) *
  444. sizeof(struct netdev_desc));
  445. /* Rubicon now supports 40 bits of addressing space. */
  446. np->rx_ring[i].fraginfo =
  447. cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
  448. np->rx_buf_sz, DMA_FROM_DEVICE));
  449. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  450. }
  451. return 0;
  452. }
  453. static void rio_hw_init(struct net_device *dev)
  454. {
  455. struct netdev_private *np = netdev_priv(dev);
  456. void __iomem *ioaddr = np->ioaddr;
  457. int i;
  458. u16 macctrl;
  459. /* Reset all logic functions */
  460. dw16(ASICCtrl + 2,
  461. GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
  462. mdelay(10);
  463. rio_set_led_mode(dev);
  464. /* DebugCtrl bit 4, 5, 9 must set */
  465. dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
  466. if (np->chip_id == CHIP_IP1000A &&
  467. (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
  468. /* PHY magic taken from ipg driver, undocumented registers */
  469. mii_write(dev, np->phy_addr, 31, 0x0001);
  470. mii_write(dev, np->phy_addr, 27, 0x01e0);
  471. mii_write(dev, np->phy_addr, 31, 0x0002);
  472. mii_write(dev, np->phy_addr, 27, 0xeb8e);
  473. mii_write(dev, np->phy_addr, 31, 0x0000);
  474. mii_write(dev, np->phy_addr, 30, 0x005e);
  475. /* advertise 1000BASE-T half & full duplex, prefer MASTER */
  476. mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
  477. }
  478. if (np->phy_media)
  479. mii_set_media_pcs(dev);
  480. else
  481. mii_set_media(dev);
  482. /* Jumbo frame */
  483. if (np->jumbo != 0)
  484. dw16(MaxFrameSize, MAX_JUMBO+14);
  485. /* Set RFDListPtr */
  486. dw32(RFDListPtr0, np->rx_ring_dma);
  487. dw32(RFDListPtr1, 0);
  488. /* Set station address */
  489. /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
  490. * too. However, it doesn't work on IP1000A so we use 16-bit access.
  491. */
  492. for (i = 0; i < 3; i++)
  493. dw16(StationAddr0 + 2 * i,
  494. cpu_to_le16(((const u16 *)dev->dev_addr)[i]));
  495. set_multicast (dev);
  496. if (np->coalesce) {
  497. dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
  498. }
  499. /* Set RIO to poll every N*320nsec. */
  500. dw8(RxDMAPollPeriod, 0x20);
  501. dw8(TxDMAPollPeriod, 0xff);
  502. dw8(RxDMABurstThresh, 0x30);
  503. dw8(RxDMAUrgentThresh, 0x30);
  504. dw32(RmonStatMask, 0x0007ffff);
  505. /* clear statistics */
  506. clear_stats (dev);
  507. /* VLAN supported */
  508. if (np->vlan) {
  509. /* priority field in RxDMAIntCtrl */
  510. dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
  511. /* VLANId */
  512. dw16(VLANId, np->vlan);
  513. /* Length/Type should be 0x8100 */
  514. dw32(VLANTag, 0x8100 << 16 | np->vlan);
  515. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  516. VLAN information tagged by TFC' VID, CFI fields. */
  517. dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
  518. }
  519. /* Start Tx/Rx */
  520. dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
  521. macctrl = 0;
  522. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  523. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  524. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  525. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  526. dw16(MACCtrl, macctrl);
  527. }
  528. static void rio_hw_stop(struct net_device *dev)
  529. {
  530. struct netdev_private *np = netdev_priv(dev);
  531. void __iomem *ioaddr = np->ioaddr;
  532. /* Disable interrupts */
  533. dw16(IntEnable, 0);
  534. /* Stop Tx and Rx logics */
  535. dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
  536. }
  537. static int rio_open(struct net_device *dev)
  538. {
  539. struct netdev_private *np = netdev_priv(dev);
  540. const int irq = np->pdev->irq;
  541. int i;
  542. i = alloc_list(dev);
  543. if (i)
  544. return i;
  545. rio_hw_init(dev);
  546. i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  547. if (i) {
  548. rio_hw_stop(dev);
  549. free_list(dev);
  550. return i;
  551. }
  552. timer_setup(&np->timer, rio_timer, 0);
  553. np->timer.expires = jiffies + 1 * HZ;
  554. add_timer(&np->timer);
  555. netif_start_queue (dev);
  556. dl2k_enable_int(np);
  557. return 0;
  558. }
  559. static void
  560. rio_timer (struct timer_list *t)
  561. {
  562. struct netdev_private *np = from_timer(np, t, timer);
  563. struct net_device *dev = pci_get_drvdata(np->pdev);
  564. unsigned int entry;
  565. int next_tick = 1*HZ;
  566. unsigned long flags;
  567. spin_lock_irqsave(&np->rx_lock, flags);
  568. /* Recover rx ring exhausted error */
  569. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  570. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  571. /* Re-allocate skbuffs to fill the descriptor ring */
  572. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  573. struct sk_buff *skb;
  574. entry = np->old_rx % RX_RING_SIZE;
  575. /* Dropped packets don't need to re-allocate */
  576. if (np->rx_skbuff[entry] == NULL) {
  577. skb = netdev_alloc_skb_ip_align(dev,
  578. np->rx_buf_sz);
  579. if (skb == NULL) {
  580. np->rx_ring[entry].fraginfo = 0;
  581. printk (KERN_INFO
  582. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  583. dev->name, entry);
  584. break;
  585. }
  586. np->rx_skbuff[entry] = skb;
  587. np->rx_ring[entry].fraginfo =
  588. cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
  589. np->rx_buf_sz, DMA_FROM_DEVICE));
  590. }
  591. np->rx_ring[entry].fraginfo |=
  592. cpu_to_le64((u64)np->rx_buf_sz << 48);
  593. np->rx_ring[entry].status = 0;
  594. } /* end for */
  595. } /* end if */
  596. spin_unlock_irqrestore (&np->rx_lock, flags);
  597. np->timer.expires = jiffies + next_tick;
  598. add_timer(&np->timer);
  599. }
  600. static void
  601. rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
  602. {
  603. struct netdev_private *np = netdev_priv(dev);
  604. void __iomem *ioaddr = np->ioaddr;
  605. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  606. dev->name, dr32(TxStatus));
  607. rio_free_tx(dev, 0);
  608. dev->if_port = 0;
  609. netif_trans_update(dev); /* prevent tx timeout */
  610. }
  611. static netdev_tx_t
  612. start_xmit (struct sk_buff *skb, struct net_device *dev)
  613. {
  614. struct netdev_private *np = netdev_priv(dev);
  615. void __iomem *ioaddr = np->ioaddr;
  616. struct netdev_desc *txdesc;
  617. unsigned entry;
  618. u64 tfc_vlan_tag = 0;
  619. if (np->link_status == 0) { /* Link Down */
  620. dev_kfree_skb(skb);
  621. return NETDEV_TX_OK;
  622. }
  623. entry = np->cur_tx % TX_RING_SIZE;
  624. np->tx_skbuff[entry] = skb;
  625. txdesc = &np->tx_ring[entry];
  626. #if 0
  627. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  628. txdesc->status |=
  629. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  630. IPChecksumEnable);
  631. }
  632. #endif
  633. if (np->vlan) {
  634. tfc_vlan_tag = VLANTagInsert |
  635. ((u64)np->vlan << 32) |
  636. ((u64)skb->priority << 45);
  637. }
  638. txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
  639. skb->len, DMA_TO_DEVICE));
  640. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  641. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  642. * Work around: Always use 1 descriptor in 10Mbps mode */
  643. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  644. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  645. WordAlignDisable |
  646. TxDMAIndicate |
  647. (1 << FragCountShift));
  648. else
  649. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  650. WordAlignDisable |
  651. (1 << FragCountShift));
  652. /* TxDMAPollNow */
  653. dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
  654. /* Schedule ISR */
  655. dw32(CountDown, 10000);
  656. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  657. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  658. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  659. /* do nothing */
  660. } else if (!netif_queue_stopped(dev)) {
  661. netif_stop_queue (dev);
  662. }
  663. /* The first TFDListPtr */
  664. if (!dr32(TFDListPtr0)) {
  665. dw32(TFDListPtr0, np->tx_ring_dma +
  666. entry * sizeof (struct netdev_desc));
  667. dw32(TFDListPtr1, 0);
  668. }
  669. return NETDEV_TX_OK;
  670. }
  671. static irqreturn_t
  672. rio_interrupt (int irq, void *dev_instance)
  673. {
  674. struct net_device *dev = dev_instance;
  675. struct netdev_private *np = netdev_priv(dev);
  676. void __iomem *ioaddr = np->ioaddr;
  677. unsigned int_status;
  678. int cnt = max_intrloop;
  679. int handled = 0;
  680. while (1) {
  681. int_status = dr16(IntStatus);
  682. dw16(IntStatus, int_status);
  683. int_status &= DEFAULT_INTR;
  684. if (int_status == 0 || --cnt < 0)
  685. break;
  686. handled = 1;
  687. /* Processing received packets */
  688. if (int_status & RxDMAComplete)
  689. receive_packet (dev);
  690. /* TxDMAComplete interrupt */
  691. if ((int_status & (TxDMAComplete|IntRequested))) {
  692. int tx_status;
  693. tx_status = dr32(TxStatus);
  694. if (tx_status & 0x01)
  695. tx_error (dev, tx_status);
  696. /* Free used tx skbuffs */
  697. rio_free_tx (dev, 1);
  698. }
  699. /* Handle uncommon events */
  700. if (int_status &
  701. (HostError | LinkEvent | UpdateStats))
  702. rio_error (dev, int_status);
  703. }
  704. if (np->cur_tx != np->old_tx)
  705. dw32(CountDown, 100);
  706. return IRQ_RETVAL(handled);
  707. }
  708. static void
  709. rio_free_tx (struct net_device *dev, int irq)
  710. {
  711. struct netdev_private *np = netdev_priv(dev);
  712. int entry = np->old_tx % TX_RING_SIZE;
  713. int tx_use = 0;
  714. unsigned long flag = 0;
  715. if (irq)
  716. spin_lock(&np->tx_lock);
  717. else
  718. spin_lock_irqsave(&np->tx_lock, flag);
  719. /* Free used tx skbuffs */
  720. while (entry != np->cur_tx) {
  721. struct sk_buff *skb;
  722. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  723. break;
  724. skb = np->tx_skbuff[entry];
  725. dma_unmap_single(&np->pdev->dev,
  726. desc_to_dma(&np->tx_ring[entry]), skb->len,
  727. DMA_TO_DEVICE);
  728. if (irq)
  729. dev_consume_skb_irq(skb);
  730. else
  731. dev_kfree_skb(skb);
  732. np->tx_skbuff[entry] = NULL;
  733. entry = (entry + 1) % TX_RING_SIZE;
  734. tx_use++;
  735. }
  736. if (irq)
  737. spin_unlock(&np->tx_lock);
  738. else
  739. spin_unlock_irqrestore(&np->tx_lock, flag);
  740. np->old_tx = entry;
  741. /* If the ring is no longer full, clear tx_full and
  742. call netif_wake_queue() */
  743. if (netif_queue_stopped(dev) &&
  744. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  745. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  746. netif_wake_queue (dev);
  747. }
  748. }
  749. static void
  750. tx_error (struct net_device *dev, int tx_status)
  751. {
  752. struct netdev_private *np = netdev_priv(dev);
  753. void __iomem *ioaddr = np->ioaddr;
  754. int frame_id;
  755. int i;
  756. frame_id = (tx_status & 0xffff0000);
  757. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  758. dev->name, tx_status, frame_id);
  759. dev->stats.tx_errors++;
  760. /* Ttransmit Underrun */
  761. if (tx_status & 0x10) {
  762. dev->stats.tx_fifo_errors++;
  763. dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
  764. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  765. dw16(ASICCtrl + 2,
  766. TxReset | DMAReset | FIFOReset | NetworkReset);
  767. /* Wait for ResetBusy bit clear */
  768. for (i = 50; i > 0; i--) {
  769. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  770. break;
  771. mdelay (1);
  772. }
  773. rio_set_led_mode(dev);
  774. rio_free_tx (dev, 1);
  775. /* Reset TFDListPtr */
  776. dw32(TFDListPtr0, np->tx_ring_dma +
  777. np->old_tx * sizeof (struct netdev_desc));
  778. dw32(TFDListPtr1, 0);
  779. /* Let TxStartThresh stay default value */
  780. }
  781. /* Late Collision */
  782. if (tx_status & 0x04) {
  783. dev->stats.tx_fifo_errors++;
  784. /* TxReset and clear FIFO */
  785. dw16(ASICCtrl + 2, TxReset | FIFOReset);
  786. /* Wait reset done */
  787. for (i = 50; i > 0; i--) {
  788. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  789. break;
  790. mdelay (1);
  791. }
  792. rio_set_led_mode(dev);
  793. /* Let TxStartThresh stay default value */
  794. }
  795. /* Maximum Collisions */
  796. if (tx_status & 0x08)
  797. dev->stats.collisions++;
  798. /* Restart the Tx */
  799. dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
  800. }
  801. static int
  802. receive_packet (struct net_device *dev)
  803. {
  804. struct netdev_private *np = netdev_priv(dev);
  805. int entry = np->cur_rx % RX_RING_SIZE;
  806. int cnt = 30;
  807. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  808. while (1) {
  809. struct netdev_desc *desc = &np->rx_ring[entry];
  810. int pkt_len;
  811. u64 frame_status;
  812. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  813. !(desc->status & cpu_to_le64(FrameStart)) ||
  814. !(desc->status & cpu_to_le64(FrameEnd)))
  815. break;
  816. /* Chip omits the CRC. */
  817. frame_status = le64_to_cpu(desc->status);
  818. pkt_len = frame_status & 0xffff;
  819. if (--cnt < 0)
  820. break;
  821. /* Update rx error statistics, drop packet. */
  822. if (frame_status & RFS_Errors) {
  823. dev->stats.rx_errors++;
  824. if (frame_status & (RxRuntFrame | RxLengthError))
  825. dev->stats.rx_length_errors++;
  826. if (frame_status & RxFCSError)
  827. dev->stats.rx_crc_errors++;
  828. if (frame_status & RxAlignmentError && np->speed != 1000)
  829. dev->stats.rx_frame_errors++;
  830. if (frame_status & RxFIFOOverrun)
  831. dev->stats.rx_fifo_errors++;
  832. } else {
  833. struct sk_buff *skb;
  834. /* Small skbuffs for short packets */
  835. if (pkt_len > copy_thresh) {
  836. dma_unmap_single(&np->pdev->dev,
  837. desc_to_dma(desc),
  838. np->rx_buf_sz,
  839. DMA_FROM_DEVICE);
  840. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  841. np->rx_skbuff[entry] = NULL;
  842. } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
  843. dma_sync_single_for_cpu(&np->pdev->dev,
  844. desc_to_dma(desc),
  845. np->rx_buf_sz,
  846. DMA_FROM_DEVICE);
  847. skb_copy_to_linear_data (skb,
  848. np->rx_skbuff[entry]->data,
  849. pkt_len);
  850. skb_put (skb, pkt_len);
  851. dma_sync_single_for_device(&np->pdev->dev,
  852. desc_to_dma(desc),
  853. np->rx_buf_sz,
  854. DMA_FROM_DEVICE);
  855. }
  856. skb->protocol = eth_type_trans (skb, dev);
  857. #if 0
  858. /* Checksum done by hw, but csum value unavailable. */
  859. if (np->pdev->pci_rev_id >= 0x0c &&
  860. !(frame_status & (TCPError | UDPError | IPError))) {
  861. skb->ip_summed = CHECKSUM_UNNECESSARY;
  862. }
  863. #endif
  864. netif_rx (skb);
  865. }
  866. entry = (entry + 1) % RX_RING_SIZE;
  867. }
  868. spin_lock(&np->rx_lock);
  869. np->cur_rx = entry;
  870. /* Re-allocate skbuffs to fill the descriptor ring */
  871. entry = np->old_rx;
  872. while (entry != np->cur_rx) {
  873. struct sk_buff *skb;
  874. /* Dropped packets don't need to re-allocate */
  875. if (np->rx_skbuff[entry] == NULL) {
  876. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  877. if (skb == NULL) {
  878. np->rx_ring[entry].fraginfo = 0;
  879. printk (KERN_INFO
  880. "%s: receive_packet: "
  881. "Unable to re-allocate Rx skbuff.#%d\n",
  882. dev->name, entry);
  883. break;
  884. }
  885. np->rx_skbuff[entry] = skb;
  886. np->rx_ring[entry].fraginfo =
  887. cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
  888. np->rx_buf_sz, DMA_FROM_DEVICE));
  889. }
  890. np->rx_ring[entry].fraginfo |=
  891. cpu_to_le64((u64)np->rx_buf_sz << 48);
  892. np->rx_ring[entry].status = 0;
  893. entry = (entry + 1) % RX_RING_SIZE;
  894. }
  895. np->old_rx = entry;
  896. spin_unlock(&np->rx_lock);
  897. return 0;
  898. }
  899. static void
  900. rio_error (struct net_device *dev, int int_status)
  901. {
  902. struct netdev_private *np = netdev_priv(dev);
  903. void __iomem *ioaddr = np->ioaddr;
  904. u16 macctrl;
  905. /* Link change event */
  906. if (int_status & LinkEvent) {
  907. if (mii_wait_link (dev, 10) == 0) {
  908. printk (KERN_INFO "%s: Link up\n", dev->name);
  909. if (np->phy_media)
  910. mii_get_media_pcs (dev);
  911. else
  912. mii_get_media (dev);
  913. if (np->speed == 1000)
  914. np->tx_coalesce = tx_coalesce;
  915. else
  916. np->tx_coalesce = 1;
  917. macctrl = 0;
  918. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  919. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  920. macctrl |= (np->tx_flow) ?
  921. TxFlowControlEnable : 0;
  922. macctrl |= (np->rx_flow) ?
  923. RxFlowControlEnable : 0;
  924. dw16(MACCtrl, macctrl);
  925. np->link_status = 1;
  926. netif_carrier_on(dev);
  927. } else {
  928. printk (KERN_INFO "%s: Link off\n", dev->name);
  929. np->link_status = 0;
  930. netif_carrier_off(dev);
  931. }
  932. }
  933. /* UpdateStats statistics registers */
  934. if (int_status & UpdateStats) {
  935. get_stats (dev);
  936. }
  937. /* PCI Error, a catastronphic error related to the bus interface
  938. occurs, set GlobalReset and HostReset to reset. */
  939. if (int_status & HostError) {
  940. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  941. dev->name, int_status);
  942. dw16(ASICCtrl + 2, GlobalReset | HostReset);
  943. mdelay (500);
  944. rio_set_led_mode(dev);
  945. }
  946. }
  947. static struct net_device_stats *
  948. get_stats (struct net_device *dev)
  949. {
  950. struct netdev_private *np = netdev_priv(dev);
  951. void __iomem *ioaddr = np->ioaddr;
  952. #ifdef MEM_MAPPING
  953. int i;
  954. #endif
  955. unsigned int stat_reg;
  956. /* All statistics registers need to be acknowledged,
  957. else statistic overflow could cause problems */
  958. dev->stats.rx_packets += dr32(FramesRcvOk);
  959. dev->stats.tx_packets += dr32(FramesXmtOk);
  960. dev->stats.rx_bytes += dr32(OctetRcvOk);
  961. dev->stats.tx_bytes += dr32(OctetXmtOk);
  962. dev->stats.multicast = dr32(McstFramesRcvdOk);
  963. dev->stats.collisions += dr32(SingleColFrames)
  964. + dr32(MultiColFrames);
  965. /* detailed tx errors */
  966. stat_reg = dr16(FramesAbortXSColls);
  967. dev->stats.tx_aborted_errors += stat_reg;
  968. dev->stats.tx_errors += stat_reg;
  969. stat_reg = dr16(CarrierSenseErrors);
  970. dev->stats.tx_carrier_errors += stat_reg;
  971. dev->stats.tx_errors += stat_reg;
  972. /* Clear all other statistic register. */
  973. dr32(McstOctetXmtOk);
  974. dr16(BcstFramesXmtdOk);
  975. dr32(McstFramesXmtdOk);
  976. dr16(BcstFramesRcvdOk);
  977. dr16(MacControlFramesRcvd);
  978. dr16(FrameTooLongErrors);
  979. dr16(InRangeLengthErrors);
  980. dr16(FramesCheckSeqErrors);
  981. dr16(FramesLostRxErrors);
  982. dr32(McstOctetXmtOk);
  983. dr32(BcstOctetXmtOk);
  984. dr32(McstFramesXmtdOk);
  985. dr32(FramesWDeferredXmt);
  986. dr32(LateCollisions);
  987. dr16(BcstFramesXmtdOk);
  988. dr16(MacControlFramesXmtd);
  989. dr16(FramesWEXDeferal);
  990. #ifdef MEM_MAPPING
  991. for (i = 0x100; i <= 0x150; i += 4)
  992. dr32(i);
  993. #endif
  994. dr16(TxJumboFrames);
  995. dr16(RxJumboFrames);
  996. dr16(TCPCheckSumErrors);
  997. dr16(UDPCheckSumErrors);
  998. dr16(IPCheckSumErrors);
  999. return &dev->stats;
  1000. }
  1001. static int
  1002. clear_stats (struct net_device *dev)
  1003. {
  1004. struct netdev_private *np = netdev_priv(dev);
  1005. void __iomem *ioaddr = np->ioaddr;
  1006. #ifdef MEM_MAPPING
  1007. int i;
  1008. #endif
  1009. /* All statistics registers need to be acknowledged,
  1010. else statistic overflow could cause problems */
  1011. dr32(FramesRcvOk);
  1012. dr32(FramesXmtOk);
  1013. dr32(OctetRcvOk);
  1014. dr32(OctetXmtOk);
  1015. dr32(McstFramesRcvdOk);
  1016. dr32(SingleColFrames);
  1017. dr32(MultiColFrames);
  1018. dr32(LateCollisions);
  1019. /* detailed rx errors */
  1020. dr16(FrameTooLongErrors);
  1021. dr16(InRangeLengthErrors);
  1022. dr16(FramesCheckSeqErrors);
  1023. dr16(FramesLostRxErrors);
  1024. /* detailed tx errors */
  1025. dr16(FramesAbortXSColls);
  1026. dr16(CarrierSenseErrors);
  1027. /* Clear all other statistic register. */
  1028. dr32(McstOctetXmtOk);
  1029. dr16(BcstFramesXmtdOk);
  1030. dr32(McstFramesXmtdOk);
  1031. dr16(BcstFramesRcvdOk);
  1032. dr16(MacControlFramesRcvd);
  1033. dr32(McstOctetXmtOk);
  1034. dr32(BcstOctetXmtOk);
  1035. dr32(McstFramesXmtdOk);
  1036. dr32(FramesWDeferredXmt);
  1037. dr16(BcstFramesXmtdOk);
  1038. dr16(MacControlFramesXmtd);
  1039. dr16(FramesWEXDeferal);
  1040. #ifdef MEM_MAPPING
  1041. for (i = 0x100; i <= 0x150; i += 4)
  1042. dr32(i);
  1043. #endif
  1044. dr16(TxJumboFrames);
  1045. dr16(RxJumboFrames);
  1046. dr16(TCPCheckSumErrors);
  1047. dr16(UDPCheckSumErrors);
  1048. dr16(IPCheckSumErrors);
  1049. return 0;
  1050. }
  1051. static void
  1052. set_multicast (struct net_device *dev)
  1053. {
  1054. struct netdev_private *np = netdev_priv(dev);
  1055. void __iomem *ioaddr = np->ioaddr;
  1056. u32 hash_table[2];
  1057. u16 rx_mode = 0;
  1058. hash_table[0] = hash_table[1] = 0;
  1059. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1060. hash_table[1] |= 0x02000000;
  1061. if (dev->flags & IFF_PROMISC) {
  1062. /* Receive all frames promiscuously. */
  1063. rx_mode = ReceiveAllFrames;
  1064. } else if ((dev->flags & IFF_ALLMULTI) ||
  1065. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1066. /* Receive broadcast and multicast frames */
  1067. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1068. } else if (!netdev_mc_empty(dev)) {
  1069. struct netdev_hw_addr *ha;
  1070. /* Receive broadcast frames and multicast frames filtering
  1071. by Hashtable */
  1072. rx_mode =
  1073. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1074. netdev_for_each_mc_addr(ha, dev) {
  1075. int bit, index = 0;
  1076. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1077. /* The inverted high significant 6 bits of CRC are
  1078. used as an index to hashtable */
  1079. for (bit = 0; bit < 6; bit++)
  1080. if (crc & (1 << (31 - bit)))
  1081. index |= (1 << bit);
  1082. hash_table[index / 32] |= (1 << (index % 32));
  1083. }
  1084. } else {
  1085. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1086. }
  1087. if (np->vlan) {
  1088. /* ReceiveVLANMatch field in ReceiveMode */
  1089. rx_mode |= ReceiveVLANMatch;
  1090. }
  1091. dw32(HashTable0, hash_table[0]);
  1092. dw32(HashTable1, hash_table[1]);
  1093. dw16(ReceiveMode, rx_mode);
  1094. }
  1095. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1096. {
  1097. struct netdev_private *np = netdev_priv(dev);
  1098. strscpy(info->driver, "dl2k", sizeof(info->driver));
  1099. strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
  1100. }
  1101. static int rio_get_link_ksettings(struct net_device *dev,
  1102. struct ethtool_link_ksettings *cmd)
  1103. {
  1104. struct netdev_private *np = netdev_priv(dev);
  1105. u32 supported, advertising;
  1106. if (np->phy_media) {
  1107. /* fiber device */
  1108. supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1109. advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1110. cmd->base.port = PORT_FIBRE;
  1111. } else {
  1112. /* copper device */
  1113. supported = SUPPORTED_10baseT_Half |
  1114. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1115. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1116. SUPPORTED_Autoneg | SUPPORTED_MII;
  1117. advertising = ADVERTISED_10baseT_Half |
  1118. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1119. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
  1120. ADVERTISED_Autoneg | ADVERTISED_MII;
  1121. cmd->base.port = PORT_MII;
  1122. }
  1123. if (np->link_status) {
  1124. cmd->base.speed = np->speed;
  1125. cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1126. } else {
  1127. cmd->base.speed = SPEED_UNKNOWN;
  1128. cmd->base.duplex = DUPLEX_UNKNOWN;
  1129. }
  1130. if (np->an_enable)
  1131. cmd->base.autoneg = AUTONEG_ENABLE;
  1132. else
  1133. cmd->base.autoneg = AUTONEG_DISABLE;
  1134. cmd->base.phy_address = np->phy_addr;
  1135. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
  1136. supported);
  1137. ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
  1138. advertising);
  1139. return 0;
  1140. }
  1141. static int rio_set_link_ksettings(struct net_device *dev,
  1142. const struct ethtool_link_ksettings *cmd)
  1143. {
  1144. struct netdev_private *np = netdev_priv(dev);
  1145. u32 speed = cmd->base.speed;
  1146. u8 duplex = cmd->base.duplex;
  1147. netif_carrier_off(dev);
  1148. if (cmd->base.autoneg == AUTONEG_ENABLE) {
  1149. if (np->an_enable) {
  1150. return 0;
  1151. } else {
  1152. np->an_enable = 1;
  1153. mii_set_media(dev);
  1154. return 0;
  1155. }
  1156. } else {
  1157. np->an_enable = 0;
  1158. if (np->speed == 1000) {
  1159. speed = SPEED_100;
  1160. duplex = DUPLEX_FULL;
  1161. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1162. }
  1163. switch (speed) {
  1164. case SPEED_10:
  1165. np->speed = 10;
  1166. np->full_duplex = (duplex == DUPLEX_FULL);
  1167. break;
  1168. case SPEED_100:
  1169. np->speed = 100;
  1170. np->full_duplex = (duplex == DUPLEX_FULL);
  1171. break;
  1172. case SPEED_1000: /* not supported */
  1173. default:
  1174. return -EINVAL;
  1175. }
  1176. mii_set_media(dev);
  1177. }
  1178. return 0;
  1179. }
  1180. static u32 rio_get_link(struct net_device *dev)
  1181. {
  1182. struct netdev_private *np = netdev_priv(dev);
  1183. return np->link_status;
  1184. }
  1185. static const struct ethtool_ops ethtool_ops = {
  1186. .get_drvinfo = rio_get_drvinfo,
  1187. .get_link = rio_get_link,
  1188. .get_link_ksettings = rio_get_link_ksettings,
  1189. .set_link_ksettings = rio_set_link_ksettings,
  1190. };
  1191. static int
  1192. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1193. {
  1194. int phy_addr;
  1195. struct netdev_private *np = netdev_priv(dev);
  1196. struct mii_ioctl_data *miidata = if_mii(rq);
  1197. phy_addr = np->phy_addr;
  1198. switch (cmd) {
  1199. case SIOCGMIIPHY:
  1200. miidata->phy_id = phy_addr;
  1201. break;
  1202. case SIOCGMIIREG:
  1203. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1204. break;
  1205. case SIOCSMIIREG:
  1206. if (!capable(CAP_NET_ADMIN))
  1207. return -EPERM;
  1208. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1209. break;
  1210. default:
  1211. return -EOPNOTSUPP;
  1212. }
  1213. return 0;
  1214. }
  1215. #define EEP_READ 0x0200
  1216. #define EEP_BUSY 0x8000
  1217. /* Read the EEPROM word */
  1218. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1219. static int read_eeprom(struct netdev_private *np, int eep_addr)
  1220. {
  1221. void __iomem *ioaddr = np->eeprom_addr;
  1222. int i = 1000;
  1223. dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
  1224. while (i-- > 0) {
  1225. if (!(dr16(EepromCtrl) & EEP_BUSY))
  1226. return dr16(EepromData);
  1227. }
  1228. return 0;
  1229. }
  1230. enum phy_ctrl_bits {
  1231. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1232. MII_DUPLEX = 0x08,
  1233. };
  1234. #define mii_delay() dr8(PhyCtrl)
  1235. static void
  1236. mii_sendbit (struct net_device *dev, u32 data)
  1237. {
  1238. struct netdev_private *np = netdev_priv(dev);
  1239. void __iomem *ioaddr = np->ioaddr;
  1240. data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
  1241. dw8(PhyCtrl, data);
  1242. mii_delay ();
  1243. dw8(PhyCtrl, data | MII_CLK);
  1244. mii_delay ();
  1245. }
  1246. static int
  1247. mii_getbit (struct net_device *dev)
  1248. {
  1249. struct netdev_private *np = netdev_priv(dev);
  1250. void __iomem *ioaddr = np->ioaddr;
  1251. u8 data;
  1252. data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
  1253. dw8(PhyCtrl, data);
  1254. mii_delay ();
  1255. dw8(PhyCtrl, data | MII_CLK);
  1256. mii_delay ();
  1257. return (dr8(PhyCtrl) >> 1) & 1;
  1258. }
  1259. static void
  1260. mii_send_bits (struct net_device *dev, u32 data, int len)
  1261. {
  1262. int i;
  1263. for (i = len - 1; i >= 0; i--) {
  1264. mii_sendbit (dev, data & (1 << i));
  1265. }
  1266. }
  1267. static int
  1268. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1269. {
  1270. u32 cmd;
  1271. int i;
  1272. u32 retval = 0;
  1273. /* Preamble */
  1274. mii_send_bits (dev, 0xffffffff, 32);
  1275. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1276. /* ST,OP = 0110'b for read operation */
  1277. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1278. mii_send_bits (dev, cmd, 14);
  1279. /* Turnaround */
  1280. if (mii_getbit (dev))
  1281. goto err_out;
  1282. /* Read data */
  1283. for (i = 0; i < 16; i++) {
  1284. retval |= mii_getbit (dev);
  1285. retval <<= 1;
  1286. }
  1287. /* End cycle */
  1288. mii_getbit (dev);
  1289. return (retval >> 1) & 0xffff;
  1290. err_out:
  1291. return 0;
  1292. }
  1293. static int
  1294. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1295. {
  1296. u32 cmd;
  1297. /* Preamble */
  1298. mii_send_bits (dev, 0xffffffff, 32);
  1299. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1300. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1301. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1302. mii_send_bits (dev, cmd, 32);
  1303. /* End cycle */
  1304. mii_getbit (dev);
  1305. return 0;
  1306. }
  1307. static int
  1308. mii_wait_link (struct net_device *dev, int wait)
  1309. {
  1310. __u16 bmsr;
  1311. int phy_addr;
  1312. struct netdev_private *np;
  1313. np = netdev_priv(dev);
  1314. phy_addr = np->phy_addr;
  1315. do {
  1316. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1317. if (bmsr & BMSR_LSTATUS)
  1318. return 0;
  1319. mdelay (1);
  1320. } while (--wait > 0);
  1321. return -1;
  1322. }
  1323. static int
  1324. mii_get_media (struct net_device *dev)
  1325. {
  1326. __u16 negotiate;
  1327. __u16 bmsr;
  1328. __u16 mscr;
  1329. __u16 mssr;
  1330. int phy_addr;
  1331. struct netdev_private *np;
  1332. np = netdev_priv(dev);
  1333. phy_addr = np->phy_addr;
  1334. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1335. if (np->an_enable) {
  1336. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1337. /* Auto-Negotiation not completed */
  1338. return -1;
  1339. }
  1340. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1341. mii_read (dev, phy_addr, MII_LPA);
  1342. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1343. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1344. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1345. np->speed = 1000;
  1346. np->full_duplex = 1;
  1347. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1348. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1349. np->speed = 1000;
  1350. np->full_duplex = 0;
  1351. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1352. } else if (negotiate & ADVERTISE_100FULL) {
  1353. np->speed = 100;
  1354. np->full_duplex = 1;
  1355. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1356. } else if (negotiate & ADVERTISE_100HALF) {
  1357. np->speed = 100;
  1358. np->full_duplex = 0;
  1359. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1360. } else if (negotiate & ADVERTISE_10FULL) {
  1361. np->speed = 10;
  1362. np->full_duplex = 1;
  1363. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1364. } else if (negotiate & ADVERTISE_10HALF) {
  1365. np->speed = 10;
  1366. np->full_duplex = 0;
  1367. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1368. }
  1369. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1370. np->tx_flow &= 1;
  1371. np->rx_flow &= 1;
  1372. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1373. np->tx_flow = 0;
  1374. np->rx_flow &= 1;
  1375. }
  1376. /* else tx_flow, rx_flow = user select */
  1377. } else {
  1378. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1379. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1380. case BMCR_SPEED1000:
  1381. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1382. break;
  1383. case BMCR_SPEED100:
  1384. printk (KERN_INFO "Operating at 100 Mbps, ");
  1385. break;
  1386. case 0:
  1387. printk (KERN_INFO "Operating at 10 Mbps, ");
  1388. }
  1389. if (bmcr & BMCR_FULLDPLX) {
  1390. printk (KERN_CONT "Full duplex\n");
  1391. } else {
  1392. printk (KERN_CONT "Half duplex\n");
  1393. }
  1394. }
  1395. if (np->tx_flow)
  1396. printk(KERN_INFO "Enable Tx Flow Control\n");
  1397. else
  1398. printk(KERN_INFO "Disable Tx Flow Control\n");
  1399. if (np->rx_flow)
  1400. printk(KERN_INFO "Enable Rx Flow Control\n");
  1401. else
  1402. printk(KERN_INFO "Disable Rx Flow Control\n");
  1403. return 0;
  1404. }
  1405. static int
  1406. mii_set_media (struct net_device *dev)
  1407. {
  1408. __u16 pscr;
  1409. __u16 bmcr;
  1410. __u16 bmsr;
  1411. __u16 anar;
  1412. int phy_addr;
  1413. struct netdev_private *np;
  1414. np = netdev_priv(dev);
  1415. phy_addr = np->phy_addr;
  1416. /* Does user set speed? */
  1417. if (np->an_enable) {
  1418. /* Advertise capabilities */
  1419. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1420. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1421. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1422. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1423. ADVERTISE_100BASE4);
  1424. if (bmsr & BMSR_100FULL)
  1425. anar |= ADVERTISE_100FULL;
  1426. if (bmsr & BMSR_100HALF)
  1427. anar |= ADVERTISE_100HALF;
  1428. if (bmsr & BMSR_100BASE4)
  1429. anar |= ADVERTISE_100BASE4;
  1430. if (bmsr & BMSR_10FULL)
  1431. anar |= ADVERTISE_10FULL;
  1432. if (bmsr & BMSR_10HALF)
  1433. anar |= ADVERTISE_10HALF;
  1434. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1435. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1436. /* Enable Auto crossover */
  1437. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1438. pscr |= 3 << 5; /* 11'b */
  1439. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1440. /* Soft reset PHY */
  1441. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1442. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1443. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1444. mdelay(1);
  1445. } else {
  1446. /* Force speed setting */
  1447. /* 1) Disable Auto crossover */
  1448. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1449. pscr &= ~(3 << 5);
  1450. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1451. /* 2) PHY Reset */
  1452. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1453. bmcr |= BMCR_RESET;
  1454. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1455. /* 3) Power Down */
  1456. bmcr = 0x1940; /* must be 0x1940 */
  1457. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1458. mdelay (100); /* wait a certain time */
  1459. /* 4) Advertise nothing */
  1460. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1461. /* 5) Set media and Power Up */
  1462. bmcr = BMCR_PDOWN;
  1463. if (np->speed == 100) {
  1464. bmcr |= BMCR_SPEED100;
  1465. printk (KERN_INFO "Manual 100 Mbps, ");
  1466. } else if (np->speed == 10) {
  1467. printk (KERN_INFO "Manual 10 Mbps, ");
  1468. }
  1469. if (np->full_duplex) {
  1470. bmcr |= BMCR_FULLDPLX;
  1471. printk (KERN_CONT "Full duplex\n");
  1472. } else {
  1473. printk (KERN_CONT "Half duplex\n");
  1474. }
  1475. #if 0
  1476. /* Set 1000BaseT Master/Slave setting */
  1477. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1478. mscr |= MII_MSCR_CFG_ENABLE;
  1479. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1480. #endif
  1481. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1482. mdelay(10);
  1483. }
  1484. return 0;
  1485. }
  1486. static int
  1487. mii_get_media_pcs (struct net_device *dev)
  1488. {
  1489. __u16 negotiate;
  1490. __u16 bmsr;
  1491. int phy_addr;
  1492. struct netdev_private *np;
  1493. np = netdev_priv(dev);
  1494. phy_addr = np->phy_addr;
  1495. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1496. if (np->an_enable) {
  1497. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1498. /* Auto-Negotiation not completed */
  1499. return -1;
  1500. }
  1501. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1502. mii_read (dev, phy_addr, PCS_ANLPAR);
  1503. np->speed = 1000;
  1504. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1505. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1506. np->full_duplex = 1;
  1507. } else {
  1508. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1509. np->full_duplex = 0;
  1510. }
  1511. if (negotiate & PCS_ANAR_PAUSE) {
  1512. np->tx_flow &= 1;
  1513. np->rx_flow &= 1;
  1514. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1515. np->tx_flow = 0;
  1516. np->rx_flow &= 1;
  1517. }
  1518. /* else tx_flow, rx_flow = user select */
  1519. } else {
  1520. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1521. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1522. if (bmcr & BMCR_FULLDPLX) {
  1523. printk (KERN_CONT "Full duplex\n");
  1524. } else {
  1525. printk (KERN_CONT "Half duplex\n");
  1526. }
  1527. }
  1528. if (np->tx_flow)
  1529. printk(KERN_INFO "Enable Tx Flow Control\n");
  1530. else
  1531. printk(KERN_INFO "Disable Tx Flow Control\n");
  1532. if (np->rx_flow)
  1533. printk(KERN_INFO "Enable Rx Flow Control\n");
  1534. else
  1535. printk(KERN_INFO "Disable Rx Flow Control\n");
  1536. return 0;
  1537. }
  1538. static int
  1539. mii_set_media_pcs (struct net_device *dev)
  1540. {
  1541. __u16 bmcr;
  1542. __u16 esr;
  1543. __u16 anar;
  1544. int phy_addr;
  1545. struct netdev_private *np;
  1546. np = netdev_priv(dev);
  1547. phy_addr = np->phy_addr;
  1548. /* Auto-Negotiation? */
  1549. if (np->an_enable) {
  1550. /* Advertise capabilities */
  1551. esr = mii_read (dev, phy_addr, PCS_ESR);
  1552. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1553. ~PCS_ANAR_HALF_DUPLEX &
  1554. ~PCS_ANAR_FULL_DUPLEX;
  1555. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1556. anar |= PCS_ANAR_HALF_DUPLEX;
  1557. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1558. anar |= PCS_ANAR_FULL_DUPLEX;
  1559. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1560. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1561. /* Soft reset PHY */
  1562. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1563. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1564. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1565. mdelay(1);
  1566. } else {
  1567. /* Force speed setting */
  1568. /* PHY Reset */
  1569. bmcr = BMCR_RESET;
  1570. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1571. mdelay(10);
  1572. if (np->full_duplex) {
  1573. bmcr = BMCR_FULLDPLX;
  1574. printk (KERN_INFO "Manual full duplex\n");
  1575. } else {
  1576. bmcr = 0;
  1577. printk (KERN_INFO "Manual half duplex\n");
  1578. }
  1579. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1580. mdelay(10);
  1581. /* Advertise nothing */
  1582. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1583. }
  1584. return 0;
  1585. }
  1586. static int
  1587. rio_close (struct net_device *dev)
  1588. {
  1589. struct netdev_private *np = netdev_priv(dev);
  1590. struct pci_dev *pdev = np->pdev;
  1591. netif_stop_queue (dev);
  1592. rio_hw_stop(dev);
  1593. free_irq(pdev->irq, dev);
  1594. del_timer_sync (&np->timer);
  1595. free_list(dev);
  1596. return 0;
  1597. }
  1598. static void
  1599. rio_remove1 (struct pci_dev *pdev)
  1600. {
  1601. struct net_device *dev = pci_get_drvdata (pdev);
  1602. if (dev) {
  1603. struct netdev_private *np = netdev_priv(dev);
  1604. unregister_netdev (dev);
  1605. dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
  1606. np->rx_ring_dma);
  1607. dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
  1608. np->tx_ring_dma);
  1609. #ifdef MEM_MAPPING
  1610. pci_iounmap(pdev, np->ioaddr);
  1611. #endif
  1612. pci_iounmap(pdev, np->eeprom_addr);
  1613. free_netdev (dev);
  1614. pci_release_regions (pdev);
  1615. pci_disable_device (pdev);
  1616. }
  1617. }
  1618. #ifdef CONFIG_PM_SLEEP
  1619. static int rio_suspend(struct device *device)
  1620. {
  1621. struct net_device *dev = dev_get_drvdata(device);
  1622. struct netdev_private *np = netdev_priv(dev);
  1623. if (!netif_running(dev))
  1624. return 0;
  1625. netif_device_detach(dev);
  1626. del_timer_sync(&np->timer);
  1627. rio_hw_stop(dev);
  1628. return 0;
  1629. }
  1630. static int rio_resume(struct device *device)
  1631. {
  1632. struct net_device *dev = dev_get_drvdata(device);
  1633. struct netdev_private *np = netdev_priv(dev);
  1634. if (!netif_running(dev))
  1635. return 0;
  1636. rio_reset_ring(np);
  1637. rio_hw_init(dev);
  1638. np->timer.expires = jiffies + 1 * HZ;
  1639. add_timer(&np->timer);
  1640. netif_device_attach(dev);
  1641. dl2k_enable_int(np);
  1642. return 0;
  1643. }
  1644. static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
  1645. #define RIO_PM_OPS (&rio_pm_ops)
  1646. #else
  1647. #define RIO_PM_OPS NULL
  1648. #endif /* CONFIG_PM_SLEEP */
  1649. static struct pci_driver rio_driver = {
  1650. .name = "dl2k",
  1651. .id_table = rio_pci_tbl,
  1652. .probe = rio_probe1,
  1653. .remove = rio_remove1,
  1654. .driver.pm = RIO_PM_OPS,
  1655. };
  1656. module_pci_driver(rio_driver);
  1657. /* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */