peak_pci.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2007, 2011 Wolfgang Grandegger <[email protected]>
  4. * Copyright (C) 2012 Stephane Grosjean <[email protected]>
  5. *
  6. * Derived from the PCAN project file driver/src/pcan_pci.c:
  7. *
  8. * Copyright (C) 2001-2006 PEAK System-Technik GmbH
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/delay.h>
  15. #include <linux/pci.h>
  16. #include <linux/io.h>
  17. #include <linux/i2c.h>
  18. #include <linux/i2c-algo-bit.h>
  19. #include <linux/can.h>
  20. #include <linux/can/dev.h>
  21. #include "sja1000.h"
  22. MODULE_AUTHOR("Stephane Grosjean <[email protected]>");
  23. MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCI family cards");
  24. MODULE_LICENSE("GPL v2");
  25. #define DRV_NAME "peak_pci"
  26. /* FPGA cards FW version registers */
  27. #define PEAK_VER_REG1 0x40
  28. #define PEAK_VER_REG2 0x44
  29. struct peak_pciec_card;
  30. struct peak_pci_chan {
  31. void __iomem *cfg_base; /* Common for all channels */
  32. struct net_device *prev_dev; /* Chain of network devices */
  33. u16 icr_mask; /* Interrupt mask for fast ack */
  34. struct peak_pciec_card *pciec_card; /* only for PCIeC LEDs */
  35. };
  36. #define PEAK_PCI_CAN_CLOCK (16000000 / 2)
  37. #define PEAK_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
  38. #define PEAK_PCI_OCR OCR_TX0_PUSHPULL
  39. /* Important PITA registers */
  40. #define PITA_ICR 0x00 /* Interrupt control register */
  41. #define PITA_GPIOICR 0x18 /* GPIO interface control register */
  42. #define PITA_MISC 0x1C /* Miscellaneous register */
  43. #define PEAK_PCI_CFG_SIZE 0x1000 /* Size of the config PCI bar */
  44. #define PEAK_PCI_CHAN_SIZE 0x0400 /* Size used by the channel */
  45. #define PEAK_PCI_VENDOR_ID 0x001C /* The PCI device and vendor IDs */
  46. #define PEAK_PCI_DEVICE_ID 0x0001 /* for PCI/PCIe slot cards */
  47. #define PEAK_PCIEC_DEVICE_ID 0x0002 /* for ExpressCard slot cards */
  48. #define PEAK_PCIE_DEVICE_ID 0x0003 /* for nextgen PCIe slot cards */
  49. #define PEAK_CPCI_DEVICE_ID 0x0004 /* for nextgen cPCI slot cards */
  50. #define PEAK_MPCI_DEVICE_ID 0x0005 /* for nextgen miniPCI slot cards */
  51. #define PEAK_PC_104P_DEVICE_ID 0x0006 /* PCAN-PC/104+ cards */
  52. #define PEAK_PCI_104E_DEVICE_ID 0x0007 /* PCAN-PCI/104 Express cards */
  53. #define PEAK_MPCIE_DEVICE_ID 0x0008 /* The miniPCIe slot cards */
  54. #define PEAK_PCIE_OEM_ID 0x0009 /* PCAN-PCI Express OEM */
  55. #define PEAK_PCIEC34_DEVICE_ID 0x000A /* PCAN-PCI Express 34 (one channel) */
  56. #define PEAK_PCI_CHAN_MAX 4
  57. static const u16 peak_pci_icr_masks[PEAK_PCI_CHAN_MAX] = {
  58. 0x02, 0x01, 0x40, 0x80
  59. };
  60. static const struct pci_device_id peak_pci_tbl[] = {
  61. {
  62. PEAK_PCI_VENDOR_ID, PEAK_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  63. .driver_data = (kernel_ulong_t)"PCAN-PCI",
  64. }, {
  65. PEAK_PCI_VENDOR_ID, PEAK_PCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  66. .driver_data = (kernel_ulong_t)"PCAN-PCI Express",
  67. }, {
  68. PEAK_PCI_VENDOR_ID, PEAK_MPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  69. .driver_data = (kernel_ulong_t)"PCAN-miniPCI",
  70. }, {
  71. PEAK_PCI_VENDOR_ID, PEAK_MPCIE_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  72. .driver_data = (kernel_ulong_t)"PCAN-miniPCIe",
  73. }, {
  74. PEAK_PCI_VENDOR_ID, PEAK_PC_104P_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  75. .driver_data = (kernel_ulong_t)"PCAN-PC/104-Plus Quad",
  76. }, {
  77. PEAK_PCI_VENDOR_ID, PEAK_PCI_104E_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  78. .driver_data = (kernel_ulong_t)"PCAN-PCI/104-Express",
  79. }, {
  80. PEAK_PCI_VENDOR_ID, PEAK_CPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  81. .driver_data = (kernel_ulong_t)"PCAN-cPCI",
  82. }, {
  83. PEAK_PCI_VENDOR_ID, PEAK_PCIE_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,
  84. .driver_data = (kernel_ulong_t)"PCAN-Chip PCIe",
  85. },
  86. #ifdef CONFIG_CAN_PEAK_PCIEC
  87. {
  88. PEAK_PCI_VENDOR_ID, PEAK_PCIEC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  89. .driver_data = (kernel_ulong_t)"PCAN-ExpressCard",
  90. }, {
  91. PEAK_PCI_VENDOR_ID, PEAK_PCIEC34_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,
  92. .driver_data = (kernel_ulong_t)"PCAN-ExpressCard 34",
  93. },
  94. #endif
  95. { /* sentinel */ }
  96. };
  97. MODULE_DEVICE_TABLE(pci, peak_pci_tbl);
  98. #ifdef CONFIG_CAN_PEAK_PCIEC
  99. /* PCAN-ExpressCard needs I2C bit-banging configuration option. */
  100. /* GPIOICR byte access offsets */
  101. #define PITA_GPOUT 0x18 /* GPx output value */
  102. #define PITA_GPIN 0x19 /* GPx input value */
  103. #define PITA_GPOEN 0x1A /* configure GPx as output pin */
  104. /* I2C GP bits */
  105. #define PITA_GPIN_SCL 0x01 /* Serial Clock Line */
  106. #define PITA_GPIN_SDA 0x04 /* Serial DAta line */
  107. #define PCA9553_1_SLAVEADDR (0xC4 >> 1)
  108. /* PCA9553 LS0 fields values */
  109. enum {
  110. PCA9553_LOW,
  111. PCA9553_HIGHZ,
  112. PCA9553_PWM0,
  113. PCA9553_PWM1
  114. };
  115. /* LEDs control */
  116. #define PCA9553_ON PCA9553_LOW
  117. #define PCA9553_OFF PCA9553_HIGHZ
  118. #define PCA9553_SLOW PCA9553_PWM0
  119. #define PCA9553_FAST PCA9553_PWM1
  120. #define PCA9553_LED(c) (1 << (c))
  121. #define PCA9553_LED_STATE(s, c) ((s) << ((c) << 1))
  122. #define PCA9553_LED_ON(c) PCA9553_LED_STATE(PCA9553_ON, c)
  123. #define PCA9553_LED_OFF(c) PCA9553_LED_STATE(PCA9553_OFF, c)
  124. #define PCA9553_LED_SLOW(c) PCA9553_LED_STATE(PCA9553_SLOW, c)
  125. #define PCA9553_LED_FAST(c) PCA9553_LED_STATE(PCA9553_FAST, c)
  126. #define PCA9553_LED_MASK(c) PCA9553_LED_STATE(0x03, c)
  127. #define PCA9553_LED_OFF_ALL (PCA9553_LED_OFF(0) | PCA9553_LED_OFF(1))
  128. #define PCA9553_LS0_INIT 0x40 /* initial value (!= from 0x00) */
  129. struct peak_pciec_chan {
  130. struct net_device *netdev;
  131. unsigned long prev_rx_bytes;
  132. unsigned long prev_tx_bytes;
  133. };
  134. struct peak_pciec_card {
  135. void __iomem *cfg_base; /* Common for all channels */
  136. void __iomem *reg_base; /* first channel base address */
  137. u8 led_cache; /* leds state cache */
  138. /* PCIExpressCard i2c data */
  139. struct i2c_algo_bit_data i2c_bit;
  140. struct i2c_adapter led_chip;
  141. struct delayed_work led_work; /* led delayed work */
  142. int chan_count;
  143. struct peak_pciec_chan channel[PEAK_PCI_CHAN_MAX];
  144. };
  145. /* "normal" pci register write callback is overloaded for leds control */
  146. static void peak_pci_write_reg(const struct sja1000_priv *priv,
  147. int port, u8 val);
  148. static inline void pita_set_scl_highz(struct peak_pciec_card *card)
  149. {
  150. u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SCL;
  151. writeb(gp_outen, card->cfg_base + PITA_GPOEN);
  152. }
  153. static inline void pita_set_sda_highz(struct peak_pciec_card *card)
  154. {
  155. u8 gp_outen = readb(card->cfg_base + PITA_GPOEN) & ~PITA_GPIN_SDA;
  156. writeb(gp_outen, card->cfg_base + PITA_GPOEN);
  157. }
  158. static void peak_pciec_init_pita_gpio(struct peak_pciec_card *card)
  159. {
  160. /* raise SCL & SDA GPIOs to high-Z */
  161. pita_set_scl_highz(card);
  162. pita_set_sda_highz(card);
  163. }
  164. static void pita_setsda(void *data, int state)
  165. {
  166. struct peak_pciec_card *card = (struct peak_pciec_card *)data;
  167. u8 gp_out, gp_outen;
  168. /* set output sda always to 0 */
  169. gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SDA;
  170. writeb(gp_out, card->cfg_base + PITA_GPOUT);
  171. /* control output sda with GPOEN */
  172. gp_outen = readb(card->cfg_base + PITA_GPOEN);
  173. if (state)
  174. gp_outen &= ~PITA_GPIN_SDA;
  175. else
  176. gp_outen |= PITA_GPIN_SDA;
  177. writeb(gp_outen, card->cfg_base + PITA_GPOEN);
  178. }
  179. static void pita_setscl(void *data, int state)
  180. {
  181. struct peak_pciec_card *card = (struct peak_pciec_card *)data;
  182. u8 gp_out, gp_outen;
  183. /* set output scl always to 0 */
  184. gp_out = readb(card->cfg_base + PITA_GPOUT) & ~PITA_GPIN_SCL;
  185. writeb(gp_out, card->cfg_base + PITA_GPOUT);
  186. /* control output scl with GPOEN */
  187. gp_outen = readb(card->cfg_base + PITA_GPOEN);
  188. if (state)
  189. gp_outen &= ~PITA_GPIN_SCL;
  190. else
  191. gp_outen |= PITA_GPIN_SCL;
  192. writeb(gp_outen, card->cfg_base + PITA_GPOEN);
  193. }
  194. static int pita_getsda(void *data)
  195. {
  196. struct peak_pciec_card *card = (struct peak_pciec_card *)data;
  197. /* set tristate */
  198. pita_set_sda_highz(card);
  199. return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SDA) ? 1 : 0;
  200. }
  201. static int pita_getscl(void *data)
  202. {
  203. struct peak_pciec_card *card = (struct peak_pciec_card *)data;
  204. /* set tristate */
  205. pita_set_scl_highz(card);
  206. return (readb(card->cfg_base + PITA_GPIN) & PITA_GPIN_SCL) ? 1 : 0;
  207. }
  208. /* write commands to the LED chip though the I2C-bus of the PCAN-PCIeC */
  209. static int peak_pciec_write_pca9553(struct peak_pciec_card *card,
  210. u8 offset, u8 data)
  211. {
  212. u8 buffer[2] = {
  213. offset,
  214. data
  215. };
  216. struct i2c_msg msg = {
  217. .addr = PCA9553_1_SLAVEADDR,
  218. .len = 2,
  219. .buf = buffer,
  220. };
  221. int ret;
  222. /* cache led mask */
  223. if (offset == 5 && data == card->led_cache)
  224. return 0;
  225. ret = i2c_transfer(&card->led_chip, &msg, 1);
  226. if (ret < 0)
  227. return ret;
  228. if (offset == 5)
  229. card->led_cache = data;
  230. return 0;
  231. }
  232. /* delayed work callback used to control the LEDs */
  233. static void peak_pciec_led_work(struct work_struct *work)
  234. {
  235. struct peak_pciec_card *card =
  236. container_of(work, struct peak_pciec_card, led_work.work);
  237. struct net_device *netdev;
  238. u8 new_led = card->led_cache;
  239. int i, up_count = 0;
  240. /* first check what is to do */
  241. for (i = 0; i < card->chan_count; i++) {
  242. /* default is: not configured */
  243. new_led &= ~PCA9553_LED_MASK(i);
  244. new_led |= PCA9553_LED_ON(i);
  245. netdev = card->channel[i].netdev;
  246. if (!netdev || !(netdev->flags & IFF_UP))
  247. continue;
  248. up_count++;
  249. /* no activity (but configured) */
  250. new_led &= ~PCA9553_LED_MASK(i);
  251. new_led |= PCA9553_LED_SLOW(i);
  252. /* if bytes counters changed, set fast blinking led */
  253. if (netdev->stats.rx_bytes != card->channel[i].prev_rx_bytes) {
  254. card->channel[i].prev_rx_bytes = netdev->stats.rx_bytes;
  255. new_led &= ~PCA9553_LED_MASK(i);
  256. new_led |= PCA9553_LED_FAST(i);
  257. }
  258. if (netdev->stats.tx_bytes != card->channel[i].prev_tx_bytes) {
  259. card->channel[i].prev_tx_bytes = netdev->stats.tx_bytes;
  260. new_led &= ~PCA9553_LED_MASK(i);
  261. new_led |= PCA9553_LED_FAST(i);
  262. }
  263. }
  264. /* check if LS0 settings changed, only update i2c if so */
  265. peak_pciec_write_pca9553(card, 5, new_led);
  266. /* restart timer (except if no more configured channels) */
  267. if (up_count)
  268. schedule_delayed_work(&card->led_work, HZ);
  269. }
  270. /* set LEDs blinking state */
  271. static void peak_pciec_set_leds(struct peak_pciec_card *card, u8 led_mask, u8 s)
  272. {
  273. u8 new_led = card->led_cache;
  274. int i;
  275. /* first check what is to do */
  276. for (i = 0; i < card->chan_count; i++)
  277. if (led_mask & PCA9553_LED(i)) {
  278. new_led &= ~PCA9553_LED_MASK(i);
  279. new_led |= PCA9553_LED_STATE(s, i);
  280. }
  281. /* check if LS0 settings changed, only update i2c if so */
  282. peak_pciec_write_pca9553(card, 5, new_led);
  283. }
  284. /* start one second delayed work to control LEDs */
  285. static void peak_pciec_start_led_work(struct peak_pciec_card *card)
  286. {
  287. schedule_delayed_work(&card->led_work, HZ);
  288. }
  289. /* stop LEDs delayed work */
  290. static void peak_pciec_stop_led_work(struct peak_pciec_card *card)
  291. {
  292. cancel_delayed_work_sync(&card->led_work);
  293. }
  294. /* initialize the PCA9553 4-bit I2C-bus LED chip */
  295. static int peak_pciec_init_leds(struct peak_pciec_card *card)
  296. {
  297. int err;
  298. /* prescaler for frequency 0: "SLOW" = 1 Hz = "44" */
  299. err = peak_pciec_write_pca9553(card, 1, 44 / 1);
  300. if (err)
  301. return err;
  302. /* duty cycle 0: 50% */
  303. err = peak_pciec_write_pca9553(card, 2, 0x80);
  304. if (err)
  305. return err;
  306. /* prescaler for frequency 1: "FAST" = 5 Hz */
  307. err = peak_pciec_write_pca9553(card, 3, 44 / 5);
  308. if (err)
  309. return err;
  310. /* duty cycle 1: 50% */
  311. err = peak_pciec_write_pca9553(card, 4, 0x80);
  312. if (err)
  313. return err;
  314. /* switch LEDs to initial state */
  315. return peak_pciec_write_pca9553(card, 5, PCA9553_LS0_INIT);
  316. }
  317. /* restore LEDs state to off peak_pciec_leds_exit */
  318. static void peak_pciec_leds_exit(struct peak_pciec_card *card)
  319. {
  320. /* switch LEDs to off */
  321. peak_pciec_write_pca9553(card, 5, PCA9553_LED_OFF_ALL);
  322. }
  323. /* normal write sja1000 register method overloaded to catch when controller
  324. * is started or stopped, to control leds
  325. */
  326. static void peak_pciec_write_reg(const struct sja1000_priv *priv,
  327. int port, u8 val)
  328. {
  329. struct peak_pci_chan *chan = priv->priv;
  330. struct peak_pciec_card *card = chan->pciec_card;
  331. int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE;
  332. /* sja1000 register changes control the leds state */
  333. if (port == SJA1000_MOD)
  334. switch (val) {
  335. case MOD_RM:
  336. /* Reset Mode: set led on */
  337. peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_ON);
  338. break;
  339. case 0x00:
  340. /* Normal Mode: led slow blinking and start led timer */
  341. peak_pciec_set_leds(card, PCA9553_LED(c), PCA9553_SLOW);
  342. peak_pciec_start_led_work(card);
  343. break;
  344. default:
  345. break;
  346. }
  347. /* call base function */
  348. peak_pci_write_reg(priv, port, val);
  349. }
  350. static const struct i2c_algo_bit_data peak_pciec_i2c_bit_ops = {
  351. .setsda = pita_setsda,
  352. .setscl = pita_setscl,
  353. .getsda = pita_getsda,
  354. .getscl = pita_getscl,
  355. .udelay = 10,
  356. .timeout = HZ,
  357. };
  358. static int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev)
  359. {
  360. struct sja1000_priv *priv = netdev_priv(dev);
  361. struct peak_pci_chan *chan = priv->priv;
  362. struct peak_pciec_card *card;
  363. int err;
  364. /* copy i2c object address from 1st channel */
  365. if (chan->prev_dev) {
  366. struct sja1000_priv *prev_priv = netdev_priv(chan->prev_dev);
  367. struct peak_pci_chan *prev_chan = prev_priv->priv;
  368. card = prev_chan->pciec_card;
  369. if (!card)
  370. return -ENODEV;
  371. /* channel is the first one: do the init part */
  372. } else {
  373. /* create the bit banging I2C adapter structure */
  374. card = kzalloc(sizeof(*card), GFP_KERNEL);
  375. if (!card)
  376. return -ENOMEM;
  377. card->cfg_base = chan->cfg_base;
  378. card->reg_base = priv->reg_base;
  379. card->led_chip.owner = THIS_MODULE;
  380. card->led_chip.dev.parent = &pdev->dev;
  381. card->led_chip.algo_data = &card->i2c_bit;
  382. strncpy(card->led_chip.name, "peak_i2c",
  383. sizeof(card->led_chip.name));
  384. card->i2c_bit = peak_pciec_i2c_bit_ops;
  385. card->i2c_bit.udelay = 10;
  386. card->i2c_bit.timeout = HZ;
  387. card->i2c_bit.data = card;
  388. peak_pciec_init_pita_gpio(card);
  389. err = i2c_bit_add_bus(&card->led_chip);
  390. if (err) {
  391. dev_err(&pdev->dev, "i2c init failed\n");
  392. goto pciec_init_err_1;
  393. }
  394. err = peak_pciec_init_leds(card);
  395. if (err) {
  396. dev_err(&pdev->dev, "leds hardware init failed\n");
  397. goto pciec_init_err_2;
  398. }
  399. INIT_DELAYED_WORK(&card->led_work, peak_pciec_led_work);
  400. /* PCAN-ExpressCard needs its own callback for leds */
  401. priv->write_reg = peak_pciec_write_reg;
  402. }
  403. chan->pciec_card = card;
  404. card->channel[card->chan_count++].netdev = dev;
  405. return 0;
  406. pciec_init_err_2:
  407. i2c_del_adapter(&card->led_chip);
  408. pciec_init_err_1:
  409. peak_pciec_init_pita_gpio(card);
  410. kfree(card);
  411. return err;
  412. }
  413. static void peak_pciec_remove(struct peak_pciec_card *card)
  414. {
  415. peak_pciec_stop_led_work(card);
  416. peak_pciec_leds_exit(card);
  417. i2c_del_adapter(&card->led_chip);
  418. peak_pciec_init_pita_gpio(card);
  419. kfree(card);
  420. }
  421. #else /* CONFIG_CAN_PEAK_PCIEC */
  422. /* Placebo functions when PCAN-ExpressCard support is not selected */
  423. static inline int peak_pciec_probe(struct pci_dev *pdev, struct net_device *dev)
  424. {
  425. return -ENODEV;
  426. }
  427. static inline void peak_pciec_remove(struct peak_pciec_card *card)
  428. {
  429. }
  430. #endif /* CONFIG_CAN_PEAK_PCIEC */
  431. static u8 peak_pci_read_reg(const struct sja1000_priv *priv, int port)
  432. {
  433. return readb(priv->reg_base + (port << 2));
  434. }
  435. static void peak_pci_write_reg(const struct sja1000_priv *priv,
  436. int port, u8 val)
  437. {
  438. writeb(val, priv->reg_base + (port << 2));
  439. }
  440. static void peak_pci_post_irq(const struct sja1000_priv *priv)
  441. {
  442. struct peak_pci_chan *chan = priv->priv;
  443. u16 icr;
  444. /* Select and clear in PITA stored interrupt */
  445. icr = readw(chan->cfg_base + PITA_ICR);
  446. if (icr & chan->icr_mask)
  447. writew(chan->icr_mask, chan->cfg_base + PITA_ICR);
  448. }
  449. static int peak_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  450. {
  451. struct sja1000_priv *priv;
  452. struct peak_pci_chan *chan;
  453. struct net_device *dev, *prev_dev;
  454. void __iomem *cfg_base, *reg_base;
  455. u16 sub_sys_id, icr;
  456. int i, err, channels;
  457. char fw_str[14] = "";
  458. err = pci_enable_device(pdev);
  459. if (err)
  460. return err;
  461. err = pci_request_regions(pdev, DRV_NAME);
  462. if (err)
  463. goto failure_disable_pci;
  464. err = pci_read_config_word(pdev, 0x2e, &sub_sys_id);
  465. if (err)
  466. goto failure_release_regions;
  467. dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n",
  468. pdev->vendor, pdev->device, sub_sys_id);
  469. err = pci_write_config_word(pdev, 0x44, 0);
  470. if (err)
  471. goto failure_release_regions;
  472. if (sub_sys_id >= 12)
  473. channels = 4;
  474. else if (sub_sys_id >= 10)
  475. channels = 3;
  476. else if (sub_sys_id >= 4)
  477. channels = 2;
  478. else
  479. channels = 1;
  480. cfg_base = pci_iomap(pdev, 0, PEAK_PCI_CFG_SIZE);
  481. if (!cfg_base) {
  482. dev_err(&pdev->dev, "failed to map PCI resource #0\n");
  483. err = -ENOMEM;
  484. goto failure_release_regions;
  485. }
  486. reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels);
  487. if (!reg_base) {
  488. dev_err(&pdev->dev, "failed to map PCI resource #1\n");
  489. err = -ENOMEM;
  490. goto failure_unmap_cfg_base;
  491. }
  492. /* Set GPIO control register */
  493. writew(0x0005, cfg_base + PITA_GPIOICR + 2);
  494. /* Enable all channels of this card */
  495. writeb(0x00, cfg_base + PITA_GPIOICR);
  496. /* Toggle reset */
  497. writeb(0x05, cfg_base + PITA_MISC + 3);
  498. usleep_range(5000, 6000);
  499. /* Leave parport mux mode */
  500. writeb(0x04, cfg_base + PITA_MISC + 3);
  501. /* FPGA equipped card if not 0 */
  502. if (readl(cfg_base + PEAK_VER_REG1)) {
  503. /* FPGA card: display version of the running firmware */
  504. u32 fw_ver = readl(cfg_base + PEAK_VER_REG2);
  505. snprintf(fw_str, sizeof(fw_str), " FW v%u.%u.%u",
  506. (fw_ver >> 12) & 0xf,
  507. (fw_ver >> 8) & 0xf,
  508. (fw_ver >> 4) & 0xf);
  509. }
  510. /* Display commercial name (and, eventually, FW version) of the card */
  511. dev_info(&pdev->dev, "%ux CAN %s%s\n",
  512. channels, (const char *)ent->driver_data, fw_str);
  513. icr = readw(cfg_base + PITA_ICR + 2);
  514. for (i = 0; i < channels; i++) {
  515. dev = alloc_sja1000dev(sizeof(struct peak_pci_chan));
  516. if (!dev) {
  517. err = -ENOMEM;
  518. goto failure_remove_channels;
  519. }
  520. priv = netdev_priv(dev);
  521. chan = priv->priv;
  522. chan->cfg_base = cfg_base;
  523. priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE;
  524. priv->read_reg = peak_pci_read_reg;
  525. priv->write_reg = peak_pci_write_reg;
  526. priv->post_irq = peak_pci_post_irq;
  527. priv->can.clock.freq = PEAK_PCI_CAN_CLOCK;
  528. priv->ocr = PEAK_PCI_OCR;
  529. priv->cdr = PEAK_PCI_CDR;
  530. /* Neither a slave nor a single device distributes the clock */
  531. if (channels == 1 || i > 0)
  532. priv->cdr |= CDR_CLK_OFF;
  533. /* Setup interrupt handling */
  534. priv->irq_flags = IRQF_SHARED;
  535. dev->irq = pdev->irq;
  536. chan->icr_mask = peak_pci_icr_masks[i];
  537. icr |= chan->icr_mask;
  538. SET_NETDEV_DEV(dev, &pdev->dev);
  539. dev->dev_id = i;
  540. /* Create chain of SJA1000 devices */
  541. chan->prev_dev = pci_get_drvdata(pdev);
  542. pci_set_drvdata(pdev, dev);
  543. /* PCAN-ExpressCard needs some additional i2c init.
  544. * This must be done *before* register_sja1000dev() but
  545. * *after* devices linkage
  546. */
  547. if (pdev->device == PEAK_PCIEC_DEVICE_ID ||
  548. pdev->device == PEAK_PCIEC34_DEVICE_ID) {
  549. err = peak_pciec_probe(pdev, dev);
  550. if (err) {
  551. dev_err(&pdev->dev,
  552. "failed to probe device (err %d)\n",
  553. err);
  554. goto failure_free_dev;
  555. }
  556. }
  557. err = register_sja1000dev(dev);
  558. if (err) {
  559. dev_err(&pdev->dev, "failed to register device\n");
  560. goto failure_free_dev;
  561. }
  562. dev_info(&pdev->dev,
  563. "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n",
  564. dev->name, priv->reg_base, chan->cfg_base, dev->irq);
  565. }
  566. /* Enable interrupts */
  567. writew(icr, cfg_base + PITA_ICR + 2);
  568. return 0;
  569. failure_free_dev:
  570. pci_set_drvdata(pdev, chan->prev_dev);
  571. free_sja1000dev(dev);
  572. failure_remove_channels:
  573. /* Disable interrupts */
  574. writew(0x0, cfg_base + PITA_ICR + 2);
  575. chan = NULL;
  576. for (dev = pci_get_drvdata(pdev); dev; dev = prev_dev) {
  577. priv = netdev_priv(dev);
  578. chan = priv->priv;
  579. prev_dev = chan->prev_dev;
  580. unregister_sja1000dev(dev);
  581. free_sja1000dev(dev);
  582. }
  583. /* free any PCIeC resources too */
  584. if (chan && chan->pciec_card)
  585. peak_pciec_remove(chan->pciec_card);
  586. pci_iounmap(pdev, reg_base);
  587. failure_unmap_cfg_base:
  588. pci_iounmap(pdev, cfg_base);
  589. failure_release_regions:
  590. pci_release_regions(pdev);
  591. failure_disable_pci:
  592. pci_disable_device(pdev);
  593. /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while
  594. * the probe() function must return a negative errno in case of failure
  595. * (err is unchanged if negative)
  596. */
  597. return pcibios_err_to_errno(err);
  598. }
  599. static void peak_pci_remove(struct pci_dev *pdev)
  600. {
  601. struct net_device *dev = pci_get_drvdata(pdev); /* Last device */
  602. struct sja1000_priv *priv = netdev_priv(dev);
  603. struct peak_pci_chan *chan = priv->priv;
  604. void __iomem *cfg_base = chan->cfg_base;
  605. void __iomem *reg_base = priv->reg_base;
  606. /* Disable interrupts */
  607. writew(0x0, cfg_base + PITA_ICR + 2);
  608. /* Loop over all registered devices */
  609. while (1) {
  610. struct net_device *prev_dev = chan->prev_dev;
  611. dev_info(&pdev->dev, "removing device %s\n", dev->name);
  612. /* do that only for first channel */
  613. if (!prev_dev && chan->pciec_card)
  614. peak_pciec_remove(chan->pciec_card);
  615. unregister_sja1000dev(dev);
  616. free_sja1000dev(dev);
  617. dev = prev_dev;
  618. if (!dev)
  619. break;
  620. priv = netdev_priv(dev);
  621. chan = priv->priv;
  622. }
  623. pci_iounmap(pdev, reg_base);
  624. pci_iounmap(pdev, cfg_base);
  625. pci_release_regions(pdev);
  626. pci_disable_device(pdev);
  627. }
  628. static struct pci_driver peak_pci_driver = {
  629. .name = DRV_NAME,
  630. .id_table = peak_pci_tbl,
  631. .probe = peak_pci_probe,
  632. .remove = peak_pci_remove,
  633. };
  634. module_pci_driver(peak_pci_driver);