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- /* SPDX-License-Identifier: GPL-2.0-or-later */
- /*******************************************************************************
- *
- * CTU CAN FD IP Core
- *
- * Copyright (C) 2015-2018 Ondrej Ille <[email protected]> FEE CTU
- * Copyright (C) 2018-2021 Ondrej Ille <[email protected]> self-funded
- * Copyright (C) 2018-2019 Martin Jerabek <[email protected]> FEE CTU
- * Copyright (C) 2018-2021 Pavel Pisa <[email protected]> FEE CTU/self-funded
- *
- * Project advisors:
- * Jiri Novak <[email protected]>
- * Pavel Pisa <[email protected]>
- *
- * Department of Measurement (http://meas.fel.cvut.cz/)
- * Faculty of Electrical Engineering (http://www.fel.cvut.cz)
- * Czech Technical University (http://www.cvut.cz/)
- ******************************************************************************/
- /* This file is autogenerated, DO NOT EDIT! */
- #ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
- #define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
- #include <linux/bits.h>
- /* CAN_Frame_format memory map */
- enum ctu_can_fd_can_frame_format {
- CTUCANFD_FRAME_FORMAT_W = 0x0,
- CTUCANFD_IDENTIFIER_W = 0x4,
- CTUCANFD_TIMESTAMP_L_W = 0x8,
- CTUCANFD_TIMESTAMP_U_W = 0xc,
- CTUCANFD_DATA_1_4_W = 0x10,
- CTUCANFD_DATA_5_8_W = 0x14,
- CTUCANFD_DATA_61_64_W = 0x4c,
- };
- /* CAN_FD_Frame_format memory region */
- /* FRAME_FORMAT_W registers */
- #define REG_FRAME_FORMAT_W_DLC GENMASK(3, 0)
- #define REG_FRAME_FORMAT_W_RTR BIT(5)
- #define REG_FRAME_FORMAT_W_IDE BIT(6)
- #define REG_FRAME_FORMAT_W_FDF BIT(7)
- #define REG_FRAME_FORMAT_W_BRS BIT(9)
- #define REG_FRAME_FORMAT_W_ESI_RSV BIT(10)
- #define REG_FRAME_FORMAT_W_RWCNT GENMASK(15, 11)
- /* IDENTIFIER_W registers */
- #define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK(17, 0)
- #define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK(28, 18)
- /* TIMESTAMP_L_W registers */
- #define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK(31, 0)
- /* TIMESTAMP_U_W registers */
- #define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK(31, 0)
- /* DATA_1_4_W registers */
- #define REG_DATA_1_4_W_DATA_1 GENMASK(7, 0)
- #define REG_DATA_1_4_W_DATA_2 GENMASK(15, 8)
- #define REG_DATA_1_4_W_DATA_3 GENMASK(23, 16)
- #define REG_DATA_1_4_W_DATA_4 GENMASK(31, 24)
- /* DATA_5_8_W registers */
- #define REG_DATA_5_8_W_DATA_5 GENMASK(7, 0)
- #define REG_DATA_5_8_W_DATA_6 GENMASK(15, 8)
- #define REG_DATA_5_8_W_DATA_7 GENMASK(23, 16)
- #define REG_DATA_5_8_W_DATA_8 GENMASK(31, 24)
- /* DATA_61_64_W registers */
- #define REG_DATA_61_64_W_DATA_61 GENMASK(7, 0)
- #define REG_DATA_61_64_W_DATA_62 GENMASK(15, 8)
- #define REG_DATA_61_64_W_DATA_63 GENMASK(23, 16)
- #define REG_DATA_61_64_W_DATA_64 GENMASK(31, 24)
- #endif
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