denali_dt.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NAND Flash Controller Device Driver for DT
  4. *
  5. * Copyright © 2011, Picochip.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/ioport.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/reset.h>
  18. #include "denali.h"
  19. struct denali_dt {
  20. struct denali_controller controller;
  21. struct clk *clk; /* core clock */
  22. struct clk *clk_x; /* bus interface clock */
  23. struct clk *clk_ecc; /* ECC circuit clock */
  24. struct reset_control *rst; /* core reset */
  25. struct reset_control *rst_reg; /* register reset */
  26. };
  27. struct denali_dt_data {
  28. unsigned int revision;
  29. unsigned int caps;
  30. unsigned int oob_skip_bytes;
  31. const struct nand_ecc_caps *ecc_caps;
  32. };
  33. NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
  34. 512, 8, 15);
  35. static const struct denali_dt_data denali_socfpga_data = {
  36. .caps = DENALI_CAP_HW_ECC_FIXUP,
  37. .oob_skip_bytes = 2,
  38. .ecc_caps = &denali_socfpga_ecc_caps,
  39. };
  40. NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
  41. 1024, 8, 16, 24);
  42. static const struct denali_dt_data denali_uniphier_v5a_data = {
  43. .caps = DENALI_CAP_HW_ECC_FIXUP |
  44. DENALI_CAP_DMA_64BIT,
  45. .oob_skip_bytes = 8,
  46. .ecc_caps = &denali_uniphier_v5a_ecc_caps,
  47. };
  48. NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
  49. 1024, 8, 16);
  50. static const struct denali_dt_data denali_uniphier_v5b_data = {
  51. .revision = 0x0501,
  52. .caps = DENALI_CAP_HW_ECC_FIXUP |
  53. DENALI_CAP_DMA_64BIT,
  54. .oob_skip_bytes = 8,
  55. .ecc_caps = &denali_uniphier_v5b_ecc_caps,
  56. };
  57. static const struct of_device_id denali_nand_dt_ids[] = {
  58. {
  59. .compatible = "altr,socfpga-denali-nand",
  60. .data = &denali_socfpga_data,
  61. },
  62. {
  63. .compatible = "socionext,uniphier-denali-nand-v5a",
  64. .data = &denali_uniphier_v5a_data,
  65. },
  66. {
  67. .compatible = "socionext,uniphier-denali-nand-v5b",
  68. .data = &denali_uniphier_v5b_data,
  69. },
  70. { /* sentinel */ }
  71. };
  72. MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
  73. static int denali_dt_chip_init(struct denali_controller *denali,
  74. struct device_node *chip_np)
  75. {
  76. struct denali_chip *dchip;
  77. u32 bank;
  78. int nsels, i, ret;
  79. nsels = of_property_count_u32_elems(chip_np, "reg");
  80. if (nsels < 0)
  81. return nsels;
  82. dchip = devm_kzalloc(denali->dev, struct_size(dchip, sels, nsels),
  83. GFP_KERNEL);
  84. if (!dchip)
  85. return -ENOMEM;
  86. dchip->nsels = nsels;
  87. for (i = 0; i < nsels; i++) {
  88. ret = of_property_read_u32_index(chip_np, "reg", i, &bank);
  89. if (ret)
  90. return ret;
  91. dchip->sels[i].bank = bank;
  92. nand_set_flash_node(&dchip->chip, chip_np);
  93. }
  94. return denali_chip_init(denali, dchip);
  95. }
  96. static int denali_dt_probe(struct platform_device *pdev)
  97. {
  98. struct device *dev = &pdev->dev;
  99. struct denali_dt *dt;
  100. const struct denali_dt_data *data;
  101. struct denali_controller *denali;
  102. struct device_node *np;
  103. int ret;
  104. dt = devm_kzalloc(dev, sizeof(*dt), GFP_KERNEL);
  105. if (!dt)
  106. return -ENOMEM;
  107. denali = &dt->controller;
  108. data = of_device_get_match_data(dev);
  109. if (WARN_ON(!data))
  110. return -EINVAL;
  111. denali->revision = data->revision;
  112. denali->caps = data->caps;
  113. denali->oob_skip_bytes = data->oob_skip_bytes;
  114. denali->ecc_caps = data->ecc_caps;
  115. denali->dev = dev;
  116. denali->irq = platform_get_irq(pdev, 0);
  117. if (denali->irq < 0)
  118. return denali->irq;
  119. denali->reg = devm_platform_ioremap_resource_byname(pdev, "denali_reg");
  120. if (IS_ERR(denali->reg))
  121. return PTR_ERR(denali->reg);
  122. denali->host = devm_platform_ioremap_resource_byname(pdev, "nand_data");
  123. if (IS_ERR(denali->host))
  124. return PTR_ERR(denali->host);
  125. dt->clk = devm_clk_get(dev, "nand");
  126. if (IS_ERR(dt->clk))
  127. return PTR_ERR(dt->clk);
  128. dt->clk_x = devm_clk_get(dev, "nand_x");
  129. if (IS_ERR(dt->clk_x))
  130. return PTR_ERR(dt->clk_x);
  131. dt->clk_ecc = devm_clk_get(dev, "ecc");
  132. if (IS_ERR(dt->clk_ecc))
  133. return PTR_ERR(dt->clk_ecc);
  134. dt->rst = devm_reset_control_get_optional_shared(dev, "nand");
  135. if (IS_ERR(dt->rst))
  136. return PTR_ERR(dt->rst);
  137. dt->rst_reg = devm_reset_control_get_optional_shared(dev, "reg");
  138. if (IS_ERR(dt->rst_reg))
  139. return PTR_ERR(dt->rst_reg);
  140. ret = clk_prepare_enable(dt->clk);
  141. if (ret)
  142. return ret;
  143. ret = clk_prepare_enable(dt->clk_x);
  144. if (ret)
  145. goto out_disable_clk;
  146. ret = clk_prepare_enable(dt->clk_ecc);
  147. if (ret)
  148. goto out_disable_clk_x;
  149. denali->clk_rate = clk_get_rate(dt->clk);
  150. denali->clk_x_rate = clk_get_rate(dt->clk_x);
  151. /*
  152. * Deassert the register reset, and the core reset in this order.
  153. * Deasserting the core reset while the register reset is asserted
  154. * will cause unpredictable behavior in the controller.
  155. */
  156. ret = reset_control_deassert(dt->rst_reg);
  157. if (ret)
  158. goto out_disable_clk_ecc;
  159. ret = reset_control_deassert(dt->rst);
  160. if (ret)
  161. goto out_assert_rst_reg;
  162. /*
  163. * When the reset is deasserted, the initialization sequence is kicked
  164. * (bootstrap process). The driver must wait until it finished.
  165. * Otherwise, it will result in unpredictable behavior.
  166. */
  167. usleep_range(200, 1000);
  168. ret = denali_init(denali);
  169. if (ret)
  170. goto out_assert_rst;
  171. for_each_child_of_node(dev->of_node, np) {
  172. ret = denali_dt_chip_init(denali, np);
  173. if (ret) {
  174. of_node_put(np);
  175. goto out_remove_denali;
  176. }
  177. }
  178. platform_set_drvdata(pdev, dt);
  179. return 0;
  180. out_remove_denali:
  181. denali_remove(denali);
  182. out_assert_rst:
  183. reset_control_assert(dt->rst);
  184. out_assert_rst_reg:
  185. reset_control_assert(dt->rst_reg);
  186. out_disable_clk_ecc:
  187. clk_disable_unprepare(dt->clk_ecc);
  188. out_disable_clk_x:
  189. clk_disable_unprepare(dt->clk_x);
  190. out_disable_clk:
  191. clk_disable_unprepare(dt->clk);
  192. return ret;
  193. }
  194. static int denali_dt_remove(struct platform_device *pdev)
  195. {
  196. struct denali_dt *dt = platform_get_drvdata(pdev);
  197. denali_remove(&dt->controller);
  198. reset_control_assert(dt->rst);
  199. reset_control_assert(dt->rst_reg);
  200. clk_disable_unprepare(dt->clk_ecc);
  201. clk_disable_unprepare(dt->clk_x);
  202. clk_disable_unprepare(dt->clk);
  203. return 0;
  204. }
  205. static struct platform_driver denali_dt_driver = {
  206. .probe = denali_dt_probe,
  207. .remove = denali_dt_remove,
  208. .driver = {
  209. .name = "denali-nand-dt",
  210. .of_match_table = denali_nand_dt_ids,
  211. },
  212. };
  213. module_platform_driver(denali_dt_driver);
  214. MODULE_LICENSE("GPL v2");
  215. MODULE_AUTHOR("Jamie Iles");
  216. MODULE_DESCRIPTION("DT driver for Denali NAND controller");