Kconfig 8.3 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menu "RAM/ROM/Flash chip drivers"
  3. depends on MTD!=n
  4. config MTD_CFI
  5. tristate "Detect flash chips by Common Flash Interface (CFI) probe"
  6. select MTD_GEN_PROBE
  7. select MTD_CFI_UTIL
  8. help
  9. The Common Flash Interface specification was developed by Intel,
  10. AMD and other flash manufactures that provides a universal method
  11. for probing the capabilities of flash devices. If you wish to
  12. support any device that is CFI-compliant, you need to enable this
  13. option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
  14. for more information on CFI.
  15. config MTD_JEDECPROBE
  16. tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
  17. select MTD_GEN_PROBE
  18. select MTD_CFI_UTIL
  19. help
  20. This option enables JEDEC-style probing of flash chips which are not
  21. compatible with the Common Flash Interface, but will use the common
  22. CFI-targeted flash drivers for any chips which are identified which
  23. are in fact compatible in all but the probe method. This actually
  24. covers most AMD/Fujitsu-compatible chips and also non-CFI
  25. Intel chips.
  26. config MTD_GEN_PROBE
  27. tristate
  28. config MTD_CFI_ADV_OPTIONS
  29. bool "Flash chip driver advanced configuration options"
  30. depends on MTD_GEN_PROBE
  31. help
  32. If you need to specify a specific endianness for access to flash
  33. chips, or if you wish to reduce the size of the kernel by including
  34. support for only specific arrangements of flash chips, say 'Y'. This
  35. option does not directly affect the code, but will enable other
  36. configuration options which allow you to do so.
  37. If unsure, say 'N'.
  38. choice
  39. prompt "Flash cmd/query data swapping"
  40. depends on MTD_CFI_ADV_OPTIONS
  41. default MTD_CFI_NOSWAP
  42. help
  43. This option defines the way in which the CPU attempts to arrange
  44. data bits when writing the 'magic' commands to the chips. Saying
  45. 'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
  46. enabled, means that the CPU will not do any swapping; the chips
  47. are expected to be wired to the CPU in 'host-endian' form.
  48. Specific arrangements are possible with the BIG_ENDIAN_BYTE and
  49. LITTLE_ENDIAN_BYTE, if the bytes are reversed.
  50. config MTD_CFI_NOSWAP
  51. depends on !ARCH_IXP4XX || CPU_BIG_ENDIAN
  52. bool "NO"
  53. config MTD_CFI_BE_BYTE_SWAP
  54. bool "BIG_ENDIAN_BYTE"
  55. config MTD_CFI_LE_BYTE_SWAP
  56. depends on !ARCH_IXP4XX
  57. bool "LITTLE_ENDIAN_BYTE"
  58. endchoice
  59. config MTD_CFI_GEOMETRY
  60. bool "Specific CFI Flash geometry selection"
  61. depends on MTD_CFI_ADV_OPTIONS
  62. select MTD_MAP_BANK_WIDTH_1 if !(MTD_MAP_BANK_WIDTH_2 || \
  63. MTD_MAP_BANK_WIDTH_4 || MTD_MAP_BANK_WIDTH_8 || \
  64. MTD_MAP_BANK_WIDTH_16 || MTD_MAP_BANK_WIDTH_32)
  65. select MTD_CFI_I1 if !(MTD_CFI_I2 || MTD_CFI_I4 || MTD_CFI_I8)
  66. help
  67. This option does not affect the code directly, but will enable
  68. some other configuration options which would allow you to reduce
  69. the size of the kernel by including support for only certain
  70. arrangements of CFI chips. If unsure, say 'N' and all options
  71. which are supported by the current code will be enabled.
  72. config MTD_MAP_BANK_WIDTH_1
  73. bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
  74. default y
  75. help
  76. If you wish to support CFI devices on a physical bus which is
  77. 8 bits wide, say 'Y'.
  78. config MTD_MAP_BANK_WIDTH_2
  79. bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
  80. default y
  81. help
  82. If you wish to support CFI devices on a physical bus which is
  83. 16 bits wide, say 'Y'.
  84. config MTD_MAP_BANK_WIDTH_4
  85. bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
  86. default y
  87. help
  88. If you wish to support CFI devices on a physical bus which is
  89. 32 bits wide, say 'Y'.
  90. config MTD_MAP_BANK_WIDTH_8
  91. bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
  92. default n
  93. help
  94. If you wish to support CFI devices on a physical bus which is
  95. 64 bits wide, say 'Y'.
  96. config MTD_MAP_BANK_WIDTH_16
  97. bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
  98. default n
  99. help
  100. If you wish to support CFI devices on a physical bus which is
  101. 128 bits wide, say 'Y'.
  102. config MTD_MAP_BANK_WIDTH_32
  103. bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
  104. select MTD_COMPLEX_MAPPINGS if HAS_IOMEM
  105. default n
  106. help
  107. If you wish to support CFI devices on a physical bus which is
  108. 256 bits wide, say 'Y'.
  109. config MTD_CFI_I1
  110. bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
  111. default y
  112. help
  113. If your flash chips are not interleaved - i.e. you only have one
  114. flash chip addressed by each bus cycle, then say 'Y'.
  115. config MTD_CFI_I2
  116. bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
  117. default y
  118. help
  119. If your flash chips are interleaved in pairs - i.e. you have two
  120. flash chips addressed by each bus cycle, then say 'Y'.
  121. config MTD_CFI_I4
  122. bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
  123. default n
  124. help
  125. If your flash chips are interleaved in fours - i.e. you have four
  126. flash chips addressed by each bus cycle, then say 'Y'.
  127. config MTD_CFI_I8
  128. bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
  129. default n
  130. help
  131. If your flash chips are interleaved in eights - i.e. you have eight
  132. flash chips addressed by each bus cycle, then say 'Y'.
  133. config MTD_OTP
  134. bool "Protection Registers aka one-time programmable (OTP) bits"
  135. depends on MTD_CFI_ADV_OPTIONS
  136. default n
  137. help
  138. This enables support for reading, writing and locking so called
  139. "Protection Registers" present on some flash chips.
  140. A subset of them are pre-programmed at the factory with a
  141. unique set of values. The rest is user-programmable.
  142. The user-programmable Protection Registers contain one-time
  143. programmable (OTP) bits; when programmed, register bits cannot be
  144. erased. Each Protection Register can be accessed multiple times to
  145. program individual bits, as long as the register remains unlocked.
  146. Each Protection Register has an associated Lock Register bit. When a
  147. Lock Register bit is programmed, the associated Protection Register
  148. can only be read; it can no longer be programmed. Additionally,
  149. because the Lock Register bits themselves are OTP, when programmed,
  150. Lock Register bits cannot be erased. Therefore, when a Protection
  151. Register is locked, it cannot be unlocked.
  152. This feature should therefore be used with extreme care. Any mistake
  153. in the programming of OTP bits will waste them.
  154. config MTD_CFI_INTELEXT
  155. tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
  156. depends on MTD_GEN_PROBE
  157. select MTD_CFI_UTIL
  158. help
  159. The Common Flash Interface defines a number of different command
  160. sets which a CFI-compliant chip may claim to implement. This code
  161. provides support for command set 0001, used on Intel StrataFlash
  162. and other parts.
  163. config MTD_CFI_AMDSTD
  164. tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
  165. depends on MTD_GEN_PROBE
  166. select MTD_CFI_UTIL
  167. help
  168. The Common Flash Interface defines a number of different command
  169. sets which a CFI-compliant chip may claim to implement. This code
  170. provides support for command set 0002, used on chips including
  171. the AMD Am29LV320.
  172. config MTD_CFI_STAA
  173. tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
  174. depends on MTD_GEN_PROBE
  175. select MTD_CFI_UTIL
  176. help
  177. The Common Flash Interface defines a number of different command
  178. sets which a CFI-compliant chip may claim to implement. This code
  179. provides support for command set 0020.
  180. config MTD_CFI_UTIL
  181. tristate
  182. config MTD_RAM
  183. tristate "Support for RAM chips in bus mapping"
  184. help
  185. This option enables basic support for RAM chips accessed through
  186. a bus mapping driver.
  187. config MTD_ROM
  188. tristate "Support for ROM chips in bus mapping"
  189. help
  190. This option enables basic support for ROM chips accessed through
  191. a bus mapping driver.
  192. config MTD_ABSENT
  193. tristate "Support for absent chips in bus mapping"
  194. help
  195. This option enables support for a dummy probing driver used to
  196. allocated placeholder MTD devices on systems that have socketed
  197. or removable media. Use of this driver as a fallback chip probe
  198. preserves the expected registration order of MTD device nodes on
  199. the system regardless of media presence. Device nodes created
  200. with this driver will return -ENODEV upon access.
  201. config MTD_XIP
  202. bool "XIP aware MTD support"
  203. depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
  204. default y if XIP_KERNEL
  205. help
  206. This allows MTD support to work with flash memory which is also
  207. used for XIP purposes. If you're not sure what this is all about
  208. then say N.
  209. endmenu