cxl.h 42 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2014 IBM Corp.
  4. */
  5. #ifndef _CXL_H_
  6. #define _CXL_H_
  7. #include <linux/interrupt.h>
  8. #include <linux/semaphore.h>
  9. #include <linux/device.h>
  10. #include <linux/types.h>
  11. #include <linux/cdev.h>
  12. #include <linux/pid.h>
  13. #include <linux/io.h>
  14. #include <linux/pci.h>
  15. #include <linux/fs.h>
  16. #include <asm/cputable.h>
  17. #include <asm/mmu.h>
  18. #include <asm/reg.h>
  19. #include <misc/cxl-base.h>
  20. #include <misc/cxl.h>
  21. #include <uapi/misc/cxl.h>
  22. extern uint cxl_verbose;
  23. struct property;
  24. #define CXL_TIMEOUT 5
  25. /*
  26. * Bump version each time a user API change is made, whether it is
  27. * backwards compatible ot not.
  28. */
  29. #define CXL_API_VERSION 3
  30. #define CXL_API_VERSION_COMPATIBLE 1
  31. /*
  32. * Opaque types to avoid accidentally passing registers for the wrong MMIO
  33. *
  34. * At the end of the day, I'm not married to using typedef here, but it might
  35. * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  36. * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  37. *
  38. * I'm quite happy if these are changed back to #defines before upstreaming, it
  39. * should be little more than a regexp search+replace operation in this file.
  40. */
  41. typedef struct {
  42. const int x;
  43. } cxl_p1_reg_t;
  44. typedef struct {
  45. const int x;
  46. } cxl_p1n_reg_t;
  47. typedef struct {
  48. const int x;
  49. } cxl_p2n_reg_t;
  50. #define cxl_reg_off(reg) \
  51. (reg.x)
  52. /* Memory maps. Ref CXL Appendix A */
  53. /* PSL Privilege 1 Memory Map */
  54. /* Configuration and Control area - CAIA 1&2 */
  55. static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  56. static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  57. static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
  58. static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
  59. static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  60. /* Downloading */
  61. static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
  62. static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
  63. /* PSL Lookaside Buffer Management Area - CAIA 1 */
  64. static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
  65. static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
  66. static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
  67. static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
  68. static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
  69. static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
  70. /* 0x00C0:7EFF Implementation dependent area */
  71. /* PSL registers - CAIA 1 */
  72. static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
  73. static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
  74. static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
  75. static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
  76. static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
  77. static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  78. static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
  79. static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
  80. static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  81. static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
  82. /* PSL registers - CAIA 2 */
  83. static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
  84. static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};
  85. static const cxl_p1_reg_t CXL_XSL9_DBG = {0x0130};
  86. static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};
  87. static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
  88. static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
  89. static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
  90. static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
  91. static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
  92. static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
  93. static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350};
  94. static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
  95. static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
  96. static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
  97. static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
  98. static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
  99. static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
  100. static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
  101. static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
  102. static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590};
  103. /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
  104. /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
  105. /* PSL Slice Privilege 1 Memory Map */
  106. /* Configuration Area - CAIA 1&2 */
  107. static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
  108. static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
  109. static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
  110. static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
  111. static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
  112. static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
  113. /* Memory Management and Lookaside Buffer Management - CAIA 1*/
  114. static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
  115. /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
  116. static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
  117. /* Pointer Area - CAIA 1&2 */
  118. static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
  119. static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
  120. static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
  121. /* Control Area - CAIA 1&2 */
  122. static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
  123. static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
  124. static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
  125. static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
  126. /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
  127. static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
  128. static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
  129. /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
  130. static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
  131. static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
  132. static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
  133. static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
  134. /* PSL Slice Privilege 2 Memory Map */
  135. /* Configuration and Control Area - CAIA 1&2 */
  136. static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
  137. static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
  138. /* Configuration and Control Area - CAIA 1 */
  139. static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
  140. static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
  141. static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
  142. static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
  143. /* Configuration and Control Area - CAIA 1 */
  144. static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
  145. /* Segment Lookaside Buffer Management - CAIA 1 */
  146. static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
  147. static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
  148. static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
  149. /* Interrupt Registers - CAIA 1&2 */
  150. static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
  151. static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
  152. static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
  153. static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
  154. static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
  155. static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
  156. /* AFU Registers - CAIA 1&2 */
  157. static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
  158. static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
  159. /* Work Element Descriptor - CAIA 1&2 */
  160. static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
  161. /* 0x0C0:FFF Implementation Dependent Area */
  162. #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
  163. #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
  164. #define CXL_PSL_SPAP_Size_Shift 4
  165. #define CXL_PSL_SPAP_V 0x0000000000000001ULL
  166. /****** CXL_PSL_Control ****************************************************/
  167. #define CXL_PSL_Control_tb (0x1ull << (63-63))
  168. #define CXL_PSL_Control_Fr (0x1ull << (63-31))
  169. #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
  170. #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
  171. /****** CXL_PSL_DLCNTL *****************************************************/
  172. #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
  173. #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
  174. #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
  175. #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
  176. #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
  177. #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
  178. /****** CXL_PSL_SR_An ******************************************************/
  179. #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
  180. #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
  181. #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
  182. #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
  183. #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
  184. #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
  185. #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
  186. #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
  187. #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
  188. #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
  189. #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
  190. #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
  191. #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
  192. #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
  193. #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
  194. /****** CXL_PSL_ID_An ****************************************************/
  195. #define CXL_PSL_ID_An_F (1ull << (63-31))
  196. #define CXL_PSL_ID_An_L (1ull << (63-30))
  197. /****** CXL_PSL_SERR_An ****************************************************/
  198. #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
  199. #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
  200. #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
  201. #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
  202. #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
  203. #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
  204. #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
  205. #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
  206. #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
  207. #define CXL_PSL_SERR_An_IRQS ( \
  208. CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
  209. CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
  210. CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
  211. #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
  212. #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
  213. #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
  214. #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
  215. #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
  216. #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
  217. #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
  218. #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
  219. #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
  220. #define CXL_PSL_SERR_An_IRQ_MASKS ( \
  221. CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
  222. CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
  223. CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
  224. #define CXL_PSL_SERR_An_AE (1ull << (63-30))
  225. /****** CXL_PSL_SCNTL_An ****************************************************/
  226. #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
  227. /* Programming Modes: */
  228. #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
  229. #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
  230. #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
  231. #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
  232. #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
  233. #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
  234. /* Purge Status (ro) */
  235. #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
  236. #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
  237. #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
  238. /* Purge */
  239. #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
  240. /* Suspend Status (ro) */
  241. #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
  242. #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
  243. #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
  244. /* Suspend Control */
  245. #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
  246. /* AFU Slice Enable Status (ro) */
  247. #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
  248. #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
  249. #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
  250. /* AFU Slice Enable */
  251. #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
  252. /* AFU Slice Reset status (ro) */
  253. #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
  254. #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
  255. #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
  256. /* AFU Slice Reset */
  257. #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
  258. /****** CXL_SSTP0/1_An ******************************************************/
  259. /* These top bits are for the segment that CONTAINS the segment table */
  260. #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
  261. #define CXL_SSTP0_An_KS (1ull << (63-2))
  262. #define CXL_SSTP0_An_KP (1ull << (63-3))
  263. #define CXL_SSTP0_An_N (1ull << (63-4))
  264. #define CXL_SSTP0_An_L (1ull << (63-5))
  265. #define CXL_SSTP0_An_C (1ull << (63-6))
  266. #define CXL_SSTP0_An_TA (1ull << (63-7))
  267. #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
  268. /* And finally, the virtual address & size of the segment table: */
  269. #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
  270. #define CXL_SSTP0_An_SegTableSize_MASK \
  271. (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
  272. #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
  273. #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
  274. #define CXL_SSTP1_An_V (1ull << (63-63))
  275. /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
  276. /* write: */
  277. #define CXL_SLBIE_C PPC_BIT(36) /* Class */
  278. #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
  279. #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
  280. #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
  281. /* read: */
  282. #define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
  283. #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
  284. /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
  285. #define CXL_TLB_SLB_P (1ull) /* Pending (read) */
  286. /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
  287. #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
  288. #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
  289. #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
  290. /****** CXL_PSL_AFUSEL ******************************************************/
  291. #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
  292. /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
  293. #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
  294. #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
  295. #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
  296. #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
  297. #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
  298. #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
  299. #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
  300. #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
  301. #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
  302. /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
  303. #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
  304. #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
  305. #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
  306. #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
  307. #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
  308. /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
  309. #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
  310. #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
  311. #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
  312. #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
  313. #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
  314. #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
  315. /*
  316. * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
  317. * Status (0:7) Encoding
  318. */
  319. #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
  320. #define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b10000000 */
  321. #define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b10001000 */
  322. #define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b10001100 */
  323. #define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b10010000 */
  324. #define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b10010100 */
  325. #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b10011100 */
  326. #define CXL_PSL9_DSISR_An_URTCH 0x00000000000000B4ULL /* Unsupported Radix Tree Configuration 0b10110100 */
  327. /****** CXL_PSL_TFC_An ******************************************************/
  328. #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
  329. #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
  330. #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
  331. #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
  332. /****** CXL_PSL_DEBUG *****************************************************/
  333. #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
  334. /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
  335. #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
  336. #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
  337. #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
  338. #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
  339. #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
  340. #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
  341. /* cxl_process_element->software_status */
  342. #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
  343. #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
  344. #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
  345. #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
  346. /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
  347. * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
  348. * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
  349. * of the hang pulse frequency.
  350. */
  351. #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
  352. /* SPA->sw_command_status */
  353. #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
  354. #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
  355. #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
  356. #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
  357. #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
  358. #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
  359. #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
  360. #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
  361. #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
  362. #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
  363. #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
  364. #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
  365. #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
  366. #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
  367. #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
  368. #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
  369. #define CXL_MAX_SLICES 4
  370. #define MAX_AFU_MMIO_REGS 3
  371. #define CXL_MODE_TIME_SLICED 0x4
  372. #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
  373. #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
  374. #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
  375. #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
  376. #define CXL_PSL9_TRACEID_MAX 0xAU
  377. #define CXL_PSL9_TRACESTATE_FIN 0x3U
  378. enum cxl_context_status {
  379. CLOSED,
  380. OPENED,
  381. STARTED
  382. };
  383. enum prefault_modes {
  384. CXL_PREFAULT_NONE,
  385. CXL_PREFAULT_WED,
  386. CXL_PREFAULT_ALL,
  387. };
  388. enum cxl_attrs {
  389. CXL_ADAPTER_ATTRS,
  390. CXL_AFU_MASTER_ATTRS,
  391. CXL_AFU_ATTRS,
  392. };
  393. struct cxl_sste {
  394. __be64 esid_data;
  395. __be64 vsid_data;
  396. };
  397. #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
  398. #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
  399. struct cxl_afu_native {
  400. void __iomem *p1n_mmio;
  401. void __iomem *afu_desc_mmio;
  402. irq_hw_number_t psl_hwirq;
  403. unsigned int psl_virq;
  404. struct mutex spa_mutex;
  405. /*
  406. * Only the first part of the SPA is used for the process element
  407. * linked list. The only other part that software needs to worry about
  408. * is sw_command_status, which we store a separate pointer to.
  409. * Everything else in the SPA is only used by hardware
  410. */
  411. struct cxl_process_element *spa;
  412. __be64 *sw_command_status;
  413. unsigned int spa_size;
  414. int spa_order;
  415. int spa_max_procs;
  416. u64 pp_offset;
  417. };
  418. struct cxl_afu_guest {
  419. struct cxl_afu *parent;
  420. u64 handle;
  421. phys_addr_t p2n_phys;
  422. u64 p2n_size;
  423. int max_ints;
  424. bool handle_err;
  425. struct delayed_work work_err;
  426. int previous_state;
  427. };
  428. struct cxl_afu {
  429. struct cxl_afu_native *native;
  430. struct cxl_afu_guest *guest;
  431. irq_hw_number_t serr_hwirq;
  432. unsigned int serr_virq;
  433. char *psl_irq_name;
  434. char *err_irq_name;
  435. void __iomem *p2n_mmio;
  436. phys_addr_t psn_phys;
  437. u64 pp_size;
  438. struct cxl *adapter;
  439. struct device dev;
  440. struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
  441. struct device *chardev_s, *chardev_m, *chardev_d;
  442. struct idr contexts_idr;
  443. struct dentry *debugfs;
  444. struct mutex contexts_lock;
  445. spinlock_t afu_cntl_lock;
  446. /* -1: AFU deconfigured/locked, >= 0: number of readers */
  447. atomic_t configured_state;
  448. /* AFU error buffer fields and bin attribute for sysfs */
  449. u64 eb_len, eb_offset;
  450. struct bin_attribute attr_eb;
  451. /* pointer to the vphb */
  452. struct pci_controller *phb;
  453. int pp_irqs;
  454. int irqs_max;
  455. int num_procs;
  456. int max_procs_virtualised;
  457. int slice;
  458. int modes_supported;
  459. int current_mode;
  460. int crs_num;
  461. u64 crs_len;
  462. u64 crs_offset;
  463. struct list_head crs;
  464. enum prefault_modes prefault_mode;
  465. bool psa;
  466. bool pp_psa;
  467. bool enabled;
  468. };
  469. struct cxl_irq_name {
  470. struct list_head list;
  471. char *name;
  472. };
  473. struct irq_avail {
  474. irq_hw_number_t offset;
  475. irq_hw_number_t range;
  476. unsigned long *bitmap;
  477. };
  478. /*
  479. * This is a cxl context. If the PSL is in dedicated mode, there will be one
  480. * of these per AFU. If in AFU directed there can be lots of these.
  481. */
  482. struct cxl_context {
  483. struct cxl_afu *afu;
  484. /* Problem state MMIO */
  485. phys_addr_t psn_phys;
  486. u64 psn_size;
  487. /* Used to unmap any mmaps when force detaching */
  488. struct address_space *mapping;
  489. struct mutex mapping_lock;
  490. struct page *ff_page;
  491. bool mmio_err_ff;
  492. bool kernelapi;
  493. spinlock_t sste_lock; /* Protects segment table entries */
  494. struct cxl_sste *sstp;
  495. u64 sstp0, sstp1;
  496. unsigned int sst_size, sst_lru;
  497. wait_queue_head_t wq;
  498. /* use mm context associated with this pid for ds faults */
  499. struct pid *pid;
  500. spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
  501. /* Only used in PR mode */
  502. u64 process_token;
  503. /* driver private data */
  504. void *priv;
  505. unsigned long *irq_bitmap; /* Accessed from IRQ context */
  506. struct cxl_irq_ranges irqs;
  507. struct list_head irq_names;
  508. u64 fault_addr;
  509. u64 fault_dsisr;
  510. u64 afu_err;
  511. /*
  512. * This status and it's lock pretects start and detach context
  513. * from racing. It also prevents detach from racing with
  514. * itself
  515. */
  516. enum cxl_context_status status;
  517. struct mutex status_mutex;
  518. /* XXX: Is it possible to need multiple work items at once? */
  519. struct work_struct fault_work;
  520. u64 dsisr;
  521. u64 dar;
  522. struct cxl_process_element *elem;
  523. /*
  524. * pe is the process element handle, assigned by this driver when the
  525. * context is initialized.
  526. *
  527. * external_pe is the PE shown outside of cxl.
  528. * On bare-metal, pe=external_pe, because we decide what the handle is.
  529. * In a guest, we only find out about the pe used by pHyp when the
  530. * context is attached, and that's the value we want to report outside
  531. * of cxl.
  532. */
  533. int pe;
  534. int external_pe;
  535. u32 irq_count;
  536. bool pe_inserted;
  537. bool master;
  538. bool kernel;
  539. bool pending_irq;
  540. bool pending_fault;
  541. bool pending_afu_err;
  542. /* Used by AFU drivers for driver specific event delivery */
  543. struct cxl_afu_driver_ops *afu_driver_ops;
  544. atomic_t afu_driver_events;
  545. struct rcu_head rcu;
  546. struct mm_struct *mm;
  547. u16 tidr;
  548. bool assign_tidr;
  549. };
  550. struct cxl_irq_info;
  551. struct cxl_service_layer_ops {
  552. int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
  553. int (*invalidate_all)(struct cxl *adapter);
  554. int (*afu_regs_init)(struct cxl_afu *afu);
  555. int (*sanitise_afu_regs)(struct cxl_afu *afu);
  556. int (*register_serr_irq)(struct cxl_afu *afu);
  557. void (*release_serr_irq)(struct cxl_afu *afu);
  558. irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
  559. irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
  560. int (*activate_dedicated_process)(struct cxl_afu *afu);
  561. int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
  562. int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
  563. void (*update_dedicated_ivtes)(struct cxl_context *ctx);
  564. void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
  565. void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
  566. void (*psl_irq_dump_registers)(struct cxl_context *ctx);
  567. void (*err_irq_dump_registers)(struct cxl *adapter);
  568. void (*debugfs_stop_trace)(struct cxl *adapter);
  569. void (*write_timebase_ctrl)(struct cxl *adapter);
  570. u64 (*timebase_read)(struct cxl *adapter);
  571. int capi_mode;
  572. bool needs_reset_before_disable;
  573. };
  574. struct cxl_native {
  575. u64 afu_desc_off;
  576. u64 afu_desc_size;
  577. void __iomem *p1_mmio;
  578. void __iomem *p2_mmio;
  579. irq_hw_number_t err_hwirq;
  580. unsigned int err_virq;
  581. u64 ps_off;
  582. bool no_data_cache; /* set if no data cache on the card */
  583. const struct cxl_service_layer_ops *sl_ops;
  584. };
  585. struct cxl_guest {
  586. struct platform_device *pdev;
  587. int irq_nranges;
  588. struct cdev cdev;
  589. irq_hw_number_t irq_base_offset;
  590. struct irq_avail *irq_avail;
  591. spinlock_t irq_alloc_lock;
  592. u64 handle;
  593. char *status;
  594. u16 vendor;
  595. u16 device;
  596. u16 subsystem_vendor;
  597. u16 subsystem;
  598. };
  599. struct cxl {
  600. struct cxl_native *native;
  601. struct cxl_guest *guest;
  602. spinlock_t afu_list_lock;
  603. struct cxl_afu *afu[CXL_MAX_SLICES];
  604. struct device dev;
  605. struct dentry *trace;
  606. struct dentry *psl_err_chk;
  607. struct dentry *debugfs;
  608. char *irq_name;
  609. struct bin_attribute cxl_attr;
  610. int adapter_num;
  611. int user_irqs;
  612. u64 ps_size;
  613. u16 psl_rev;
  614. u16 base_image;
  615. u8 vsec_status;
  616. u8 caia_major;
  617. u8 caia_minor;
  618. u8 slices;
  619. bool user_image_loaded;
  620. bool perst_loads_image;
  621. bool perst_select_user;
  622. bool perst_same_image;
  623. bool psl_timebase_synced;
  624. bool tunneled_ops_supported;
  625. /*
  626. * number of contexts mapped on to this card. Possible values are:
  627. * >0: Number of contexts mapped and new one can be mapped.
  628. * 0: No active contexts and new ones can be mapped.
  629. * -1: No contexts mapped and new ones cannot be mapped.
  630. */
  631. atomic_t contexts_num;
  632. };
  633. int cxl_pci_alloc_one_irq(struct cxl *adapter);
  634. void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
  635. int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
  636. void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
  637. int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
  638. int cxl_update_image_control(struct cxl *adapter);
  639. int cxl_pci_reset(struct cxl *adapter);
  640. void cxl_pci_release_afu(struct device *dev);
  641. ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
  642. /* common == phyp + powernv - CAIA 1&2 */
  643. struct cxl_process_element_common {
  644. __be32 tid;
  645. __be32 pid;
  646. __be64 csrp;
  647. union {
  648. struct {
  649. __be64 aurp0;
  650. __be64 aurp1;
  651. __be64 sstp0;
  652. __be64 sstp1;
  653. } psl8; /* CAIA 1 */
  654. struct {
  655. u8 reserved2[8];
  656. u8 reserved3[8];
  657. u8 reserved4[8];
  658. u8 reserved5[8];
  659. } psl9; /* CAIA 2 */
  660. } u;
  661. __be64 amr;
  662. u8 reserved6[4];
  663. __be64 wed;
  664. } __packed;
  665. /* just powernv - CAIA 1&2 */
  666. struct cxl_process_element {
  667. __be64 sr;
  668. __be64 SPOffset;
  669. union {
  670. __be64 sdr; /* CAIA 1 */
  671. u8 reserved1[8]; /* CAIA 2 */
  672. } u;
  673. __be64 haurp;
  674. __be32 ctxtime;
  675. __be16 ivte_offsets[4];
  676. __be16 ivte_ranges[4];
  677. __be32 lpid;
  678. struct cxl_process_element_common common;
  679. __be32 software_state;
  680. } __packed;
  681. static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
  682. {
  683. struct pci_dev *pdev;
  684. if (cpu_has_feature(CPU_FTR_HVMODE)) {
  685. pdev = to_pci_dev(cxl->dev.parent);
  686. return !pci_channel_offline(pdev);
  687. }
  688. return true;
  689. }
  690. static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
  691. {
  692. WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
  693. return cxl->native->p1_mmio + cxl_reg_off(reg);
  694. }
  695. static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
  696. {
  697. if (likely(cxl_adapter_link_ok(cxl, NULL)))
  698. out_be64(_cxl_p1_addr(cxl, reg), val);
  699. }
  700. static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
  701. {
  702. if (likely(cxl_adapter_link_ok(cxl, NULL)))
  703. return in_be64(_cxl_p1_addr(cxl, reg));
  704. else
  705. return ~0ULL;
  706. }
  707. static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
  708. {
  709. WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
  710. return afu->native->p1n_mmio + cxl_reg_off(reg);
  711. }
  712. static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
  713. {
  714. if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
  715. out_be64(_cxl_p1n_addr(afu, reg), val);
  716. }
  717. static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
  718. {
  719. if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
  720. return in_be64(_cxl_p1n_addr(afu, reg));
  721. else
  722. return ~0ULL;
  723. }
  724. static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
  725. {
  726. return afu->p2n_mmio + cxl_reg_off(reg);
  727. }
  728. static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
  729. {
  730. if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
  731. out_be64(_cxl_p2n_addr(afu, reg), val);
  732. }
  733. static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
  734. {
  735. if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
  736. return in_be64(_cxl_p2n_addr(afu, reg));
  737. else
  738. return ~0ULL;
  739. }
  740. static inline bool cxl_is_power8(void)
  741. {
  742. if ((pvr_version_is(PVR_POWER8E)) ||
  743. (pvr_version_is(PVR_POWER8NVL)) ||
  744. (pvr_version_is(PVR_POWER8)))
  745. return true;
  746. return false;
  747. }
  748. static inline bool cxl_is_power9(void)
  749. {
  750. if (pvr_version_is(PVR_POWER9))
  751. return true;
  752. return false;
  753. }
  754. ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
  755. loff_t off, size_t count);
  756. struct cxl_calls {
  757. void (*cxl_slbia)(struct mm_struct *mm);
  758. struct module *owner;
  759. };
  760. int register_cxl_calls(struct cxl_calls *calls);
  761. void unregister_cxl_calls(struct cxl_calls *calls);
  762. int cxl_update_properties(struct device_node *dn, struct property *new_prop);
  763. void cxl_remove_adapter_nr(struct cxl *adapter);
  764. void cxl_release_spa(struct cxl_afu *afu);
  765. dev_t cxl_get_dev(void);
  766. int cxl_file_init(void);
  767. void cxl_file_exit(void);
  768. int cxl_register_adapter(struct cxl *adapter);
  769. int cxl_register_afu(struct cxl_afu *afu);
  770. int cxl_chardev_d_afu_add(struct cxl_afu *afu);
  771. int cxl_chardev_m_afu_add(struct cxl_afu *afu);
  772. int cxl_chardev_s_afu_add(struct cxl_afu *afu);
  773. void cxl_chardev_afu_remove(struct cxl_afu *afu);
  774. void cxl_context_detach_all(struct cxl_afu *afu);
  775. void cxl_context_free(struct cxl_context *ctx);
  776. void cxl_context_detach(struct cxl_context *ctx);
  777. int cxl_sysfs_adapter_add(struct cxl *adapter);
  778. void cxl_sysfs_adapter_remove(struct cxl *adapter);
  779. int cxl_sysfs_afu_add(struct cxl_afu *afu);
  780. void cxl_sysfs_afu_remove(struct cxl_afu *afu);
  781. int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
  782. void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
  783. struct cxl *cxl_alloc_adapter(void);
  784. struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
  785. int cxl_afu_select_best_mode(struct cxl_afu *afu);
  786. int cxl_native_register_psl_irq(struct cxl_afu *afu);
  787. void cxl_native_release_psl_irq(struct cxl_afu *afu);
  788. int cxl_native_register_psl_err_irq(struct cxl *adapter);
  789. void cxl_native_release_psl_err_irq(struct cxl *adapter);
  790. int cxl_native_register_serr_irq(struct cxl_afu *afu);
  791. void cxl_native_release_serr_irq(struct cxl_afu *afu);
  792. int afu_register_irqs(struct cxl_context *ctx, u32 count);
  793. void afu_release_irqs(struct cxl_context *ctx, void *cookie);
  794. void afu_irq_name_free(struct cxl_context *ctx);
  795. int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
  796. int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
  797. int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
  798. int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
  799. int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
  800. int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
  801. void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
  802. void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
  803. #ifdef CONFIG_DEBUG_FS
  804. void cxl_debugfs_init(void);
  805. void cxl_debugfs_exit(void);
  806. void cxl_debugfs_adapter_add(struct cxl *adapter);
  807. void cxl_debugfs_adapter_remove(struct cxl *adapter);
  808. void cxl_debugfs_afu_add(struct cxl_afu *afu);
  809. void cxl_debugfs_afu_remove(struct cxl_afu *afu);
  810. void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
  811. void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
  812. void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
  813. void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
  814. #else /* CONFIG_DEBUG_FS */
  815. static inline void __init cxl_debugfs_init(void)
  816. {
  817. }
  818. static inline void cxl_debugfs_exit(void)
  819. {
  820. }
  821. static inline void cxl_debugfs_adapter_add(struct cxl *adapter)
  822. {
  823. }
  824. static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
  825. {
  826. }
  827. static inline void cxl_debugfs_afu_add(struct cxl_afu *afu)
  828. {
  829. }
  830. static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
  831. {
  832. }
  833. static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
  834. struct dentry *dir)
  835. {
  836. }
  837. static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
  838. struct dentry *dir)
  839. {
  840. }
  841. static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
  842. {
  843. }
  844. static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
  845. {
  846. }
  847. #endif /* CONFIG_DEBUG_FS */
  848. void cxl_handle_fault(struct work_struct *work);
  849. void cxl_prefault(struct cxl_context *ctx, u64 wed);
  850. int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
  851. struct cxl *get_cxl_adapter(int num);
  852. int cxl_alloc_sst(struct cxl_context *ctx);
  853. void cxl_dump_debug_buffer(void *addr, size_t size);
  854. void init_cxl_native(void);
  855. struct cxl_context *cxl_context_alloc(void);
  856. int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
  857. void cxl_context_set_mapping(struct cxl_context *ctx,
  858. struct address_space *mapping);
  859. void cxl_context_free(struct cxl_context *ctx);
  860. int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
  861. unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
  862. irq_handler_t handler, void *cookie, const char *name);
  863. void cxl_unmap_irq(unsigned int virq, void *cookie);
  864. int __detach_context(struct cxl_context *ctx);
  865. /*
  866. * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
  867. * in PAPR.
  868. * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
  869. * On a guest environment, PSL_PID_An is located on the upper 32 bits and
  870. * PSL_TID_An register in the lower 32 bits.
  871. */
  872. struct cxl_irq_info {
  873. u64 dsisr;
  874. u64 dar;
  875. u64 dsr;
  876. u64 reserved;
  877. u64 afu_err;
  878. u64 errstat;
  879. u64 proc_handle;
  880. u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
  881. };
  882. void cxl_assign_psn_space(struct cxl_context *ctx);
  883. int cxl_invalidate_all_psl9(struct cxl *adapter);
  884. int cxl_invalidate_all_psl8(struct cxl *adapter);
  885. irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
  886. irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
  887. irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
  888. int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
  889. void *cookie, irq_hw_number_t *dest_hwirq,
  890. unsigned int *dest_virq, const char *name);
  891. int cxl_check_error(struct cxl_afu *afu);
  892. int cxl_afu_slbia(struct cxl_afu *afu);
  893. int cxl_data_cache_flush(struct cxl *adapter);
  894. int cxl_afu_disable(struct cxl_afu *afu);
  895. int cxl_psl_purge(struct cxl_afu *afu);
  896. int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
  897. u32 *phb_index, u64 *capp_unit_id);
  898. int cxl_slot_is_switched(struct pci_dev *dev);
  899. int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
  900. u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
  901. void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
  902. void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
  903. void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
  904. void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
  905. int cxl_pci_vphb_add(struct cxl_afu *afu);
  906. void cxl_pci_vphb_remove(struct cxl_afu *afu);
  907. void cxl_release_mapping(struct cxl_context *ctx);
  908. extern struct pci_driver cxl_pci_driver;
  909. extern struct platform_driver cxl_of_driver;
  910. int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
  911. int afu_open(struct inode *inode, struct file *file);
  912. int afu_release(struct inode *inode, struct file *file);
  913. long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
  914. int afu_mmap(struct file *file, struct vm_area_struct *vm);
  915. __poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
  916. ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
  917. extern const struct file_operations afu_fops;
  918. struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
  919. void cxl_guest_remove_adapter(struct cxl *adapter);
  920. int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
  921. int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
  922. ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
  923. ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
  924. int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
  925. void cxl_guest_remove_afu(struct cxl_afu *afu);
  926. int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
  927. int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
  928. int cxl_guest_add_chardev(struct cxl *adapter);
  929. void cxl_guest_remove_chardev(struct cxl *adapter);
  930. void cxl_guest_reload_module(struct cxl *adapter);
  931. int cxl_of_probe(struct platform_device *pdev);
  932. struct cxl_backend_ops {
  933. struct module *module;
  934. int (*adapter_reset)(struct cxl *adapter);
  935. int (*alloc_one_irq)(struct cxl *adapter);
  936. void (*release_one_irq)(struct cxl *adapter, int hwirq);
  937. int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
  938. struct cxl *adapter, unsigned int num);
  939. void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
  940. struct cxl *adapter);
  941. int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
  942. unsigned int virq);
  943. irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
  944. u64 dsisr, u64 errstat);
  945. irqreturn_t (*psl_interrupt)(int irq, void *data);
  946. int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
  947. void (*irq_wait)(struct cxl_context *ctx);
  948. int (*attach_process)(struct cxl_context *ctx, bool kernel,
  949. u64 wed, u64 amr);
  950. int (*detach_process)(struct cxl_context *ctx);
  951. void (*update_ivtes)(struct cxl_context *ctx);
  952. bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
  953. bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
  954. void (*release_afu)(struct device *dev);
  955. ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
  956. loff_t off, size_t count);
  957. int (*afu_check_and_enable)(struct cxl_afu *afu);
  958. int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
  959. int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
  960. int (*afu_reset)(struct cxl_afu *afu);
  961. int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
  962. int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
  963. int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
  964. int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
  965. int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
  966. int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
  967. int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
  968. ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
  969. };
  970. extern const struct cxl_backend_ops cxl_native_ops;
  971. extern const struct cxl_backend_ops cxl_guest_ops;
  972. extern const struct cxl_backend_ops *cxl_ops;
  973. /* check if the given pci_dev is on the cxl vphb bus */
  974. bool cxl_pci_is_vphb_device(struct pci_dev *dev);
  975. /* decode AFU error bits in the PSL register PSL_SERR_An */
  976. void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
  977. /*
  978. * Increments the number of attached contexts on an adapter.
  979. * In case an adapter_context_lock is taken the return -EBUSY.
  980. */
  981. int cxl_adapter_context_get(struct cxl *adapter);
  982. /* Decrements the number of attached contexts on an adapter */
  983. void cxl_adapter_context_put(struct cxl *adapter);
  984. /* If no active contexts then prevents contexts from being attached */
  985. int cxl_adapter_context_lock(struct cxl *adapter);
  986. /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
  987. void cxl_adapter_context_unlock(struct cxl *adapter);
  988. /* Increases the reference count to "struct mm_struct" */
  989. void cxl_context_mm_count_get(struct cxl_context *ctx);
  990. /* Decrements the reference count to "struct mm_struct" */
  991. void cxl_context_mm_count_put(struct cxl_context *ctx);
  992. #endif