tc6393xb.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Toshiba TC6393XB SoC support
  4. *
  5. * Copyright(c) 2005-2006 Chris Humbert
  6. * Copyright(c) 2005 Dirk Opfer
  7. * Copyright(c) 2005 Ian Molton <[email protected]>
  8. * Copyright(c) 2007 Dmitry Baryshkov
  9. *
  10. * Based on code written by Sharp/Lineo for 2.4 kernels
  11. * Based on locomo.c
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/mfd/core.h>
  21. #include <linux/mfd/tmio.h>
  22. #include <linux/mfd/tc6393xb.h>
  23. #include <linux/gpio/driver.h>
  24. #include <linux/gpio/machine.h>
  25. #include <linux/gpio/consumer.h>
  26. #include <linux/slab.h>
  27. #define SCR_REVID 0x08 /* b Revision ID */
  28. #define SCR_ISR 0x50 /* b Interrupt Status */
  29. #define SCR_IMR 0x52 /* b Interrupt Mask */
  30. #define SCR_IRR 0x54 /* b Interrupt Routing */
  31. #define SCR_GPER 0x60 /* w GP Enable */
  32. #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
  33. #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
  34. #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
  35. #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
  36. #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
  37. #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
  38. #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
  39. #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
  40. #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
  41. #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
  42. #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
  43. #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
  44. #define SCR_CCR 0x98 /* w Clock Control */
  45. #define SCR_PLL2CR 0x9a /* w PLL2 Control */
  46. #define SCR_PLL1CR 0x9c /* l PLL1 Control */
  47. #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
  48. #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
  49. #define SCR_FER 0xe0 /* b Function Enable */
  50. #define SCR_MCR 0xe4 /* w Mode Control */
  51. #define SCR_CONFIG 0xfc /* b Configuration Control */
  52. #define SCR_DEBUG 0xff /* b Debug */
  53. #define SCR_CCR_CK32K BIT(0)
  54. #define SCR_CCR_USBCK BIT(1)
  55. #define SCR_CCR_UNK1 BIT(4)
  56. #define SCR_CCR_MCLK_MASK (7 << 8)
  57. #define SCR_CCR_MCLK_OFF (0 << 8)
  58. #define SCR_CCR_MCLK_12 (1 << 8)
  59. #define SCR_CCR_MCLK_24 (2 << 8)
  60. #define SCR_CCR_MCLK_48 (3 << 8)
  61. #define SCR_CCR_HCLK_MASK (3 << 12)
  62. #define SCR_CCR_HCLK_24 (0 << 12)
  63. #define SCR_CCR_HCLK_48 (1 << 12)
  64. #define SCR_FER_USBEN BIT(0) /* USB host enable */
  65. #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
  66. #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
  67. #define SCR_MCR_RDY_MASK (3 << 0)
  68. #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
  69. #define SCR_MCR_RDY_TRISTATE (1 << 0)
  70. #define SCR_MCR_RDY_PUSHPULL (2 << 0)
  71. #define SCR_MCR_RDY_UNK BIT(2)
  72. #define SCR_MCR_RDY_EN BIT(3)
  73. #define SCR_MCR_INT_MASK (3 << 4)
  74. #define SCR_MCR_INT_OPENDRAIN (0 << 4)
  75. #define SCR_MCR_INT_TRISTATE (1 << 4)
  76. #define SCR_MCR_INT_PUSHPULL (2 << 4)
  77. #define SCR_MCR_INT_UNK BIT(6)
  78. #define SCR_MCR_INT_EN BIT(7)
  79. /* bits 8 - 16 are unknown */
  80. #define TC_GPIO_BIT(i) (1 << (i & 0x7))
  81. /*--------------------------------------------------------------------------*/
  82. struct tc6393xb {
  83. void __iomem *scr;
  84. struct device *dev;
  85. struct gpio_chip gpio;
  86. struct gpio_desc *vcc_on;
  87. struct clk *clk; /* 3,6 Mhz */
  88. raw_spinlock_t lock; /* protects RMW cycles */
  89. struct {
  90. u8 fer;
  91. u16 ccr;
  92. u8 gpi_bcr[3];
  93. u8 gpo_dsr[3];
  94. u8 gpo_doecr[3];
  95. } suspend_state;
  96. struct resource rscr;
  97. struct resource *iomem;
  98. int irq;
  99. int irq_base;
  100. };
  101. enum {
  102. TC6393XB_CELL_NAND,
  103. TC6393XB_CELL_MMC,
  104. TC6393XB_CELL_OHCI,
  105. TC6393XB_CELL_FB,
  106. };
  107. /*--------------------------------------------------------------------------*/
  108. static int tc6393xb_nand_enable(struct platform_device *nand)
  109. {
  110. struct tc6393xb *tc6393xb = dev_get_drvdata(nand->dev.parent);
  111. unsigned long flags;
  112. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  113. /* SMD buffer on */
  114. dev_dbg(nand->dev.parent, "SMD buffer on\n");
  115. tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
  116. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  117. return 0;
  118. }
  119. static const struct resource tc6393xb_nand_resources[] = {
  120. {
  121. .start = 0x1000,
  122. .end = 0x1007,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. {
  126. .start = 0x0100,
  127. .end = 0x01ff,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. {
  131. .start = IRQ_TC6393_NAND,
  132. .end = IRQ_TC6393_NAND,
  133. .flags = IORESOURCE_IRQ,
  134. },
  135. };
  136. static const struct resource tc6393xb_mmc_resources[] = {
  137. {
  138. .start = 0x800,
  139. .end = 0x9ff,
  140. .flags = IORESOURCE_MEM,
  141. },
  142. {
  143. .start = IRQ_TC6393_MMC,
  144. .end = IRQ_TC6393_MMC,
  145. .flags = IORESOURCE_IRQ,
  146. },
  147. };
  148. static const struct resource tc6393xb_ohci_resources[] = {
  149. {
  150. .start = 0x3000,
  151. .end = 0x31ff,
  152. .flags = IORESOURCE_MEM,
  153. },
  154. {
  155. .start = 0x0300,
  156. .end = 0x03ff,
  157. .flags = IORESOURCE_MEM,
  158. },
  159. {
  160. .start = 0x010000,
  161. .end = 0x017fff,
  162. .flags = IORESOURCE_MEM,
  163. },
  164. {
  165. .start = 0x018000,
  166. .end = 0x01ffff,
  167. .flags = IORESOURCE_MEM,
  168. },
  169. {
  170. .start = IRQ_TC6393_OHCI,
  171. .end = IRQ_TC6393_OHCI,
  172. .flags = IORESOURCE_IRQ,
  173. },
  174. };
  175. static const struct resource tc6393xb_fb_resources[] = {
  176. {
  177. .start = 0x5000,
  178. .end = 0x51ff,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. {
  182. .start = 0x0500,
  183. .end = 0x05ff,
  184. .flags = IORESOURCE_MEM,
  185. },
  186. {
  187. .start = 0x100000,
  188. .end = 0x1fffff,
  189. .flags = IORESOURCE_MEM,
  190. },
  191. {
  192. .start = IRQ_TC6393_FB,
  193. .end = IRQ_TC6393_FB,
  194. .flags = IORESOURCE_IRQ,
  195. },
  196. };
  197. static int tc6393xb_ohci_enable(struct platform_device *dev)
  198. {
  199. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  200. unsigned long flags;
  201. u16 ccr;
  202. u8 fer;
  203. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  204. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  205. ccr |= SCR_CCR_USBCK;
  206. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  207. fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
  208. fer |= SCR_FER_USBEN;
  209. tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
  210. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  211. return 0;
  212. }
  213. static int tc6393xb_ohci_disable(struct platform_device *dev)
  214. {
  215. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  216. unsigned long flags;
  217. u16 ccr;
  218. u8 fer;
  219. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  220. fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
  221. fer &= ~SCR_FER_USBEN;
  222. tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
  223. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  224. ccr &= ~SCR_CCR_USBCK;
  225. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  226. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  227. return 0;
  228. }
  229. static int tc6393xb_ohci_suspend(struct platform_device *dev)
  230. {
  231. struct tc6393xb_platform_data *tcpd = dev_get_platdata(dev->dev.parent);
  232. /* We can't properly store/restore OHCI state, so fail here */
  233. if (tcpd->resume_restore)
  234. return -EBUSY;
  235. return tc6393xb_ohci_disable(dev);
  236. }
  237. static int tc6393xb_fb_enable(struct platform_device *dev)
  238. {
  239. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  240. unsigned long flags;
  241. u16 ccr;
  242. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  243. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  244. ccr &= ~SCR_CCR_MCLK_MASK;
  245. ccr |= SCR_CCR_MCLK_48;
  246. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  247. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  248. return 0;
  249. }
  250. static int tc6393xb_fb_disable(struct platform_device *dev)
  251. {
  252. struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
  253. unsigned long flags;
  254. u16 ccr;
  255. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  256. ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
  257. ccr &= ~SCR_CCR_MCLK_MASK;
  258. ccr |= SCR_CCR_MCLK_OFF;
  259. tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
  260. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  261. return 0;
  262. }
  263. int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
  264. {
  265. struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
  266. u8 fer;
  267. unsigned long flags;
  268. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  269. fer = ioread8(tc6393xb->scr + SCR_FER);
  270. if (on)
  271. fer |= SCR_FER_SLCDEN;
  272. else
  273. fer &= ~SCR_FER_SLCDEN;
  274. iowrite8(fer, tc6393xb->scr + SCR_FER);
  275. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  276. return 0;
  277. }
  278. EXPORT_SYMBOL(tc6393xb_lcd_set_power);
  279. int tc6393xb_lcd_mode(struct platform_device *fb,
  280. const struct fb_videomode *mode) {
  281. struct tc6393xb *tc6393xb = dev_get_drvdata(fb->dev.parent);
  282. unsigned long flags;
  283. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  284. iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
  285. iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
  286. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  287. return 0;
  288. }
  289. EXPORT_SYMBOL(tc6393xb_lcd_mode);
  290. static int tc6393xb_mmc_enable(struct platform_device *mmc)
  291. {
  292. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  293. tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
  294. tc6393xb_mmc_resources[0].start & 0xfffe);
  295. return 0;
  296. }
  297. static int tc6393xb_mmc_resume(struct platform_device *mmc)
  298. {
  299. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  300. tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
  301. tc6393xb_mmc_resources[0].start & 0xfffe);
  302. return 0;
  303. }
  304. static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
  305. {
  306. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  307. tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
  308. }
  309. static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
  310. {
  311. struct tc6393xb *tc6393xb = dev_get_drvdata(mmc->dev.parent);
  312. tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
  313. }
  314. static struct tmio_mmc_data tc6393xb_mmc_data = {
  315. .hclk = 24000000,
  316. .set_pwr = tc6393xb_mmc_pwr,
  317. .set_clk_div = tc6393xb_mmc_clk_div,
  318. };
  319. static struct mfd_cell tc6393xb_cells[] = {
  320. [TC6393XB_CELL_NAND] = {
  321. .name = "tmio-nand",
  322. .enable = tc6393xb_nand_enable,
  323. .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
  324. .resources = tc6393xb_nand_resources,
  325. },
  326. [TC6393XB_CELL_MMC] = {
  327. .name = "tmio-mmc",
  328. .enable = tc6393xb_mmc_enable,
  329. .resume = tc6393xb_mmc_resume,
  330. .platform_data = &tc6393xb_mmc_data,
  331. .pdata_size = sizeof(tc6393xb_mmc_data),
  332. .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
  333. .resources = tc6393xb_mmc_resources,
  334. },
  335. [TC6393XB_CELL_OHCI] = {
  336. .name = "tmio-ohci",
  337. .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
  338. .resources = tc6393xb_ohci_resources,
  339. .enable = tc6393xb_ohci_enable,
  340. .suspend = tc6393xb_ohci_suspend,
  341. .resume = tc6393xb_ohci_enable,
  342. .disable = tc6393xb_ohci_disable,
  343. },
  344. [TC6393XB_CELL_FB] = {
  345. .name = "tmio-fb",
  346. .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
  347. .resources = tc6393xb_fb_resources,
  348. .enable = tc6393xb_fb_enable,
  349. .suspend = tc6393xb_fb_disable,
  350. .resume = tc6393xb_fb_enable,
  351. .disable = tc6393xb_fb_disable,
  352. },
  353. };
  354. /*--------------------------------------------------------------------------*/
  355. static int tc6393xb_gpio_get(struct gpio_chip *chip,
  356. unsigned offset)
  357. {
  358. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  359. /* XXX: does dsr also represent inputs? */
  360. return !!(tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
  361. & TC_GPIO_BIT(offset));
  362. }
  363. static void __tc6393xb_gpio_set(struct gpio_chip *chip,
  364. unsigned offset, int value)
  365. {
  366. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  367. u8 dsr;
  368. dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
  369. if (value)
  370. dsr |= TC_GPIO_BIT(offset);
  371. else
  372. dsr &= ~TC_GPIO_BIT(offset);
  373. tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
  374. }
  375. static void tc6393xb_gpio_set(struct gpio_chip *chip,
  376. unsigned offset, int value)
  377. {
  378. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  379. unsigned long flags;
  380. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  381. __tc6393xb_gpio_set(chip, offset, value);
  382. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  383. }
  384. static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
  385. unsigned offset)
  386. {
  387. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  388. unsigned long flags;
  389. u8 doecr;
  390. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  391. doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  392. doecr &= ~TC_GPIO_BIT(offset);
  393. tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  394. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  395. return 0;
  396. }
  397. static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
  398. unsigned offset, int value)
  399. {
  400. struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
  401. unsigned long flags;
  402. u8 doecr;
  403. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  404. __tc6393xb_gpio_set(chip, offset, value);
  405. doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  406. doecr |= TC_GPIO_BIT(offset);
  407. tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
  408. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  409. return 0;
  410. }
  411. /*
  412. * TC6393XB GPIOs as used on TOSA, are the only user of this chip.
  413. * GPIOs 2, 5, 8 and 13 are not connected.
  414. */
  415. #define TOSA_GPIO_TG_ON 0
  416. #define TOSA_GPIO_L_MUTE 1
  417. #define TOSA_GPIO_BL_C20MA 3
  418. #define TOSA_GPIO_CARD_VCC_ON 4
  419. #define TOSA_GPIO_CHARGE_OFF 6
  420. #define TOSA_GPIO_CHARGE_OFF_JC 7
  421. #define TOSA_GPIO_BAT0_V_ON 9
  422. #define TOSA_GPIO_BAT1_V_ON 10
  423. #define TOSA_GPIO_BU_CHRG_ON 11
  424. #define TOSA_GPIO_BAT_SW_ON 12
  425. #define TOSA_GPIO_BAT0_TH_ON 14
  426. #define TOSA_GPIO_BAT1_TH_ON 15
  427. GPIO_LOOKUP_SINGLE(tosa_lcd_gpio_lookup, "spi2.0", "tc6393xb",
  428. TOSA_GPIO_TG_ON, "tg #pwr", GPIO_ACTIVE_HIGH);
  429. GPIO_LOOKUP_SINGLE(tosa_lcd_bl_gpio_lookup, "i2c-tos-bl", "tc6393xb",
  430. TOSA_GPIO_BL_C20MA, "backlight", GPIO_ACTIVE_HIGH);
  431. GPIO_LOOKUP_SINGLE(tosa_audio_gpio_lookup, "tosa-audio", "tc6393xb",
  432. TOSA_GPIO_L_MUTE, NULL, GPIO_ACTIVE_HIGH);
  433. static struct gpiod_lookup_table tosa_battery_gpio_lookup = {
  434. .dev_id = "wm97xx-battery",
  435. .table = {
  436. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_CHARGE_OFF,
  437. "main charge off", GPIO_ACTIVE_HIGH),
  438. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_CHARGE_OFF_JC,
  439. "jacket charge off", GPIO_ACTIVE_HIGH),
  440. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_BAT0_V_ON,
  441. "main battery", GPIO_ACTIVE_HIGH),
  442. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_BAT1_V_ON,
  443. "jacket battery", GPIO_ACTIVE_HIGH),
  444. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_BU_CHRG_ON,
  445. "backup battery", GPIO_ACTIVE_HIGH),
  446. /* BAT1 and BAT0 thermistors appear to be swapped */
  447. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_BAT1_TH_ON,
  448. "main battery temp", GPIO_ACTIVE_HIGH),
  449. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_BAT0_TH_ON,
  450. "jacket battery temp", GPIO_ACTIVE_HIGH),
  451. GPIO_LOOKUP("tc6393xb", TOSA_GPIO_BAT_SW_ON,
  452. "battery switch", GPIO_ACTIVE_HIGH),
  453. { },
  454. },
  455. };
  456. static struct gpiod_lookup_table *tc6393xb_gpio_lookups[] = {
  457. &tosa_lcd_gpio_lookup,
  458. &tosa_lcd_bl_gpio_lookup,
  459. &tosa_audio_gpio_lookup,
  460. &tosa_battery_gpio_lookup,
  461. };
  462. static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb)
  463. {
  464. struct gpio_chip *gc = &tc6393xb->gpio;
  465. struct device *dev = tc6393xb->dev;
  466. int ret;
  467. gc->label = "tc6393xb";
  468. gc->base = -1; /* Dynamic allocation */
  469. gc->ngpio = 16;
  470. gc->set = tc6393xb_gpio_set;
  471. gc->get = tc6393xb_gpio_get;
  472. gc->direction_input = tc6393xb_gpio_direction_input;
  473. gc->direction_output = tc6393xb_gpio_direction_output;
  474. ret = devm_gpiochip_add_data(dev, gc, tc6393xb);
  475. if (ret)
  476. return dev_err_probe(dev, ret, "failed to add GPIO chip\n");
  477. /* Register descriptor look-ups for consumers */
  478. gpiod_add_lookup_tables(tc6393xb_gpio_lookups, ARRAY_SIZE(tc6393xb_gpio_lookups));
  479. /* Request some of our own GPIOs */
  480. tc6393xb->vcc_on = gpiochip_request_own_desc(gc, TOSA_GPIO_CARD_VCC_ON, "VCC ON",
  481. GPIO_ACTIVE_HIGH, GPIOD_OUT_HIGH);
  482. if (IS_ERR(tc6393xb->vcc_on))
  483. return dev_err_probe(dev, PTR_ERR(tc6393xb->vcc_on),
  484. "failed to request VCC ON GPIO\n");
  485. return 0;
  486. }
  487. /*--------------------------------------------------------------------------*/
  488. static void tc6393xb_irq(struct irq_desc *desc)
  489. {
  490. struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc);
  491. unsigned int isr;
  492. unsigned int i, irq_base;
  493. irq_base = tc6393xb->irq_base;
  494. while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
  495. ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
  496. for (i = 0; i < TC6393XB_NR_IRQS; i++) {
  497. if (isr & (1 << i))
  498. generic_handle_irq(irq_base + i);
  499. }
  500. }
  501. static void tc6393xb_irq_ack(struct irq_data *data)
  502. {
  503. }
  504. static void tc6393xb_irq_mask(struct irq_data *data)
  505. {
  506. struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
  507. unsigned long flags;
  508. u8 imr;
  509. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  510. imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
  511. imr |= 1 << (data->irq - tc6393xb->irq_base);
  512. tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
  513. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  514. }
  515. static void tc6393xb_irq_unmask(struct irq_data *data)
  516. {
  517. struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
  518. unsigned long flags;
  519. u8 imr;
  520. raw_spin_lock_irqsave(&tc6393xb->lock, flags);
  521. imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
  522. imr &= ~(1 << (data->irq - tc6393xb->irq_base));
  523. tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
  524. raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
  525. }
  526. static struct irq_chip tc6393xb_chip = {
  527. .name = "tc6393xb",
  528. .irq_ack = tc6393xb_irq_ack,
  529. .irq_mask = tc6393xb_irq_mask,
  530. .irq_unmask = tc6393xb_irq_unmask,
  531. };
  532. static void tc6393xb_attach_irq(struct platform_device *dev)
  533. {
  534. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  535. unsigned int irq, irq_base;
  536. irq_base = tc6393xb->irq_base;
  537. for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
  538. irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
  539. irq_set_chip_data(irq, tc6393xb);
  540. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  541. }
  542. irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
  543. irq_set_chained_handler_and_data(tc6393xb->irq, tc6393xb_irq,
  544. tc6393xb);
  545. }
  546. static void tc6393xb_detach_irq(struct platform_device *dev)
  547. {
  548. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  549. unsigned int irq, irq_base;
  550. irq_set_chained_handler_and_data(tc6393xb->irq, NULL, NULL);
  551. irq_base = tc6393xb->irq_base;
  552. for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
  553. irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  554. irq_set_chip(irq, NULL);
  555. irq_set_chip_data(irq, NULL);
  556. }
  557. }
  558. /*--------------------------------------------------------------------------*/
  559. static int tc6393xb_probe(struct platform_device *dev)
  560. {
  561. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  562. struct tc6393xb *tc6393xb;
  563. struct resource *iomem, *rscr;
  564. int ret;
  565. iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
  566. if (!iomem)
  567. return -EINVAL;
  568. tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
  569. if (!tc6393xb) {
  570. ret = -ENOMEM;
  571. goto err_kzalloc;
  572. }
  573. tc6393xb->dev = &dev->dev;
  574. raw_spin_lock_init(&tc6393xb->lock);
  575. platform_set_drvdata(dev, tc6393xb);
  576. ret = platform_get_irq(dev, 0);
  577. if (ret >= 0)
  578. tc6393xb->irq = ret;
  579. else
  580. goto err_noirq;
  581. tc6393xb->iomem = iomem;
  582. tc6393xb->irq_base = tcpd->irq_base;
  583. tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
  584. if (IS_ERR(tc6393xb->clk)) {
  585. ret = PTR_ERR(tc6393xb->clk);
  586. goto err_clk_get;
  587. }
  588. rscr = &tc6393xb->rscr;
  589. rscr->name = "tc6393xb-core";
  590. rscr->start = iomem->start;
  591. rscr->end = iomem->start + 0xff;
  592. rscr->flags = IORESOURCE_MEM;
  593. ret = request_resource(iomem, rscr);
  594. if (ret)
  595. goto err_request_scr;
  596. tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
  597. if (!tc6393xb->scr) {
  598. ret = -ENOMEM;
  599. goto err_ioremap;
  600. }
  601. ret = clk_prepare_enable(tc6393xb->clk);
  602. if (ret)
  603. goto err_clk_enable;
  604. ret = tcpd->enable(dev);
  605. if (ret)
  606. goto err_enable;
  607. iowrite8(0, tc6393xb->scr + SCR_FER);
  608. iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
  609. iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
  610. tc6393xb->scr + SCR_CCR);
  611. iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
  612. SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
  613. BIT(15), tc6393xb->scr + SCR_MCR);
  614. iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
  615. iowrite8(0, tc6393xb->scr + SCR_IRR);
  616. iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
  617. printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
  618. tmio_ioread8(tc6393xb->scr + SCR_REVID),
  619. (unsigned long) iomem->start, tc6393xb->irq);
  620. ret = tc6393xb_register_gpio(tc6393xb);
  621. if (ret)
  622. goto err_gpio_add;
  623. tc6393xb_attach_irq(dev);
  624. tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data;
  625. tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size =
  626. sizeof(*tcpd->nand_data);
  627. tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data;
  628. tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data);
  629. ret = mfd_add_devices(&dev->dev, dev->id,
  630. tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
  631. iomem, tcpd->irq_base, NULL);
  632. if (!ret)
  633. return 0;
  634. tc6393xb_detach_irq(dev);
  635. err_gpio_add:
  636. tcpd->disable(dev);
  637. err_enable:
  638. clk_disable_unprepare(tc6393xb->clk);
  639. err_clk_enable:
  640. iounmap(tc6393xb->scr);
  641. err_ioremap:
  642. release_resource(&tc6393xb->rscr);
  643. err_request_scr:
  644. clk_put(tc6393xb->clk);
  645. err_noirq:
  646. err_clk_get:
  647. kfree(tc6393xb);
  648. err_kzalloc:
  649. return ret;
  650. }
  651. static int tc6393xb_remove(struct platform_device *dev)
  652. {
  653. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  654. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  655. mfd_remove_devices(&dev->dev);
  656. tc6393xb_detach_irq(dev);
  657. tcpd->disable(dev);
  658. clk_disable_unprepare(tc6393xb->clk);
  659. iounmap(tc6393xb->scr);
  660. release_resource(&tc6393xb->rscr);
  661. clk_put(tc6393xb->clk);
  662. kfree(tc6393xb);
  663. return 0;
  664. }
  665. #ifdef CONFIG_PM
  666. static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
  667. {
  668. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  669. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  670. int i, ret;
  671. tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
  672. tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
  673. for (i = 0; i < 3; i++) {
  674. tc6393xb->suspend_state.gpo_dsr[i] =
  675. ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
  676. tc6393xb->suspend_state.gpo_doecr[i] =
  677. ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
  678. tc6393xb->suspend_state.gpi_bcr[i] =
  679. ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
  680. }
  681. ret = tcpd->suspend(dev);
  682. clk_disable_unprepare(tc6393xb->clk);
  683. return ret;
  684. }
  685. static int tc6393xb_resume(struct platform_device *dev)
  686. {
  687. struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
  688. struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
  689. int ret;
  690. int i;
  691. ret = clk_prepare_enable(tc6393xb->clk);
  692. if (ret)
  693. return ret;
  694. ret = tcpd->resume(dev);
  695. if (ret)
  696. return ret;
  697. if (!tcpd->resume_restore)
  698. return 0;
  699. iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
  700. iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
  701. iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
  702. iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
  703. SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
  704. BIT(15), tc6393xb->scr + SCR_MCR);
  705. iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
  706. iowrite8(0, tc6393xb->scr + SCR_IRR);
  707. iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
  708. for (i = 0; i < 3; i++) {
  709. iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
  710. tc6393xb->scr + SCR_GPO_DSR(i));
  711. iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
  712. tc6393xb->scr + SCR_GPO_DOECR(i));
  713. iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
  714. tc6393xb->scr + SCR_GPI_BCR(i));
  715. }
  716. return 0;
  717. }
  718. #else
  719. #define tc6393xb_suspend NULL
  720. #define tc6393xb_resume NULL
  721. #endif
  722. static struct platform_driver tc6393xb_driver = {
  723. .probe = tc6393xb_probe,
  724. .remove = tc6393xb_remove,
  725. .suspend = tc6393xb_suspend,
  726. .resume = tc6393xb_resume,
  727. .driver = {
  728. .name = "tc6393xb",
  729. },
  730. };
  731. static int __init tc6393xb_init(void)
  732. {
  733. return platform_driver_register(&tc6393xb_driver);
  734. }
  735. static void __exit tc6393xb_exit(void)
  736. {
  737. platform_driver_unregister(&tc6393xb_driver);
  738. }
  739. subsys_initcall(tc6393xb_init);
  740. module_exit(tc6393xb_exit);
  741. MODULE_LICENSE("GPL v2");
  742. MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
  743. MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
  744. MODULE_ALIAS("platform:tc6393xb");