stmpe.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ST Microelectronics MFD: stmpe's driver
  4. *
  5. * Copyright (C) ST-Ericsson SA 2010
  6. *
  7. * Author: Rabin Vincent <[email protected]> for ST-Ericsson
  8. */
  9. #include <linux/err.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/export.h>
  12. #include <linux/kernel.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of.h>
  17. #include <linux/pm.h>
  18. #include <linux/slab.h>
  19. #include <linux/mfd/core.h>
  20. #include <linux/delay.h>
  21. #include <linux/regulator/consumer.h>
  22. #include "stmpe.h"
  23. /**
  24. * struct stmpe_platform_data - STMPE platform data
  25. * @id: device id to distinguish between multiple STMPEs on the same board
  26. * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
  27. * @irq_trigger: IRQ trigger to use for the interrupt to the host
  28. * @autosleep: bool to enable/disable stmpe autosleep
  29. * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
  30. */
  31. struct stmpe_platform_data {
  32. int id;
  33. unsigned int blocks;
  34. unsigned int irq_trigger;
  35. bool autosleep;
  36. int autosleep_timeout;
  37. };
  38. static int __stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
  39. {
  40. return stmpe->variant->enable(stmpe, blocks, true);
  41. }
  42. static int __stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
  43. {
  44. return stmpe->variant->enable(stmpe, blocks, false);
  45. }
  46. static int __stmpe_reg_read(struct stmpe *stmpe, u8 reg)
  47. {
  48. int ret;
  49. ret = stmpe->ci->read_byte(stmpe, reg);
  50. if (ret < 0)
  51. dev_err(stmpe->dev, "failed to read reg %#x: %d\n", reg, ret);
  52. dev_vdbg(stmpe->dev, "rd: reg %#x => data %#x\n", reg, ret);
  53. return ret;
  54. }
  55. static int __stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
  56. {
  57. int ret;
  58. dev_vdbg(stmpe->dev, "wr: reg %#x <= %#x\n", reg, val);
  59. ret = stmpe->ci->write_byte(stmpe, reg, val);
  60. if (ret < 0)
  61. dev_err(stmpe->dev, "failed to write reg %#x: %d\n", reg, ret);
  62. return ret;
  63. }
  64. static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
  65. {
  66. int ret;
  67. ret = __stmpe_reg_read(stmpe, reg);
  68. if (ret < 0)
  69. return ret;
  70. ret &= ~mask;
  71. ret |= val;
  72. return __stmpe_reg_write(stmpe, reg, ret);
  73. }
  74. static int __stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
  75. u8 *values)
  76. {
  77. int ret;
  78. ret = stmpe->ci->read_block(stmpe, reg, length, values);
  79. if (ret < 0)
  80. dev_err(stmpe->dev, "failed to read regs %#x: %d\n", reg, ret);
  81. dev_vdbg(stmpe->dev, "rd: reg %#x (%d) => ret %#x\n", reg, length, ret);
  82. stmpe_dump_bytes("stmpe rd: ", values, length);
  83. return ret;
  84. }
  85. static int __stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
  86. const u8 *values)
  87. {
  88. int ret;
  89. dev_vdbg(stmpe->dev, "wr: regs %#x (%d)\n", reg, length);
  90. stmpe_dump_bytes("stmpe wr: ", values, length);
  91. ret = stmpe->ci->write_block(stmpe, reg, length, values);
  92. if (ret < 0)
  93. dev_err(stmpe->dev, "failed to write regs %#x: %d\n", reg, ret);
  94. return ret;
  95. }
  96. /**
  97. * stmpe_enable - enable blocks on an STMPE device
  98. * @stmpe: Device to work on
  99. * @blocks: Mask of blocks (enum stmpe_block values) to enable
  100. */
  101. int stmpe_enable(struct stmpe *stmpe, unsigned int blocks)
  102. {
  103. int ret;
  104. mutex_lock(&stmpe->lock);
  105. ret = __stmpe_enable(stmpe, blocks);
  106. mutex_unlock(&stmpe->lock);
  107. return ret;
  108. }
  109. EXPORT_SYMBOL_GPL(stmpe_enable);
  110. /**
  111. * stmpe_disable - disable blocks on an STMPE device
  112. * @stmpe: Device to work on
  113. * @blocks: Mask of blocks (enum stmpe_block values) to enable
  114. */
  115. int stmpe_disable(struct stmpe *stmpe, unsigned int blocks)
  116. {
  117. int ret;
  118. mutex_lock(&stmpe->lock);
  119. ret = __stmpe_disable(stmpe, blocks);
  120. mutex_unlock(&stmpe->lock);
  121. return ret;
  122. }
  123. EXPORT_SYMBOL_GPL(stmpe_disable);
  124. /**
  125. * stmpe_reg_read() - read a single STMPE register
  126. * @stmpe: Device to read from
  127. * @reg: Register to read
  128. */
  129. int stmpe_reg_read(struct stmpe *stmpe, u8 reg)
  130. {
  131. int ret;
  132. mutex_lock(&stmpe->lock);
  133. ret = __stmpe_reg_read(stmpe, reg);
  134. mutex_unlock(&stmpe->lock);
  135. return ret;
  136. }
  137. EXPORT_SYMBOL_GPL(stmpe_reg_read);
  138. /**
  139. * stmpe_reg_write() - write a single STMPE register
  140. * @stmpe: Device to write to
  141. * @reg: Register to write
  142. * @val: Value to write
  143. */
  144. int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 val)
  145. {
  146. int ret;
  147. mutex_lock(&stmpe->lock);
  148. ret = __stmpe_reg_write(stmpe, reg, val);
  149. mutex_unlock(&stmpe->lock);
  150. return ret;
  151. }
  152. EXPORT_SYMBOL_GPL(stmpe_reg_write);
  153. /**
  154. * stmpe_set_bits() - set the value of a bitfield in a STMPE register
  155. * @stmpe: Device to write to
  156. * @reg: Register to write
  157. * @mask: Mask of bits to set
  158. * @val: Value to set
  159. */
  160. int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val)
  161. {
  162. int ret;
  163. mutex_lock(&stmpe->lock);
  164. ret = __stmpe_set_bits(stmpe, reg, mask, val);
  165. mutex_unlock(&stmpe->lock);
  166. return ret;
  167. }
  168. EXPORT_SYMBOL_GPL(stmpe_set_bits);
  169. /**
  170. * stmpe_block_read() - read multiple STMPE registers
  171. * @stmpe: Device to read from
  172. * @reg: First register
  173. * @length: Number of registers
  174. * @values: Buffer to write to
  175. */
  176. int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, u8 *values)
  177. {
  178. int ret;
  179. mutex_lock(&stmpe->lock);
  180. ret = __stmpe_block_read(stmpe, reg, length, values);
  181. mutex_unlock(&stmpe->lock);
  182. return ret;
  183. }
  184. EXPORT_SYMBOL_GPL(stmpe_block_read);
  185. /**
  186. * stmpe_block_write() - write multiple STMPE registers
  187. * @stmpe: Device to write to
  188. * @reg: First register
  189. * @length: Number of registers
  190. * @values: Values to write
  191. */
  192. int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
  193. const u8 *values)
  194. {
  195. int ret;
  196. mutex_lock(&stmpe->lock);
  197. ret = __stmpe_block_write(stmpe, reg, length, values);
  198. mutex_unlock(&stmpe->lock);
  199. return ret;
  200. }
  201. EXPORT_SYMBOL_GPL(stmpe_block_write);
  202. /**
  203. * stmpe_set_altfunc()- set the alternate function for STMPE pins
  204. * @stmpe: Device to configure
  205. * @pins: Bitmask of pins to affect
  206. * @block: block to enable alternate functions for
  207. *
  208. * @pins is assumed to have a bit set for each of the bits whose alternate
  209. * function is to be changed, numbered according to the GPIOXY numbers.
  210. *
  211. * If the GPIO module is not enabled, this function automatically enables it in
  212. * order to perform the change.
  213. */
  214. int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block)
  215. {
  216. struct stmpe_variant_info *variant = stmpe->variant;
  217. u8 regaddr = stmpe->regs[STMPE_IDX_GPAFR_U_MSB];
  218. int af_bits = variant->af_bits;
  219. int numregs = DIV_ROUND_UP(stmpe->num_gpios * af_bits, 8);
  220. int mask = (1 << af_bits) - 1;
  221. u8 regs[8];
  222. int af, afperreg, ret;
  223. if (!variant->get_altfunc)
  224. return 0;
  225. afperreg = 8 / af_bits;
  226. mutex_lock(&stmpe->lock);
  227. ret = __stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
  228. if (ret < 0)
  229. goto out;
  230. ret = __stmpe_block_read(stmpe, regaddr, numregs, regs);
  231. if (ret < 0)
  232. goto out;
  233. af = variant->get_altfunc(stmpe, block);
  234. while (pins) {
  235. int pin = __ffs(pins);
  236. int regoffset = numregs - (pin / afperreg) - 1;
  237. int pos = (pin % afperreg) * (8 / afperreg);
  238. regs[regoffset] &= ~(mask << pos);
  239. regs[regoffset] |= af << pos;
  240. pins &= ~(1 << pin);
  241. }
  242. ret = __stmpe_block_write(stmpe, regaddr, numregs, regs);
  243. out:
  244. mutex_unlock(&stmpe->lock);
  245. return ret;
  246. }
  247. EXPORT_SYMBOL_GPL(stmpe_set_altfunc);
  248. /*
  249. * GPIO (all variants)
  250. */
  251. static struct resource stmpe_gpio_resources[] = {
  252. /* Start and end filled dynamically */
  253. {
  254. .flags = IORESOURCE_IRQ,
  255. },
  256. };
  257. static const struct mfd_cell stmpe_gpio_cell = {
  258. .name = "stmpe-gpio",
  259. .of_compatible = "st,stmpe-gpio",
  260. .resources = stmpe_gpio_resources,
  261. .num_resources = ARRAY_SIZE(stmpe_gpio_resources),
  262. };
  263. static const struct mfd_cell stmpe_gpio_cell_noirq = {
  264. .name = "stmpe-gpio",
  265. .of_compatible = "st,stmpe-gpio",
  266. /* gpio cell resources consist of an irq only so no resources here */
  267. };
  268. /*
  269. * Keypad (1601, 2401, 2403)
  270. */
  271. static struct resource stmpe_keypad_resources[] = {
  272. /* Start and end filled dynamically */
  273. {
  274. .name = "KEYPAD",
  275. .flags = IORESOURCE_IRQ,
  276. },
  277. {
  278. .name = "KEYPAD_OVER",
  279. .flags = IORESOURCE_IRQ,
  280. },
  281. };
  282. static const struct mfd_cell stmpe_keypad_cell = {
  283. .name = "stmpe-keypad",
  284. .of_compatible = "st,stmpe-keypad",
  285. .resources = stmpe_keypad_resources,
  286. .num_resources = ARRAY_SIZE(stmpe_keypad_resources),
  287. };
  288. /*
  289. * PWM (1601, 2401, 2403)
  290. */
  291. static struct resource stmpe_pwm_resources[] = {
  292. /* Start and end filled dynamically */
  293. {
  294. .name = "PWM0",
  295. .flags = IORESOURCE_IRQ,
  296. },
  297. {
  298. .name = "PWM1",
  299. .flags = IORESOURCE_IRQ,
  300. },
  301. {
  302. .name = "PWM2",
  303. .flags = IORESOURCE_IRQ,
  304. },
  305. };
  306. static const struct mfd_cell stmpe_pwm_cell = {
  307. .name = "stmpe-pwm",
  308. .of_compatible = "st,stmpe-pwm",
  309. .resources = stmpe_pwm_resources,
  310. .num_resources = ARRAY_SIZE(stmpe_pwm_resources),
  311. };
  312. /*
  313. * STMPE801
  314. */
  315. static const u8 stmpe801_regs[] = {
  316. [STMPE_IDX_CHIP_ID] = STMPE801_REG_CHIP_ID,
  317. [STMPE_IDX_ICR_LSB] = STMPE801_REG_SYS_CTRL,
  318. [STMPE_IDX_GPMR_LSB] = STMPE801_REG_GPIO_MP_STA,
  319. [STMPE_IDX_GPSR_LSB] = STMPE801_REG_GPIO_SET_PIN,
  320. [STMPE_IDX_GPCR_LSB] = STMPE801_REG_GPIO_SET_PIN,
  321. [STMPE_IDX_GPDR_LSB] = STMPE801_REG_GPIO_DIR,
  322. [STMPE_IDX_IEGPIOR_LSB] = STMPE801_REG_GPIO_INT_EN,
  323. [STMPE_IDX_ISGPIOR_MSB] = STMPE801_REG_GPIO_INT_STA,
  324. };
  325. static struct stmpe_variant_block stmpe801_blocks[] = {
  326. {
  327. .cell = &stmpe_gpio_cell,
  328. .irq = 0,
  329. .block = STMPE_BLOCK_GPIO,
  330. },
  331. };
  332. static struct stmpe_variant_block stmpe801_blocks_noirq[] = {
  333. {
  334. .cell = &stmpe_gpio_cell_noirq,
  335. .block = STMPE_BLOCK_GPIO,
  336. },
  337. };
  338. static int stmpe801_enable(struct stmpe *stmpe, unsigned int blocks,
  339. bool enable)
  340. {
  341. if (blocks & STMPE_BLOCK_GPIO)
  342. return 0;
  343. else
  344. return -EINVAL;
  345. }
  346. static struct stmpe_variant_info stmpe801 = {
  347. .name = "stmpe801",
  348. .id_val = STMPE801_ID,
  349. .id_mask = 0xffff,
  350. .num_gpios = 8,
  351. .regs = stmpe801_regs,
  352. .blocks = stmpe801_blocks,
  353. .num_blocks = ARRAY_SIZE(stmpe801_blocks),
  354. .num_irqs = STMPE801_NR_INTERNAL_IRQS,
  355. .enable = stmpe801_enable,
  356. };
  357. static struct stmpe_variant_info stmpe801_noirq = {
  358. .name = "stmpe801",
  359. .id_val = STMPE801_ID,
  360. .id_mask = 0xffff,
  361. .num_gpios = 8,
  362. .regs = stmpe801_regs,
  363. .blocks = stmpe801_blocks_noirq,
  364. .num_blocks = ARRAY_SIZE(stmpe801_blocks_noirq),
  365. .enable = stmpe801_enable,
  366. };
  367. /*
  368. * Touchscreen (STMPE811 or STMPE610)
  369. */
  370. static struct resource stmpe_ts_resources[] = {
  371. /* Start and end filled dynamically */
  372. {
  373. .name = "TOUCH_DET",
  374. .flags = IORESOURCE_IRQ,
  375. },
  376. {
  377. .name = "FIFO_TH",
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. };
  381. static const struct mfd_cell stmpe_ts_cell = {
  382. .name = "stmpe-ts",
  383. .of_compatible = "st,stmpe-ts",
  384. .resources = stmpe_ts_resources,
  385. .num_resources = ARRAY_SIZE(stmpe_ts_resources),
  386. };
  387. /*
  388. * ADC (STMPE811)
  389. */
  390. static struct resource stmpe_adc_resources[] = {
  391. /* Start and end filled dynamically */
  392. {
  393. .name = "STMPE_TEMP_SENS",
  394. .flags = IORESOURCE_IRQ,
  395. },
  396. {
  397. .name = "STMPE_ADC",
  398. .flags = IORESOURCE_IRQ,
  399. },
  400. };
  401. static const struct mfd_cell stmpe_adc_cell = {
  402. .name = "stmpe-adc",
  403. .of_compatible = "st,stmpe-adc",
  404. .resources = stmpe_adc_resources,
  405. .num_resources = ARRAY_SIZE(stmpe_adc_resources),
  406. };
  407. /*
  408. * STMPE811 or STMPE610
  409. */
  410. static const u8 stmpe811_regs[] = {
  411. [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID,
  412. [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL,
  413. [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2,
  414. [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL,
  415. [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN,
  416. [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA,
  417. [STMPE_IDX_GPMR_LSB] = STMPE811_REG_GPIO_MP_STA,
  418. [STMPE_IDX_GPSR_LSB] = STMPE811_REG_GPIO_SET_PIN,
  419. [STMPE_IDX_GPCR_LSB] = STMPE811_REG_GPIO_CLR_PIN,
  420. [STMPE_IDX_GPDR_LSB] = STMPE811_REG_GPIO_DIR,
  421. [STMPE_IDX_GPRER_LSB] = STMPE811_REG_GPIO_RE,
  422. [STMPE_IDX_GPFER_LSB] = STMPE811_REG_GPIO_FE,
  423. [STMPE_IDX_GPAFR_U_MSB] = STMPE811_REG_GPIO_AF,
  424. [STMPE_IDX_IEGPIOR_LSB] = STMPE811_REG_GPIO_INT_EN,
  425. [STMPE_IDX_ISGPIOR_MSB] = STMPE811_REG_GPIO_INT_STA,
  426. [STMPE_IDX_GPEDR_LSB] = STMPE811_REG_GPIO_ED,
  427. };
  428. static struct stmpe_variant_block stmpe811_blocks[] = {
  429. {
  430. .cell = &stmpe_gpio_cell,
  431. .irq = STMPE811_IRQ_GPIOC,
  432. .block = STMPE_BLOCK_GPIO,
  433. },
  434. {
  435. .cell = &stmpe_ts_cell,
  436. .irq = STMPE811_IRQ_TOUCH_DET,
  437. .block = STMPE_BLOCK_TOUCHSCREEN,
  438. },
  439. {
  440. .cell = &stmpe_adc_cell,
  441. .irq = STMPE811_IRQ_TEMP_SENS,
  442. .block = STMPE_BLOCK_ADC,
  443. },
  444. };
  445. static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
  446. bool enable)
  447. {
  448. unsigned int mask = 0;
  449. if (blocks & STMPE_BLOCK_GPIO)
  450. mask |= STMPE811_SYS_CTRL2_GPIO_OFF;
  451. if (blocks & STMPE_BLOCK_ADC)
  452. mask |= STMPE811_SYS_CTRL2_ADC_OFF;
  453. if (blocks & STMPE_BLOCK_TOUCHSCREEN)
  454. mask |= STMPE811_SYS_CTRL2_TSC_OFF;
  455. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask,
  456. enable ? 0 : mask);
  457. }
  458. int stmpe811_adc_common_init(struct stmpe *stmpe)
  459. {
  460. int ret;
  461. u8 adc_ctrl1, adc_ctrl1_mask;
  462. adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) |
  463. STMPE_MOD_12B(stmpe->mod_12b) |
  464. STMPE_REF_SEL(stmpe->ref_sel);
  465. adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) |
  466. STMPE_REF_SEL(0xff);
  467. ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1,
  468. adc_ctrl1_mask, adc_ctrl1);
  469. if (ret) {
  470. dev_err(stmpe->dev, "Could not setup ADC\n");
  471. return ret;
  472. }
  473. ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2,
  474. STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq));
  475. if (ret) {
  476. dev_err(stmpe->dev, "Could not setup ADC\n");
  477. return ret;
  478. }
  479. return 0;
  480. }
  481. EXPORT_SYMBOL_GPL(stmpe811_adc_common_init);
  482. static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
  483. {
  484. /* 0 for touchscreen, 1 for GPIO */
  485. return block != STMPE_BLOCK_TOUCHSCREEN;
  486. }
  487. static struct stmpe_variant_info stmpe811 = {
  488. .name = "stmpe811",
  489. .id_val = 0x0811,
  490. .id_mask = 0xffff,
  491. .num_gpios = 8,
  492. .af_bits = 1,
  493. .regs = stmpe811_regs,
  494. .blocks = stmpe811_blocks,
  495. .num_blocks = ARRAY_SIZE(stmpe811_blocks),
  496. .num_irqs = STMPE811_NR_INTERNAL_IRQS,
  497. .enable = stmpe811_enable,
  498. .get_altfunc = stmpe811_get_altfunc,
  499. };
  500. /* Similar to 811, except number of gpios */
  501. static struct stmpe_variant_info stmpe610 = {
  502. .name = "stmpe610",
  503. .id_val = 0x0811,
  504. .id_mask = 0xffff,
  505. .num_gpios = 6,
  506. .af_bits = 1,
  507. .regs = stmpe811_regs,
  508. .blocks = stmpe811_blocks,
  509. .num_blocks = ARRAY_SIZE(stmpe811_blocks),
  510. .num_irqs = STMPE811_NR_INTERNAL_IRQS,
  511. .enable = stmpe811_enable,
  512. .get_altfunc = stmpe811_get_altfunc,
  513. };
  514. /*
  515. * STMPE1600
  516. * Compared to all others STMPE variant, LSB and MSB regs are located in this
  517. * order : LSB addr
  518. * MSB addr + 1
  519. * As there is only 2 * 8bits registers for GPMR/GPSR/IEGPIOPR, CSB index is MSB registers
  520. */
  521. static const u8 stmpe1600_regs[] = {
  522. [STMPE_IDX_CHIP_ID] = STMPE1600_REG_CHIP_ID,
  523. [STMPE_IDX_SYS_CTRL] = STMPE1600_REG_SYS_CTRL,
  524. [STMPE_IDX_ICR_LSB] = STMPE1600_REG_SYS_CTRL,
  525. [STMPE_IDX_GPMR_LSB] = STMPE1600_REG_GPMR_LSB,
  526. [STMPE_IDX_GPMR_CSB] = STMPE1600_REG_GPMR_MSB,
  527. [STMPE_IDX_GPSR_LSB] = STMPE1600_REG_GPSR_LSB,
  528. [STMPE_IDX_GPSR_CSB] = STMPE1600_REG_GPSR_MSB,
  529. [STMPE_IDX_GPCR_LSB] = STMPE1600_REG_GPSR_LSB,
  530. [STMPE_IDX_GPCR_CSB] = STMPE1600_REG_GPSR_MSB,
  531. [STMPE_IDX_GPDR_LSB] = STMPE1600_REG_GPDR_LSB,
  532. [STMPE_IDX_GPDR_CSB] = STMPE1600_REG_GPDR_MSB,
  533. [STMPE_IDX_IEGPIOR_LSB] = STMPE1600_REG_IEGPIOR_LSB,
  534. [STMPE_IDX_IEGPIOR_CSB] = STMPE1600_REG_IEGPIOR_MSB,
  535. [STMPE_IDX_ISGPIOR_LSB] = STMPE1600_REG_ISGPIOR_LSB,
  536. };
  537. static struct stmpe_variant_block stmpe1600_blocks[] = {
  538. {
  539. .cell = &stmpe_gpio_cell,
  540. .irq = 0,
  541. .block = STMPE_BLOCK_GPIO,
  542. },
  543. };
  544. static int stmpe1600_enable(struct stmpe *stmpe, unsigned int blocks,
  545. bool enable)
  546. {
  547. if (blocks & STMPE_BLOCK_GPIO)
  548. return 0;
  549. else
  550. return -EINVAL;
  551. }
  552. static struct stmpe_variant_info stmpe1600 = {
  553. .name = "stmpe1600",
  554. .id_val = STMPE1600_ID,
  555. .id_mask = 0xffff,
  556. .num_gpios = 16,
  557. .af_bits = 0,
  558. .regs = stmpe1600_regs,
  559. .blocks = stmpe1600_blocks,
  560. .num_blocks = ARRAY_SIZE(stmpe1600_blocks),
  561. .num_irqs = STMPE1600_NR_INTERNAL_IRQS,
  562. .enable = stmpe1600_enable,
  563. };
  564. /*
  565. * STMPE1601
  566. */
  567. static const u8 stmpe1601_regs[] = {
  568. [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID,
  569. [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL,
  570. [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2,
  571. [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB,
  572. [STMPE_IDX_IER_MSB] = STMPE1601_REG_IER_MSB,
  573. [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB,
  574. [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB,
  575. [STMPE_IDX_GPMR_LSB] = STMPE1601_REG_GPIO_MP_LSB,
  576. [STMPE_IDX_GPMR_CSB] = STMPE1601_REG_GPIO_MP_MSB,
  577. [STMPE_IDX_GPSR_LSB] = STMPE1601_REG_GPIO_SET_LSB,
  578. [STMPE_IDX_GPSR_CSB] = STMPE1601_REG_GPIO_SET_MSB,
  579. [STMPE_IDX_GPCR_LSB] = STMPE1601_REG_GPIO_CLR_LSB,
  580. [STMPE_IDX_GPCR_CSB] = STMPE1601_REG_GPIO_CLR_MSB,
  581. [STMPE_IDX_GPDR_LSB] = STMPE1601_REG_GPIO_SET_DIR_LSB,
  582. [STMPE_IDX_GPDR_CSB] = STMPE1601_REG_GPIO_SET_DIR_MSB,
  583. [STMPE_IDX_GPEDR_LSB] = STMPE1601_REG_GPIO_ED_LSB,
  584. [STMPE_IDX_GPEDR_CSB] = STMPE1601_REG_GPIO_ED_MSB,
  585. [STMPE_IDX_GPRER_LSB] = STMPE1601_REG_GPIO_RE_LSB,
  586. [STMPE_IDX_GPRER_CSB] = STMPE1601_REG_GPIO_RE_MSB,
  587. [STMPE_IDX_GPFER_LSB] = STMPE1601_REG_GPIO_FE_LSB,
  588. [STMPE_IDX_GPFER_CSB] = STMPE1601_REG_GPIO_FE_MSB,
  589. [STMPE_IDX_GPPUR_LSB] = STMPE1601_REG_GPIO_PU_LSB,
  590. [STMPE_IDX_GPAFR_U_MSB] = STMPE1601_REG_GPIO_AF_U_MSB,
  591. [STMPE_IDX_IEGPIOR_LSB] = STMPE1601_REG_INT_EN_GPIO_MASK_LSB,
  592. [STMPE_IDX_IEGPIOR_CSB] = STMPE1601_REG_INT_EN_GPIO_MASK_MSB,
  593. [STMPE_IDX_ISGPIOR_MSB] = STMPE1601_REG_INT_STA_GPIO_MSB,
  594. };
  595. static struct stmpe_variant_block stmpe1601_blocks[] = {
  596. {
  597. .cell = &stmpe_gpio_cell,
  598. .irq = STMPE1601_IRQ_GPIOC,
  599. .block = STMPE_BLOCK_GPIO,
  600. },
  601. {
  602. .cell = &stmpe_keypad_cell,
  603. .irq = STMPE1601_IRQ_KEYPAD,
  604. .block = STMPE_BLOCK_KEYPAD,
  605. },
  606. {
  607. .cell = &stmpe_pwm_cell,
  608. .irq = STMPE1601_IRQ_PWM0,
  609. .block = STMPE_BLOCK_PWM,
  610. },
  611. };
  612. /* supported autosleep timeout delay (in msecs) */
  613. static const int stmpe_autosleep_delay[] = {
  614. 4, 16, 32, 64, 128, 256, 512, 1024,
  615. };
  616. static int stmpe_round_timeout(int timeout)
  617. {
  618. int i;
  619. for (i = 0; i < ARRAY_SIZE(stmpe_autosleep_delay); i++) {
  620. if (stmpe_autosleep_delay[i] >= timeout)
  621. return i;
  622. }
  623. /*
  624. * requests for delays longer than supported should not return the
  625. * longest supported delay
  626. */
  627. return -EINVAL;
  628. }
  629. static int stmpe_autosleep(struct stmpe *stmpe, int autosleep_timeout)
  630. {
  631. int ret;
  632. if (!stmpe->variant->enable_autosleep)
  633. return -ENOSYS;
  634. mutex_lock(&stmpe->lock);
  635. ret = stmpe->variant->enable_autosleep(stmpe, autosleep_timeout);
  636. mutex_unlock(&stmpe->lock);
  637. return ret;
  638. }
  639. /*
  640. * Both stmpe 1601/2403 support same layout for autosleep
  641. */
  642. static int stmpe1601_autosleep(struct stmpe *stmpe,
  643. int autosleep_timeout)
  644. {
  645. int ret, timeout;
  646. /* choose the best available timeout */
  647. timeout = stmpe_round_timeout(autosleep_timeout);
  648. if (timeout < 0) {
  649. dev_err(stmpe->dev, "invalid timeout\n");
  650. return timeout;
  651. }
  652. ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
  653. STMPE1601_AUTOSLEEP_TIMEOUT_MASK,
  654. timeout);
  655. if (ret < 0)
  656. return ret;
  657. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2],
  658. STPME1601_AUTOSLEEP_ENABLE,
  659. STPME1601_AUTOSLEEP_ENABLE);
  660. }
  661. static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks,
  662. bool enable)
  663. {
  664. unsigned int mask = 0;
  665. if (blocks & STMPE_BLOCK_GPIO)
  666. mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO;
  667. else
  668. mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO;
  669. if (blocks & STMPE_BLOCK_KEYPAD)
  670. mask |= STMPE1601_SYS_CTRL_ENABLE_KPC;
  671. else
  672. mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC;
  673. if (blocks & STMPE_BLOCK_PWM)
  674. mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM;
  675. else
  676. mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM;
  677. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
  678. enable ? mask : 0);
  679. }
  680. static int stmpe1601_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
  681. {
  682. switch (block) {
  683. case STMPE_BLOCK_PWM:
  684. return 2;
  685. case STMPE_BLOCK_KEYPAD:
  686. return 1;
  687. case STMPE_BLOCK_GPIO:
  688. default:
  689. return 0;
  690. }
  691. }
  692. static struct stmpe_variant_info stmpe1601 = {
  693. .name = "stmpe1601",
  694. .id_val = 0x0210,
  695. .id_mask = 0xfff0, /* at least 0x0210 and 0x0212 */
  696. .num_gpios = 16,
  697. .af_bits = 2,
  698. .regs = stmpe1601_regs,
  699. .blocks = stmpe1601_blocks,
  700. .num_blocks = ARRAY_SIZE(stmpe1601_blocks),
  701. .num_irqs = STMPE1601_NR_INTERNAL_IRQS,
  702. .enable = stmpe1601_enable,
  703. .get_altfunc = stmpe1601_get_altfunc,
  704. .enable_autosleep = stmpe1601_autosleep,
  705. };
  706. /*
  707. * STMPE1801
  708. */
  709. static const u8 stmpe1801_regs[] = {
  710. [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID,
  711. [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL,
  712. [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW,
  713. [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW,
  714. [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW,
  715. [STMPE_IDX_GPMR_LSB] = STMPE1801_REG_GPIO_MP_LOW,
  716. [STMPE_IDX_GPMR_CSB] = STMPE1801_REG_GPIO_MP_MID,
  717. [STMPE_IDX_GPMR_MSB] = STMPE1801_REG_GPIO_MP_HIGH,
  718. [STMPE_IDX_GPSR_LSB] = STMPE1801_REG_GPIO_SET_LOW,
  719. [STMPE_IDX_GPSR_CSB] = STMPE1801_REG_GPIO_SET_MID,
  720. [STMPE_IDX_GPSR_MSB] = STMPE1801_REG_GPIO_SET_HIGH,
  721. [STMPE_IDX_GPCR_LSB] = STMPE1801_REG_GPIO_CLR_LOW,
  722. [STMPE_IDX_GPCR_CSB] = STMPE1801_REG_GPIO_CLR_MID,
  723. [STMPE_IDX_GPCR_MSB] = STMPE1801_REG_GPIO_CLR_HIGH,
  724. [STMPE_IDX_GPDR_LSB] = STMPE1801_REG_GPIO_SET_DIR_LOW,
  725. [STMPE_IDX_GPDR_CSB] = STMPE1801_REG_GPIO_SET_DIR_MID,
  726. [STMPE_IDX_GPDR_MSB] = STMPE1801_REG_GPIO_SET_DIR_HIGH,
  727. [STMPE_IDX_GPRER_LSB] = STMPE1801_REG_GPIO_RE_LOW,
  728. [STMPE_IDX_GPRER_CSB] = STMPE1801_REG_GPIO_RE_MID,
  729. [STMPE_IDX_GPRER_MSB] = STMPE1801_REG_GPIO_RE_HIGH,
  730. [STMPE_IDX_GPFER_LSB] = STMPE1801_REG_GPIO_FE_LOW,
  731. [STMPE_IDX_GPFER_CSB] = STMPE1801_REG_GPIO_FE_MID,
  732. [STMPE_IDX_GPFER_MSB] = STMPE1801_REG_GPIO_FE_HIGH,
  733. [STMPE_IDX_GPPUR_LSB] = STMPE1801_REG_GPIO_PULL_UP_LOW,
  734. [STMPE_IDX_IEGPIOR_LSB] = STMPE1801_REG_INT_EN_GPIO_MASK_LOW,
  735. [STMPE_IDX_IEGPIOR_CSB] = STMPE1801_REG_INT_EN_GPIO_MASK_MID,
  736. [STMPE_IDX_IEGPIOR_MSB] = STMPE1801_REG_INT_EN_GPIO_MASK_HIGH,
  737. [STMPE_IDX_ISGPIOR_MSB] = STMPE1801_REG_INT_STA_GPIO_HIGH,
  738. };
  739. static struct stmpe_variant_block stmpe1801_blocks[] = {
  740. {
  741. .cell = &stmpe_gpio_cell,
  742. .irq = STMPE1801_IRQ_GPIOC,
  743. .block = STMPE_BLOCK_GPIO,
  744. },
  745. {
  746. .cell = &stmpe_keypad_cell,
  747. .irq = STMPE1801_IRQ_KEYPAD,
  748. .block = STMPE_BLOCK_KEYPAD,
  749. },
  750. };
  751. static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
  752. bool enable)
  753. {
  754. unsigned int mask = 0;
  755. if (blocks & STMPE_BLOCK_GPIO)
  756. mask |= STMPE1801_MSK_INT_EN_GPIO;
  757. if (blocks & STMPE_BLOCK_KEYPAD)
  758. mask |= STMPE1801_MSK_INT_EN_KPC;
  759. return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask,
  760. enable ? mask : 0);
  761. }
  762. static int stmpe_reset(struct stmpe *stmpe)
  763. {
  764. u16 id_val = stmpe->variant->id_val;
  765. unsigned long timeout;
  766. int ret = 0;
  767. u8 reset_bit;
  768. if (id_val == STMPE811_ID)
  769. /* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
  770. reset_bit = STMPE811_SYS_CTRL_RESET;
  771. else
  772. /* all other STMPE variant use bit 7 of SYS_CTRL register */
  773. reset_bit = STMPE_SYS_CTRL_RESET;
  774. ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
  775. reset_bit, reset_bit);
  776. if (ret < 0)
  777. return ret;
  778. msleep(10);
  779. timeout = jiffies + msecs_to_jiffies(100);
  780. while (time_before(jiffies, timeout)) {
  781. ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
  782. if (ret < 0)
  783. return ret;
  784. if (!(ret & reset_bit))
  785. return 0;
  786. usleep_range(100, 200);
  787. }
  788. return -EIO;
  789. }
  790. static struct stmpe_variant_info stmpe1801 = {
  791. .name = "stmpe1801",
  792. .id_val = STMPE1801_ID,
  793. .id_mask = 0xfff0,
  794. .num_gpios = 18,
  795. .af_bits = 0,
  796. .regs = stmpe1801_regs,
  797. .blocks = stmpe1801_blocks,
  798. .num_blocks = ARRAY_SIZE(stmpe1801_blocks),
  799. .num_irqs = STMPE1801_NR_INTERNAL_IRQS,
  800. .enable = stmpe1801_enable,
  801. /* stmpe1801 do not have any gpio alternate function */
  802. .get_altfunc = NULL,
  803. };
  804. /*
  805. * STMPE24XX
  806. */
  807. static const u8 stmpe24xx_regs[] = {
  808. [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID,
  809. [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL,
  810. [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2,
  811. [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB,
  812. [STMPE_IDX_IER_MSB] = STMPE24XX_REG_IER_MSB,
  813. [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB,
  814. [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB,
  815. [STMPE_IDX_GPMR_LSB] = STMPE24XX_REG_GPMR_LSB,
  816. [STMPE_IDX_GPMR_CSB] = STMPE24XX_REG_GPMR_CSB,
  817. [STMPE_IDX_GPMR_MSB] = STMPE24XX_REG_GPMR_MSB,
  818. [STMPE_IDX_GPSR_LSB] = STMPE24XX_REG_GPSR_LSB,
  819. [STMPE_IDX_GPSR_CSB] = STMPE24XX_REG_GPSR_CSB,
  820. [STMPE_IDX_GPSR_MSB] = STMPE24XX_REG_GPSR_MSB,
  821. [STMPE_IDX_GPCR_LSB] = STMPE24XX_REG_GPCR_LSB,
  822. [STMPE_IDX_GPCR_CSB] = STMPE24XX_REG_GPCR_CSB,
  823. [STMPE_IDX_GPCR_MSB] = STMPE24XX_REG_GPCR_MSB,
  824. [STMPE_IDX_GPDR_LSB] = STMPE24XX_REG_GPDR_LSB,
  825. [STMPE_IDX_GPDR_CSB] = STMPE24XX_REG_GPDR_CSB,
  826. [STMPE_IDX_GPDR_MSB] = STMPE24XX_REG_GPDR_MSB,
  827. [STMPE_IDX_GPRER_LSB] = STMPE24XX_REG_GPRER_LSB,
  828. [STMPE_IDX_GPRER_CSB] = STMPE24XX_REG_GPRER_CSB,
  829. [STMPE_IDX_GPRER_MSB] = STMPE24XX_REG_GPRER_MSB,
  830. [STMPE_IDX_GPFER_LSB] = STMPE24XX_REG_GPFER_LSB,
  831. [STMPE_IDX_GPFER_CSB] = STMPE24XX_REG_GPFER_CSB,
  832. [STMPE_IDX_GPFER_MSB] = STMPE24XX_REG_GPFER_MSB,
  833. [STMPE_IDX_GPPUR_LSB] = STMPE24XX_REG_GPPUR_LSB,
  834. [STMPE_IDX_GPPDR_LSB] = STMPE24XX_REG_GPPDR_LSB,
  835. [STMPE_IDX_GPAFR_U_MSB] = STMPE24XX_REG_GPAFR_U_MSB,
  836. [STMPE_IDX_IEGPIOR_LSB] = STMPE24XX_REG_IEGPIOR_LSB,
  837. [STMPE_IDX_IEGPIOR_CSB] = STMPE24XX_REG_IEGPIOR_CSB,
  838. [STMPE_IDX_IEGPIOR_MSB] = STMPE24XX_REG_IEGPIOR_MSB,
  839. [STMPE_IDX_ISGPIOR_MSB] = STMPE24XX_REG_ISGPIOR_MSB,
  840. [STMPE_IDX_GPEDR_LSB] = STMPE24XX_REG_GPEDR_LSB,
  841. [STMPE_IDX_GPEDR_CSB] = STMPE24XX_REG_GPEDR_CSB,
  842. [STMPE_IDX_GPEDR_MSB] = STMPE24XX_REG_GPEDR_MSB,
  843. };
  844. static struct stmpe_variant_block stmpe24xx_blocks[] = {
  845. {
  846. .cell = &stmpe_gpio_cell,
  847. .irq = STMPE24XX_IRQ_GPIOC,
  848. .block = STMPE_BLOCK_GPIO,
  849. },
  850. {
  851. .cell = &stmpe_keypad_cell,
  852. .irq = STMPE24XX_IRQ_KEYPAD,
  853. .block = STMPE_BLOCK_KEYPAD,
  854. },
  855. {
  856. .cell = &stmpe_pwm_cell,
  857. .irq = STMPE24XX_IRQ_PWM0,
  858. .block = STMPE_BLOCK_PWM,
  859. },
  860. };
  861. static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks,
  862. bool enable)
  863. {
  864. unsigned int mask = 0;
  865. if (blocks & STMPE_BLOCK_GPIO)
  866. mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO;
  867. if (blocks & STMPE_BLOCK_KEYPAD)
  868. mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC;
  869. return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask,
  870. enable ? mask : 0);
  871. }
  872. static int stmpe24xx_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
  873. {
  874. switch (block) {
  875. case STMPE_BLOCK_ROTATOR:
  876. return 2;
  877. case STMPE_BLOCK_KEYPAD:
  878. case STMPE_BLOCK_PWM:
  879. return 1;
  880. case STMPE_BLOCK_GPIO:
  881. default:
  882. return 0;
  883. }
  884. }
  885. static struct stmpe_variant_info stmpe2401 = {
  886. .name = "stmpe2401",
  887. .id_val = 0x0101,
  888. .id_mask = 0xffff,
  889. .num_gpios = 24,
  890. .af_bits = 2,
  891. .regs = stmpe24xx_regs,
  892. .blocks = stmpe24xx_blocks,
  893. .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
  894. .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
  895. .enable = stmpe24xx_enable,
  896. .get_altfunc = stmpe24xx_get_altfunc,
  897. };
  898. static struct stmpe_variant_info stmpe2403 = {
  899. .name = "stmpe2403",
  900. .id_val = 0x0120,
  901. .id_mask = 0xffff,
  902. .num_gpios = 24,
  903. .af_bits = 2,
  904. .regs = stmpe24xx_regs,
  905. .blocks = stmpe24xx_blocks,
  906. .num_blocks = ARRAY_SIZE(stmpe24xx_blocks),
  907. .num_irqs = STMPE24XX_NR_INTERNAL_IRQS,
  908. .enable = stmpe24xx_enable,
  909. .get_altfunc = stmpe24xx_get_altfunc,
  910. .enable_autosleep = stmpe1601_autosleep, /* same as stmpe1601 */
  911. };
  912. static struct stmpe_variant_info *stmpe_variant_info[STMPE_NBR_PARTS] = {
  913. [STMPE610] = &stmpe610,
  914. [STMPE801] = &stmpe801,
  915. [STMPE811] = &stmpe811,
  916. [STMPE1600] = &stmpe1600,
  917. [STMPE1601] = &stmpe1601,
  918. [STMPE1801] = &stmpe1801,
  919. [STMPE2401] = &stmpe2401,
  920. [STMPE2403] = &stmpe2403,
  921. };
  922. /*
  923. * These devices can be connected in a 'no-irq' configuration - the irq pin
  924. * is not used and the device cannot interrupt the CPU. Here we only list
  925. * devices which support this configuration - the driver will fail probing
  926. * for any devices not listed here which are configured in this way.
  927. */
  928. static struct stmpe_variant_info *stmpe_noirq_variant_info[STMPE_NBR_PARTS] = {
  929. [STMPE801] = &stmpe801_noirq,
  930. };
  931. static irqreturn_t stmpe_irq(int irq, void *data)
  932. {
  933. struct stmpe *stmpe = data;
  934. struct stmpe_variant_info *variant = stmpe->variant;
  935. int num = DIV_ROUND_UP(variant->num_irqs, 8);
  936. u8 israddr;
  937. u8 isr[3];
  938. int ret;
  939. int i;
  940. if (variant->id_val == STMPE801_ID ||
  941. variant->id_val == STMPE1600_ID) {
  942. int base = irq_find_mapping(stmpe->domain, 0);
  943. handle_nested_irq(base);
  944. return IRQ_HANDLED;
  945. }
  946. if (variant->id_val == STMPE1801_ID)
  947. israddr = stmpe->regs[STMPE_IDX_ISR_LSB];
  948. else
  949. israddr = stmpe->regs[STMPE_IDX_ISR_MSB];
  950. ret = stmpe_block_read(stmpe, israddr, num, isr);
  951. if (ret < 0)
  952. return IRQ_NONE;
  953. for (i = 0; i < num; i++) {
  954. int bank = num - i - 1;
  955. u8 status = isr[i];
  956. u8 clear;
  957. status &= stmpe->ier[bank];
  958. if (!status)
  959. continue;
  960. clear = status;
  961. while (status) {
  962. int bit = __ffs(status);
  963. int line = bank * 8 + bit;
  964. int nestedirq = irq_find_mapping(stmpe->domain, line);
  965. handle_nested_irq(nestedirq);
  966. status &= ~(1 << bit);
  967. }
  968. stmpe_reg_write(stmpe, israddr + i, clear);
  969. }
  970. return IRQ_HANDLED;
  971. }
  972. static void stmpe_irq_lock(struct irq_data *data)
  973. {
  974. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  975. mutex_lock(&stmpe->irq_lock);
  976. }
  977. static void stmpe_irq_sync_unlock(struct irq_data *data)
  978. {
  979. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  980. struct stmpe_variant_info *variant = stmpe->variant;
  981. int num = DIV_ROUND_UP(variant->num_irqs, 8);
  982. int i;
  983. for (i = 0; i < num; i++) {
  984. u8 new = stmpe->ier[i];
  985. u8 old = stmpe->oldier[i];
  986. if (new == old)
  987. continue;
  988. stmpe->oldier[i] = new;
  989. stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_IER_LSB + i], new);
  990. }
  991. mutex_unlock(&stmpe->irq_lock);
  992. }
  993. static void stmpe_irq_mask(struct irq_data *data)
  994. {
  995. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  996. int offset = data->hwirq;
  997. int regoffset = offset / 8;
  998. int mask = 1 << (offset % 8);
  999. stmpe->ier[regoffset] &= ~mask;
  1000. }
  1001. static void stmpe_irq_unmask(struct irq_data *data)
  1002. {
  1003. struct stmpe *stmpe = irq_data_get_irq_chip_data(data);
  1004. int offset = data->hwirq;
  1005. int regoffset = offset / 8;
  1006. int mask = 1 << (offset % 8);
  1007. stmpe->ier[regoffset] |= mask;
  1008. }
  1009. static struct irq_chip stmpe_irq_chip = {
  1010. .name = "stmpe",
  1011. .irq_bus_lock = stmpe_irq_lock,
  1012. .irq_bus_sync_unlock = stmpe_irq_sync_unlock,
  1013. .irq_mask = stmpe_irq_mask,
  1014. .irq_unmask = stmpe_irq_unmask,
  1015. };
  1016. static int stmpe_irq_map(struct irq_domain *d, unsigned int virq,
  1017. irq_hw_number_t hwirq)
  1018. {
  1019. struct stmpe *stmpe = d->host_data;
  1020. struct irq_chip *chip = NULL;
  1021. if (stmpe->variant->id_val != STMPE801_ID)
  1022. chip = &stmpe_irq_chip;
  1023. irq_set_chip_data(virq, stmpe);
  1024. irq_set_chip_and_handler(virq, chip, handle_edge_irq);
  1025. irq_set_nested_thread(virq, 1);
  1026. irq_set_noprobe(virq);
  1027. return 0;
  1028. }
  1029. static void stmpe_irq_unmap(struct irq_domain *d, unsigned int virq)
  1030. {
  1031. irq_set_chip_and_handler(virq, NULL, NULL);
  1032. irq_set_chip_data(virq, NULL);
  1033. }
  1034. static const struct irq_domain_ops stmpe_irq_ops = {
  1035. .map = stmpe_irq_map,
  1036. .unmap = stmpe_irq_unmap,
  1037. .xlate = irq_domain_xlate_twocell,
  1038. };
  1039. static int stmpe_irq_init(struct stmpe *stmpe, struct device_node *np)
  1040. {
  1041. int base = 0;
  1042. int num_irqs = stmpe->variant->num_irqs;
  1043. stmpe->domain = irq_domain_add_simple(np, num_irqs, base,
  1044. &stmpe_irq_ops, stmpe);
  1045. if (!stmpe->domain) {
  1046. dev_err(stmpe->dev, "Failed to create irqdomain\n");
  1047. return -ENOSYS;
  1048. }
  1049. return 0;
  1050. }
  1051. static int stmpe_chip_init(struct stmpe *stmpe)
  1052. {
  1053. unsigned int irq_trigger = stmpe->pdata->irq_trigger;
  1054. int autosleep_timeout = stmpe->pdata->autosleep_timeout;
  1055. struct stmpe_variant_info *variant = stmpe->variant;
  1056. u8 icr = 0;
  1057. unsigned int id;
  1058. u8 data[2];
  1059. int ret;
  1060. ret = stmpe_block_read(stmpe, stmpe->regs[STMPE_IDX_CHIP_ID],
  1061. ARRAY_SIZE(data), data);
  1062. if (ret < 0)
  1063. return ret;
  1064. id = (data[0] << 8) | data[1];
  1065. if ((id & variant->id_mask) != variant->id_val) {
  1066. dev_err(stmpe->dev, "unknown chip id: %#x\n", id);
  1067. return -EINVAL;
  1068. }
  1069. dev_info(stmpe->dev, "%s detected, chip id: %#x\n", variant->name, id);
  1070. /* Disable all modules -- subdrivers should enable what they need. */
  1071. ret = stmpe_disable(stmpe, ~0);
  1072. if (ret)
  1073. return ret;
  1074. ret = stmpe_reset(stmpe);
  1075. if (ret < 0)
  1076. return ret;
  1077. if (stmpe->irq >= 0) {
  1078. if (id == STMPE801_ID || id == STMPE1600_ID)
  1079. icr = STMPE_SYS_CTRL_INT_EN;
  1080. else
  1081. icr = STMPE_ICR_LSB_GIM;
  1082. /* STMPE801 and STMPE1600 don't support Edge interrupts */
  1083. if (id != STMPE801_ID && id != STMPE1600_ID) {
  1084. if (irq_trigger == IRQF_TRIGGER_FALLING ||
  1085. irq_trigger == IRQF_TRIGGER_RISING)
  1086. icr |= STMPE_ICR_LSB_EDGE;
  1087. }
  1088. if (irq_trigger == IRQF_TRIGGER_RISING ||
  1089. irq_trigger == IRQF_TRIGGER_HIGH) {
  1090. if (id == STMPE801_ID || id == STMPE1600_ID)
  1091. icr |= STMPE_SYS_CTRL_INT_HI;
  1092. else
  1093. icr |= STMPE_ICR_LSB_HIGH;
  1094. }
  1095. }
  1096. if (stmpe->pdata->autosleep) {
  1097. ret = stmpe_autosleep(stmpe, autosleep_timeout);
  1098. if (ret)
  1099. return ret;
  1100. }
  1101. return stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_ICR_LSB], icr);
  1102. }
  1103. static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
  1104. {
  1105. return mfd_add_devices(stmpe->dev, stmpe->pdata->id, cell, 1,
  1106. NULL, 0, stmpe->domain);
  1107. }
  1108. static int stmpe_devices_init(struct stmpe *stmpe)
  1109. {
  1110. struct stmpe_variant_info *variant = stmpe->variant;
  1111. unsigned int platform_blocks = stmpe->pdata->blocks;
  1112. int ret = -EINVAL;
  1113. int i, j;
  1114. for (i = 0; i < variant->num_blocks; i++) {
  1115. struct stmpe_variant_block *block = &variant->blocks[i];
  1116. if (!(platform_blocks & block->block))
  1117. continue;
  1118. for (j = 0; j < block->cell->num_resources; j++) {
  1119. struct resource *res =
  1120. (struct resource *) &block->cell->resources[j];
  1121. /* Dynamically fill in a variant's IRQ. */
  1122. if (res->flags & IORESOURCE_IRQ)
  1123. res->start = res->end = block->irq + j;
  1124. }
  1125. platform_blocks &= ~block->block;
  1126. ret = stmpe_add_device(stmpe, block->cell);
  1127. if (ret)
  1128. return ret;
  1129. }
  1130. if (platform_blocks)
  1131. dev_warn(stmpe->dev,
  1132. "platform wants blocks (%#x) not present on variant",
  1133. platform_blocks);
  1134. return ret;
  1135. }
  1136. static void stmpe_of_probe(struct stmpe_platform_data *pdata,
  1137. struct device_node *np)
  1138. {
  1139. struct device_node *child;
  1140. pdata->id = of_alias_get_id(np, "stmpe-i2c");
  1141. if (pdata->id < 0)
  1142. pdata->id = -1;
  1143. of_property_read_u32(np, "st,autosleep-timeout",
  1144. &pdata->autosleep_timeout);
  1145. pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
  1146. for_each_available_child_of_node(np, child) {
  1147. if (of_device_is_compatible(child, stmpe_gpio_cell.of_compatible))
  1148. pdata->blocks |= STMPE_BLOCK_GPIO;
  1149. else if (of_device_is_compatible(child, stmpe_keypad_cell.of_compatible))
  1150. pdata->blocks |= STMPE_BLOCK_KEYPAD;
  1151. else if (of_device_is_compatible(child, stmpe_ts_cell.of_compatible))
  1152. pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
  1153. else if (of_device_is_compatible(child, stmpe_adc_cell.of_compatible))
  1154. pdata->blocks |= STMPE_BLOCK_ADC;
  1155. else if (of_device_is_compatible(child, stmpe_pwm_cell.of_compatible))
  1156. pdata->blocks |= STMPE_BLOCK_PWM;
  1157. }
  1158. }
  1159. /* Called from client specific probe routines */
  1160. int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
  1161. {
  1162. struct stmpe_platform_data *pdata;
  1163. struct device_node *np = ci->dev->of_node;
  1164. struct stmpe *stmpe;
  1165. struct gpio_desc *irq_gpio;
  1166. int ret;
  1167. u32 val;
  1168. pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
  1169. if (!pdata)
  1170. return -ENOMEM;
  1171. stmpe_of_probe(pdata, np);
  1172. if (of_find_property(np, "interrupts", NULL) == NULL)
  1173. ci->irq = -1;
  1174. stmpe = devm_kzalloc(ci->dev, sizeof(struct stmpe), GFP_KERNEL);
  1175. if (!stmpe)
  1176. return -ENOMEM;
  1177. mutex_init(&stmpe->irq_lock);
  1178. mutex_init(&stmpe->lock);
  1179. if (!of_property_read_u32(np, "st,sample-time", &val))
  1180. stmpe->sample_time = val;
  1181. if (!of_property_read_u32(np, "st,mod-12b", &val))
  1182. stmpe->mod_12b = val;
  1183. if (!of_property_read_u32(np, "st,ref-sel", &val))
  1184. stmpe->ref_sel = val;
  1185. if (!of_property_read_u32(np, "st,adc-freq", &val))
  1186. stmpe->adc_freq = val;
  1187. stmpe->dev = ci->dev;
  1188. stmpe->client = ci->client;
  1189. stmpe->pdata = pdata;
  1190. stmpe->ci = ci;
  1191. stmpe->partnum = partnum;
  1192. stmpe->variant = stmpe_variant_info[partnum];
  1193. stmpe->regs = stmpe->variant->regs;
  1194. stmpe->num_gpios = stmpe->variant->num_gpios;
  1195. stmpe->vcc = devm_regulator_get_optional(ci->dev, "vcc");
  1196. if (!IS_ERR(stmpe->vcc)) {
  1197. ret = regulator_enable(stmpe->vcc);
  1198. if (ret)
  1199. dev_warn(ci->dev, "failed to enable VCC supply\n");
  1200. }
  1201. stmpe->vio = devm_regulator_get_optional(ci->dev, "vio");
  1202. if (!IS_ERR(stmpe->vio)) {
  1203. ret = regulator_enable(stmpe->vio);
  1204. if (ret)
  1205. dev_warn(ci->dev, "failed to enable VIO supply\n");
  1206. }
  1207. dev_set_drvdata(stmpe->dev, stmpe);
  1208. if (ci->init)
  1209. ci->init(stmpe);
  1210. irq_gpio = devm_gpiod_get_optional(ci->dev, "irq", GPIOD_ASIS);
  1211. ret = PTR_ERR_OR_ZERO(irq_gpio);
  1212. if (ret) {
  1213. dev_err(stmpe->dev, "failed to request IRQ GPIO: %d\n", ret);
  1214. return ret;
  1215. }
  1216. if (irq_gpio) {
  1217. stmpe->irq = gpiod_to_irq(irq_gpio);
  1218. pdata->irq_trigger = gpiod_is_active_low(irq_gpio) ?
  1219. IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH;
  1220. } else {
  1221. stmpe->irq = ci->irq;
  1222. pdata->irq_trigger = IRQF_TRIGGER_NONE;
  1223. }
  1224. if (stmpe->irq < 0) {
  1225. /* use alternate variant info for no-irq mode, if supported */
  1226. dev_info(stmpe->dev,
  1227. "%s configured in no-irq mode by platform data\n",
  1228. stmpe->variant->name);
  1229. if (!stmpe_noirq_variant_info[stmpe->partnum]) {
  1230. dev_err(stmpe->dev,
  1231. "%s does not support no-irq mode!\n",
  1232. stmpe->variant->name);
  1233. return -ENODEV;
  1234. }
  1235. stmpe->variant = stmpe_noirq_variant_info[stmpe->partnum];
  1236. } else if (pdata->irq_trigger == IRQF_TRIGGER_NONE) {
  1237. pdata->irq_trigger = irq_get_trigger_type(stmpe->irq);
  1238. }
  1239. ret = stmpe_chip_init(stmpe);
  1240. if (ret)
  1241. return ret;
  1242. if (stmpe->irq >= 0) {
  1243. ret = stmpe_irq_init(stmpe, np);
  1244. if (ret)
  1245. return ret;
  1246. ret = devm_request_threaded_irq(ci->dev, stmpe->irq, NULL,
  1247. stmpe_irq, pdata->irq_trigger | IRQF_ONESHOT,
  1248. "stmpe", stmpe);
  1249. if (ret) {
  1250. dev_err(stmpe->dev, "failed to request IRQ: %d\n",
  1251. ret);
  1252. return ret;
  1253. }
  1254. }
  1255. ret = stmpe_devices_init(stmpe);
  1256. if (!ret)
  1257. return 0;
  1258. dev_err(stmpe->dev, "failed to add children\n");
  1259. mfd_remove_devices(stmpe->dev);
  1260. return ret;
  1261. }
  1262. void stmpe_remove(struct stmpe *stmpe)
  1263. {
  1264. if (!IS_ERR(stmpe->vio) && regulator_is_enabled(stmpe->vio))
  1265. regulator_disable(stmpe->vio);
  1266. if (!IS_ERR(stmpe->vcc) && regulator_is_enabled(stmpe->vcc))
  1267. regulator_disable(stmpe->vcc);
  1268. __stmpe_disable(stmpe, STMPE_BLOCK_ADC);
  1269. mfd_remove_devices(stmpe->dev);
  1270. }
  1271. #ifdef CONFIG_PM
  1272. static int stmpe_suspend(struct device *dev)
  1273. {
  1274. struct stmpe *stmpe = dev_get_drvdata(dev);
  1275. if (stmpe->irq >= 0 && device_may_wakeup(dev))
  1276. enable_irq_wake(stmpe->irq);
  1277. return 0;
  1278. }
  1279. static int stmpe_resume(struct device *dev)
  1280. {
  1281. struct stmpe *stmpe = dev_get_drvdata(dev);
  1282. if (stmpe->irq >= 0 && device_may_wakeup(dev))
  1283. disable_irq_wake(stmpe->irq);
  1284. return 0;
  1285. }
  1286. const struct dev_pm_ops stmpe_dev_pm_ops = {
  1287. .suspend = stmpe_suspend,
  1288. .resume = stmpe_resume,
  1289. };
  1290. #endif