max77775-irq.c 15 KB

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  1. /*
  2. * max77775-irq.c - Interrupt controller support for MAX77775
  3. *
  4. * Copyright (C) 2016 Samsung Electronics Co.Ltd
  5. * Insun Choi <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  19. *
  20. * This driver is based on max77775-irq.c
  21. */
  22. #include <linux/err.h>
  23. #include <linux/irq.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/gpio.h>
  26. #include <linux/mfd/max77775_log.h>
  27. #include <linux/mfd/max77775.h>
  28. #include <linux/mfd/max77775-private.h>
  29. static const u8 max77775_mask_reg[] = {
  30. /* TODO: Need to check other INTMASK */
  31. [SYS_INT] = MAX77775_PMIC_REG_SYSTEM_INT_MASK,
  32. [CHG_INT] = MAX77775_CHG_REG_INT_MASK,
  33. [FUEL_INT] = MAX77775_REG_INVALID,
  34. [USBC_INT] = MAX77775_USBC_REG_UIC_INT_M,
  35. [CC_INT] = MAX77775_USBC_REG_CC_INT_M,
  36. [PD_INT] = MAX77775_USBC_REG_PD_INT_M,
  37. [VDM_INT] = MAX77775_USBC_REG_VDM_INT_M,
  38. [SPARE_INT] = MAX77775_USBC_REG_SPARE_INT_M,
  39. [VIR_INT] = MAX77775_REG_INVALID,
  40. };
  41. static struct i2c_client *get_i2c(struct max77775_dev *max77775,
  42. enum max77775_irq_source src)
  43. {
  44. switch (src) {
  45. case SYS_INT:
  46. return max77775->i2c;
  47. case FUEL_INT:
  48. return max77775->fuelgauge;
  49. case CHG_INT:
  50. return max77775->charger;
  51. case USBC_INT:
  52. case CC_INT:
  53. case PD_INT:
  54. case VDM_INT:
  55. case SPARE_INT:
  56. case VIR_INT:
  57. return max77775->muic;
  58. default:
  59. return ERR_PTR(-EINVAL);
  60. }
  61. }
  62. struct max77775_irq_data {
  63. int mask;
  64. enum max77775_irq_source group;
  65. };
  66. static const struct max77775_irq_data max77775_irqs[] = {
  67. [MAX77775_SYSTEM_IRQ_SYSUVLO_INT] = { .group = SYS_INT, .mask = 1 << 4 },
  68. [MAX77775_SYSTEM_IRQ_SYSOVLO_INT] = { .group = SYS_INT, .mask = 1 << 5 },
  69. [MAX77775_SYSTEM_IRQ_TSHDN_INT] = { .group = SYS_INT, .mask = 1 << 6 },
  70. [MAX77775_SYSTEM_IRQ_SCP_INT] = { .group = SYS_INT, .mask = 1 << 7 },
  71. [MAX77775_CHG_IRQ_BYP_I] = { .group = CHG_INT, .mask = 1 << 0 },
  72. [MAX77775_CHG_IRQ_BATP_I] = { .group = CHG_INT, .mask = 1 << 2 },
  73. [MAX77775_CHG_IRQ_BAT_I] = { .group = CHG_INT, .mask = 1 << 3 },
  74. [MAX77775_CHG_IRQ_CHG_I] = { .group = CHG_INT, .mask = 1 << 4 },
  75. [MAX77775_CHG_IRQ_WCIN_I] = { .group = CHG_INT, .mask = 1 << 5 },
  76. [MAX77775_CHG_IRQ_CHGIN_I] = { .group = CHG_INT, .mask = 1 << 6 },
  77. [MAX77775_CHG_IRQ_AICL_I] = { .group = CHG_INT, .mask = 1 << 7 },
  78. [MAX77775_FG_IRQ_ALERT] = { .group = FUEL_INT, .mask = 1 << 1 },
  79. [MAX77775_USBC_IRQ_APC_INT] = { .group = USBC_INT, .mask = 1 << 7 },
  80. [MAX77775_USBC_IRQ_SYSM_INT] = { .group = USBC_INT, .mask = 1 << 6 },
  81. [MAX77775_USBC_IRQ_VBUS_INT] = { .group = USBC_INT, .mask = 1 << 5 },
  82. [MAX77775_USBC_IRQ_VBADC_INT] = { .group = USBC_INT, .mask = 1 << 4 },
  83. [MAX77775_USBC_IRQ_DCD_INT] = { .group = USBC_INT, .mask = 1 << 3 },
  84. [MAX77775_USBC_IRQ_STOPMODE_INT] = { .group = USBC_INT, .mask = 1 << 2 },
  85. [MAX77775_USBC_IRQ_CHGT_INT] = { .group = USBC_INT, .mask = 1 << 1 },
  86. [MAX77775_USBC_IRQ_UIDADC_INT] = { .group = USBC_INT, .mask = 1 << 0 },
  87. [MAX77775_CC_IRQ_VCONNCOP_INT] = { .group = CC_INT, .mask = 1 << 7 },
  88. [MAX77775_CC_IRQ_VSAFE0V_INT] = { .group = CC_INT, .mask = 1 << 6 },
  89. [MAX77775_CC_IRQ_DETABRT_INT] = { .group = CC_INT, .mask = 1 << 5 },
  90. [MAX77775_CC_IRQ_VCONNSC_INT] = { .group = CC_INT, .mask = 1 << 4 },
  91. [MAX77775_CC_IRQ_CCPINSTAT_INT] = { .group = CC_INT, .mask = 1 << 3 },
  92. [MAX77775_CC_IRQ_CCISTAT_INT] = { .group = CC_INT, .mask = 1 << 2 },
  93. [MAX77775_CC_IRQ_CCVCNSTAT_INT] = { .group = CC_INT, .mask = 1 << 1 },
  94. [MAX77775_CC_IRQ_CCSTAT_INT] = { .group = CC_INT, .mask = 1 << 0 },
  95. [MAX77775_PD_IRQ_PDMSG_INT] = { .group = PD_INT, .mask = 1 << 7 },
  96. [MAX77775_PD_IRQ_PS_RDY_INT] = { .group = PD_INT, .mask = 1 << 6 },
  97. [MAX77775_PD_IRQ_DATAROLE_INT] = { .group = PD_INT, .mask = 1 << 5 },
  98. [MAX77775_IRQ_VDM_ATTENTION_INT] = { .group = PD_INT, .mask = 1 << 4 },
  99. [MAX77775_IRQ_VDM_DP_CONFIGURE_INT] = { .group = PD_INT, .mask = 1 << 3 },
  100. [MAX77775_IRQ_VDM_DP_STATUS_UPDATE_INT] = { .group = PD_INT, .mask = 1 << 2 },
  101. [MAX77775_PD_IRQ_SSACCI_INT] = { .group = PD_INT, .mask = 1 << 1 },
  102. [MAX77775_PD_IRQ_FCTIDI_INT] = { .group = PD_INT, .mask = 1 << 0 },
  103. [MAX77775_IRQ_VDM_DISCOVER_ID_INT] = { .group = VDM_INT, .mask = 1 << 0 },
  104. [MAX77775_IRQ_VDM_DISCOVER_SVIDS_INT] = { .group = VDM_INT, .mask = 1 << 1 },
  105. [MAX77775_IRQ_VDM_DISCOVER_MODES_INT] = { .group = VDM_INT, .mask = 1 << 2 },
  106. [MAX77775_IRQ_VDM_ENTER_MODE_INT] = { .group = VDM_INT, .mask = 1 << 3 },
  107. [MAX77775_IRQ_USBID_INT] = { .group = SPARE_INT, .mask = 1 << 7 },
  108. [MAX77775_IRQ_TACONN_INT] = { .group = SPARE_INT, .mask = 1 << 6 },
  109. [MAX77775_VIR_IRQ_ALTERROR_INT] = { .group = VIR_INT, .mask = 1 << 0 },
  110. };
  111. static void max77775_irq_lock(struct irq_data *data)
  112. {
  113. struct max77775_dev *max77775 = irq_get_chip_data(data->irq);
  114. mutex_lock(&max77775->irqlock);
  115. }
  116. static void max77775_irq_sync_unlock(struct irq_data *data)
  117. {
  118. struct max77775_dev *max77775 = irq_get_chip_data(data->irq);
  119. int i;
  120. for (i = 0; i < MAX77775_IRQ_GROUP_NR; i++) {
  121. u8 mask_reg = max77775_mask_reg[i];
  122. struct i2c_client *i2c = get_i2c(max77775, i);
  123. if (mask_reg == MAX77775_REG_INVALID ||
  124. IS_ERR_OR_NULL(i2c))
  125. continue;
  126. max77775->irq_masks_cache[i] = max77775->irq_masks_cur[i];
  127. max77775_write_reg(i2c, max77775_mask_reg[i],
  128. max77775->irq_masks_cur[i]);
  129. }
  130. mutex_unlock(&max77775->irqlock);
  131. }
  132. static const inline struct max77775_irq_data *
  133. irq_to_max77775_irq(struct max77775_dev *max77775, int irq)
  134. {
  135. return &max77775_irqs[irq - max77775->irq_base];
  136. }
  137. static void max77775_irq_mask(struct irq_data *data)
  138. {
  139. struct max77775_dev *max77775 = irq_get_chip_data(data->irq);
  140. const struct max77775_irq_data *irq_data =
  141. irq_to_max77775_irq(max77775, data->irq);
  142. if (irq_data->group >= MAX77775_IRQ_GROUP_NR)
  143. return;
  144. max77775->irq_masks_cur[irq_data->group] |= irq_data->mask;
  145. }
  146. static void max77775_irq_unmask(struct irq_data *data)
  147. {
  148. struct max77775_dev *max77775 = irq_get_chip_data(data->irq);
  149. const struct max77775_irq_data *irq_data =
  150. irq_to_max77775_irq(max77775, data->irq);
  151. if (irq_data->group >= MAX77775_IRQ_GROUP_NR)
  152. return;
  153. max77775->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
  154. }
  155. static void max77775_irq_disable(struct irq_data *data)
  156. {
  157. max77775_irq_mask(data);
  158. }
  159. static struct irq_chip max77775_irq_chip = {
  160. .name = MFD_DEV_NAME,
  161. .irq_bus_lock = max77775_irq_lock,
  162. .irq_bus_sync_unlock = max77775_irq_sync_unlock,
  163. .irq_mask = max77775_irq_mask,
  164. .irq_unmask = max77775_irq_unmask,
  165. .irq_disable = max77775_irq_disable,
  166. };
  167. #define VB_LOW 0
  168. static irqreturn_t max77775_irq_thread(int irq, void *data)
  169. {
  170. struct max77775_dev *max77775 = data;
  171. u8 irq_reg[MAX77775_IRQ_GROUP_NR] = {0};
  172. u8 irq_src;
  173. int i, ret;
  174. u8 irq_vdm_mask = 0x0;
  175. u8 dump_reg[10] = {0, };
  176. u8 reg_data;
  177. u8 cc_status1 = 0;
  178. u8 cc_status2 = 0;
  179. u8 bc_status = 0;
  180. u8 ccstat = 0;
  181. u8 vbvolt = 0;
  182. u8 pre_ccstati = 0;
  183. u8 ic_alt_mode = 0;
  184. md75_info_usb("%s:%s irq gpio pre-state(0x%02x)\n",
  185. MFD_DEV_NAME, __func__,
  186. gpio_get_value(max77775->irq_gpio));
  187. __pm_stay_awake(&max77775->ws);
  188. if (max77775->suspended) {
  189. md75_err_usb("%s:%s skip.max77775 suspended. irq gpio post-state(0x%02x)\n",
  190. MFD_DEV_NAME, __func__, gpio_get_value(max77775->irq_gpio));
  191. /* Irq will occur again because of IRQF_TRIGGER_LOW */
  192. wait_event_interruptible_timeout(max77775->suspend_wait,
  193. !max77775->suspended,
  194. msecs_to_jiffies(50));
  195. __pm_relax(&max77775->ws);
  196. return IRQ_NONE;
  197. }
  198. ret = max77775_read_reg(max77775->i2c,
  199. MAX77775_PMIC_REG_INTSRC, &irq_src);
  200. if (ret) {
  201. md75_err_usb("%s:%s Failed to read interrupt source: %d\n",
  202. MFD_DEV_NAME, __func__, ret);
  203. __pm_relax(&max77775->ws);
  204. return IRQ_NONE;
  205. }
  206. md75_info_usb("%s:%s: irq[%d] %d/%d/%d irq_src=0x%02x (FW%02x.%02x)\n",
  207. MFD_DEV_NAME, __func__, irq, max77775->irq,
  208. max77775->irq_base, max77775->irq_gpio, irq_src,
  209. max77775->FW_Revision, max77775->FW_Minor_Revision);
  210. if (irq_src & MAX77775_IRQSRC_CHG) {
  211. /* CHG_INT */
  212. ret = max77775_read_reg(max77775->charger, MAX77775_CHG_REG_INT,
  213. &irq_reg[CHG_INT]);
  214. if (max77775->enable_nested_irq) {
  215. irq_reg[USBC_INT] |= max77775->usbc_irq;
  216. max77775->enable_nested_irq = 0x0;
  217. max77775->usbc_irq = 0x0;
  218. }
  219. pr_debug("%s:%s charger interrupt(0x%02x)\n",
  220. MFD_DEV_NAME, __func__, irq_reg[CHG_INT]);
  221. /* mask chgin to prevent chgin infinite interrupt
  222. * chgin is unmasked chgin isr
  223. */
  224. if (irq_reg[CHG_INT] &
  225. max77775_irqs[MAX77775_CHG_IRQ_CHGIN_I].mask) {
  226. max77775_read_reg(max77775->charger,
  227. MAX77775_CHG_REG_INT_MASK, &reg_data);
  228. reg_data |= (1 << 6);
  229. max77775_write_reg(max77775->charger,
  230. MAX77775_CHG_REG_INT_MASK, reg_data);
  231. }
  232. }
  233. if (irq_src & MAX77775_IRQSRC_FG) {
  234. pr_debug("%s:[%s] fuelgauge interrupt\n", MFD_DEV_NAME, __func__);
  235. pr_debug("%s:[%s]IRQ_BASE(%d), NESTED_IRQ(%d)\n",
  236. MFD_DEV_NAME, __func__, max77775->irq_base,
  237. max77775->irq_base + MAX77775_FG_IRQ_ALERT);
  238. irq_reg[FUEL_INT] = 1 << 1;
  239. }
  240. if (irq_src & MAX77775_IRQSRC_TOP) {
  241. /* SYS_INT */
  242. ret = max77775_read_reg(max77775->i2c, MAX77775_PMIC_REG_SYSTEM_INT,
  243. &irq_reg[SYS_INT]);
  244. pr_debug("%s:%s topsys interrupt(0x%02x)\n",
  245. MFD_DEV_NAME, __func__, irq_reg[SYS_INT]);
  246. }
  247. if ((irq_src & MAX77775_IRQSRC_USBC) && max77775->cc_booting_complete) {
  248. /* USBC INT */
  249. ret = max77775_bulk_read(max77775->muic, MAX77775_USBC_REG_UIC_INT,
  250. 5, &irq_reg[USBC_INT]);
  251. ret = max77775_read_reg(max77775->muic, MAX77775_USBC_REG_VDM_INT_M,
  252. &irq_vdm_mask);
  253. if (irq_reg[USBC_INT] & BIT_VBUSDetI) {
  254. ret = max77775_read_reg(max77775->muic, REG_BC_STATUS, &bc_status);
  255. ret = max77775_read_reg(max77775->muic, REG_CC_STATUS1, &cc_status1);
  256. vbvolt = (bc_status & BIT_VBUSDet) >> FFS(BIT_VBUSDet);
  257. ccstat = (cc_status1 & BIT_CCStat) >> FFS(BIT_CCStat);
  258. if (cc_No_Connection == ccstat && vbvolt == VB_LOW) {
  259. pre_ccstati = irq_reg[CC_INT];
  260. irq_reg[CC_INT] |= 0x1;
  261. md75_info_usb("%s:%s [max77775] set the cc_stat int [work-around] :%x, %x\n",
  262. MFD_DEV_NAME, __func__,
  263. pre_ccstati, irq_reg[CC_INT]);
  264. }
  265. }
  266. if (irq_reg[SPARE_INT] & BIT_USBID) {
  267. // To Do
  268. }
  269. ret = max77775_bulk_read(max77775->muic, MAX77775_USBC_REG_USBC_STATUS1,
  270. 10, dump_reg);
  271. md75_info_usb("%s:%s irq_reg, complete [%x], uicI=%x, ccI=%x, pdI=%x, vdmI=%x, vdmM=%x, sprI=%x\n",
  272. MFD_DEV_NAME, __func__,
  273. max77775->cc_booting_complete,
  274. irq_reg[USBC_INT], irq_reg[CC_INT], irq_reg[PD_INT], irq_reg[VDM_INT], irq_vdm_mask, irq_reg[SPARE_INT]);
  275. md75_info_usb("%s:%s dump_reg, S1=%x, S2=%x, bcS=%x, fwrev2=%x, ccS1=%x, ccS2=%x, pdS1=%x, pdS2=%x, sp1S=%x, sp2S=%x\n",
  276. MFD_DEV_NAME, __func__,
  277. dump_reg[0], dump_reg[1], dump_reg[2], dump_reg[3], dump_reg[4],
  278. dump_reg[5], dump_reg[6], dump_reg[7], dump_reg[8], dump_reg[9]);
  279. }
  280. if (max77775->cc_booting_complete) {
  281. max77775_read_reg(max77775->muic, REG_CC_STATUS2, &cc_status2);
  282. ic_alt_mode = (cc_status2 & BIT_Altmode) >> FFS(BIT_Altmode);
  283. if (!ic_alt_mode && max77775->set_altmode_en)
  284. irq_reg[VIR_INT] |= (1 << 0);
  285. md75_info_usb("%s:%s ic_alt_mode=%d\n", MFD_DEV_NAME, __func__, ic_alt_mode);
  286. if (irq_reg[PD_INT] & BIT_PDMsg) {
  287. if (dump_reg[6] == Sink_PD_PSRdy_received
  288. || dump_reg[6] == SRC_CAP_RECEIVED) {
  289. if (max77775->check_pdmsg)
  290. max77775->check_pdmsg(max77775->usbc_data, dump_reg[6]);
  291. }
  292. }
  293. }
  294. /* Apply masking */
  295. for (i = 0; i < MAX77775_IRQ_GROUP_NR; i++)
  296. irq_reg[i] &= ~max77775->irq_masks_cur[i];
  297. /* Report */
  298. for (i = 0; i < MAX77775_IRQ_NR; i++) {
  299. if (irq_reg[max77775_irqs[i].group] & max77775_irqs[i].mask)
  300. handle_nested_irq(max77775->irq_base + i);
  301. }
  302. __pm_relax(&max77775->ws);
  303. md75_info_usb("%s:%s irq gpio post-state(0x%02x)\n",
  304. MFD_DEV_NAME, __func__,
  305. gpio_get_value(max77775->irq_gpio));
  306. return IRQ_HANDLED;
  307. }
  308. int max77775_irq_init(struct max77775_dev *max77775)
  309. {
  310. int i;
  311. int ret = 0;
  312. u8 i2c_data;
  313. int cur_irq;
  314. if (!gpio_is_valid(max77775->irq_gpio)) {
  315. dev_warn(max77775->dev, "No interrupt specified.\n");
  316. max77775->irq_base = 0;
  317. goto err;
  318. }
  319. if (max77775->irq_base < 0) {
  320. dev_err(max77775->dev, "No interrupt base specified.\n");
  321. goto err;
  322. }
  323. mutex_init(&max77775->irqlock);
  324. max77775->irq = gpio_to_irq(max77775->irq_gpio);
  325. md75_info_usb("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
  326. max77775->irq, max77775->irq_gpio);
  327. ret = gpio_request(max77775->irq_gpio, "if_pmic_irq");
  328. if (ret) {
  329. dev_err(max77775->dev, "%s: failed requesting gpio %d\n",
  330. __func__, max77775->irq_gpio);
  331. goto err_gpio_request;
  332. }
  333. gpio_direction_input(max77775->irq_gpio);
  334. /* Mask individual interrupt sources */
  335. for (i = 0; i < MAX77775_IRQ_GROUP_NR; i++) {
  336. struct i2c_client *i2c;
  337. /* MUIC IRQ 0:MASK 1:NOT MASK => NOT USE */
  338. /* Other IRQ 1:MASK 0:NOT MASK */
  339. max77775->irq_masks_cur[i] = 0xff;
  340. max77775->irq_masks_cache[i] = 0xff;
  341. i2c = get_i2c(max77775, i);
  342. if (IS_ERR_OR_NULL(i2c))
  343. continue;
  344. if (max77775_mask_reg[i] == MAX77775_REG_INVALID)
  345. continue;
  346. max77775_write_reg(i2c, max77775_mask_reg[i], 0xff);
  347. }
  348. /* Register with genirq */
  349. for (i = 0; i < MAX77775_IRQ_NR; i++) {
  350. cur_irq = i + max77775->irq_base;
  351. irq_set_chip_data(cur_irq, max77775);
  352. irq_set_chip_and_handler(cur_irq, &max77775_irq_chip,
  353. handle_level_irq);
  354. irq_set_nested_thread(cur_irq, 1);
  355. #ifdef CONFIG_ARM
  356. set_irq_flags(cur_irq, IRQF_VALID);
  357. #else
  358. irq_set_noprobe(cur_irq);
  359. #endif
  360. }
  361. /* Unmask max77775 interrupt */
  362. ret = max77775_read_reg(max77775->i2c, MAX77775_PMIC_REG_INTSRC_MASK,
  363. &i2c_data);
  364. if (ret) {
  365. md75_err_usb("%s:%s fail to read muic reg\n", MFD_DEV_NAME, __func__);
  366. goto err_read_intsrc_mask2;
  367. }
  368. i2c_data |= 0xF; /* mask intsrc interrupt */
  369. max77775_write_reg(max77775->i2c, MAX77775_PMIC_REG_INTSRC_MASK,
  370. i2c_data);
  371. ret = request_threaded_irq(max77775->irq, NULL, max77775_irq_thread,
  372. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  373. "max77775-irq", max77775);
  374. if (ret) {
  375. dev_err(max77775->dev, "Failed to request IRQ %d: %d\n",
  376. max77775->irq, ret);
  377. goto err_read_intsrc_mask2;
  378. }
  379. enable_irq_wake(max77775->irq);
  380. /* Unmask max77775 interrupt */
  381. ret = max77775_read_reg(max77775->i2c, MAX77775_PMIC_REG_INTSRC_MASK,
  382. &i2c_data);
  383. if (ret) {
  384. md75_err_usb("%s:%s fail to read muic reg\n", MFD_DEV_NAME, __func__);
  385. goto err_read_intsrc_mask1;
  386. }
  387. i2c_data &= ~(MAX77775_IRQSRC_CHG); /* Unmask charger interrupt */
  388. max77775_write_reg(max77775->i2c, MAX77775_PMIC_REG_INTSRC_MASK,
  389. i2c_data);
  390. md75_info_usb("%s:%s max77775_PMIC_REG_INTSRC_MASK=0x%02x\n",
  391. MFD_DEV_NAME, __func__, i2c_data);
  392. return 0;
  393. err_read_intsrc_mask1:
  394. if (max77775->irq)
  395. free_irq(max77775->irq, max77775);
  396. err_read_intsrc_mask2:
  397. if (gpio_is_valid(max77775->irq_gpio))
  398. gpio_free(max77775->irq_gpio);
  399. err_gpio_request:
  400. mutex_destroy(&max77775->irqlock);
  401. err:
  402. return ret;
  403. }
  404. void max77775_irq_exit(struct max77775_dev *max77775)
  405. {
  406. if (max77775->irq)
  407. free_irq(max77775->irq, max77775);
  408. if (gpio_is_valid(max77775->irq_gpio))
  409. gpio_free(max77775->irq_gpio);
  410. mutex_destroy(&max77775->irqlock);
  411. }