ioc3.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SGI IOC3 multifunction device driver
  4. *
  5. * Copyright (C) 2018, 2019 Thomas Bogendoerfer <[email protected]>
  6. *
  7. * Based on work by:
  8. * Stanislaw Skowronek <[email protected]>
  9. * Joshua Kinard <[email protected]>
  10. * Brent Casavant <[email protected]> - IOC4 master driver
  11. * Pat Gefre <[email protected]> - IOC3 serial port IRQ demuxer
  12. */
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/module.h>
  19. #include <linux/pci.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/platform_data/sgi-w1.h>
  22. #include <linux/rtc/ds1685.h>
  23. #include <asm/pci/bridge.h>
  24. #include <asm/sn/ioc3.h>
  25. #define IOC3_IRQ_SERIAL_A 6
  26. #define IOC3_IRQ_SERIAL_B 15
  27. #define IOC3_IRQ_KBD 22
  28. /* Bitmask for selecting which IRQs are level triggered */
  29. #define IOC3_LVL_MASK (BIT(IOC3_IRQ_SERIAL_A) | BIT(IOC3_IRQ_SERIAL_B))
  30. #define M48T35_REG_SIZE 32768 /* size of m48t35 registers */
  31. /* 1.2 us latency timer (40 cycles at 33 MHz) */
  32. #define IOC3_LATENCY 40
  33. struct ioc3_priv_data {
  34. struct irq_domain *domain;
  35. struct ioc3 __iomem *regs;
  36. struct pci_dev *pdev;
  37. int domain_irq;
  38. };
  39. static void ioc3_irq_ack(struct irq_data *d)
  40. {
  41. struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
  42. unsigned int hwirq = irqd_to_hwirq(d);
  43. writel(BIT(hwirq), &ipd->regs->sio_ir);
  44. }
  45. static void ioc3_irq_mask(struct irq_data *d)
  46. {
  47. struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
  48. unsigned int hwirq = irqd_to_hwirq(d);
  49. writel(BIT(hwirq), &ipd->regs->sio_iec);
  50. }
  51. static void ioc3_irq_unmask(struct irq_data *d)
  52. {
  53. struct ioc3_priv_data *ipd = irq_data_get_irq_chip_data(d);
  54. unsigned int hwirq = irqd_to_hwirq(d);
  55. writel(BIT(hwirq), &ipd->regs->sio_ies);
  56. }
  57. static struct irq_chip ioc3_irq_chip = {
  58. .name = "IOC3",
  59. .irq_ack = ioc3_irq_ack,
  60. .irq_mask = ioc3_irq_mask,
  61. .irq_unmask = ioc3_irq_unmask,
  62. };
  63. static int ioc3_irq_domain_map(struct irq_domain *d, unsigned int irq,
  64. irq_hw_number_t hwirq)
  65. {
  66. /* Set level IRQs for every interrupt contained in IOC3_LVL_MASK */
  67. if (BIT(hwirq) & IOC3_LVL_MASK)
  68. irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_level_irq);
  69. else
  70. irq_set_chip_and_handler(irq, &ioc3_irq_chip, handle_edge_irq);
  71. irq_set_chip_data(irq, d->host_data);
  72. return 0;
  73. }
  74. static void ioc3_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
  75. {
  76. irq_set_chip_and_handler(irq, NULL, NULL);
  77. irq_set_chip_data(irq, NULL);
  78. }
  79. static const struct irq_domain_ops ioc3_irq_domain_ops = {
  80. .map = ioc3_irq_domain_map,
  81. .unmap = ioc3_irq_domain_unmap,
  82. };
  83. static void ioc3_irq_handler(struct irq_desc *desc)
  84. {
  85. struct irq_domain *domain = irq_desc_get_handler_data(desc);
  86. struct ioc3_priv_data *ipd = domain->host_data;
  87. struct ioc3 __iomem *regs = ipd->regs;
  88. u32 pending, mask;
  89. pending = readl(&regs->sio_ir);
  90. mask = readl(&regs->sio_ies);
  91. pending &= mask; /* Mask off not enabled interrupts */
  92. if (pending)
  93. generic_handle_domain_irq(domain, __ffs(pending));
  94. else
  95. spurious_interrupt();
  96. }
  97. /*
  98. * System boards/BaseIOs use more interrupt pins of the bridge ASIC
  99. * to which the IOC3 is connected. Since the IOC3 MFD driver
  100. * knows wiring of these extra pins, we use the map_irq function
  101. * to get interrupts activated
  102. */
  103. static int ioc3_map_irq(struct pci_dev *pdev, int slot, int pin)
  104. {
  105. struct pci_host_bridge *hbrg = pci_find_host_bridge(pdev->bus);
  106. return hbrg->map_irq(pdev, slot, pin);
  107. }
  108. static int ioc3_irq_domain_setup(struct ioc3_priv_data *ipd, int irq)
  109. {
  110. struct irq_domain *domain;
  111. struct fwnode_handle *fn;
  112. fn = irq_domain_alloc_named_fwnode("IOC3");
  113. if (!fn)
  114. goto err;
  115. domain = irq_domain_create_linear(fn, 24, &ioc3_irq_domain_ops, ipd);
  116. if (!domain) {
  117. irq_domain_free_fwnode(fn);
  118. goto err;
  119. }
  120. ipd->domain = domain;
  121. irq_set_chained_handler_and_data(irq, ioc3_irq_handler, domain);
  122. ipd->domain_irq = irq;
  123. return 0;
  124. err:
  125. dev_err(&ipd->pdev->dev, "irq domain setup failed\n");
  126. return -ENOMEM;
  127. }
  128. static const struct resource ioc3_uarta_resources[] = {
  129. DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uarta),
  130. sizeof_field(struct ioc3, sregs.uarta)),
  131. DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_A)
  132. };
  133. static const struct resource ioc3_uartb_resources[] = {
  134. DEFINE_RES_MEM(offsetof(struct ioc3, sregs.uartb),
  135. sizeof_field(struct ioc3, sregs.uartb)),
  136. DEFINE_RES_IRQ(IOC3_IRQ_SERIAL_B)
  137. };
  138. static struct mfd_cell ioc3_serial_cells[] = {
  139. {
  140. .name = "ioc3-serial8250",
  141. .resources = ioc3_uarta_resources,
  142. .num_resources = ARRAY_SIZE(ioc3_uarta_resources),
  143. },
  144. {
  145. .name = "ioc3-serial8250",
  146. .resources = ioc3_uartb_resources,
  147. .num_resources = ARRAY_SIZE(ioc3_uartb_resources),
  148. }
  149. };
  150. static int ioc3_serial_setup(struct ioc3_priv_data *ipd)
  151. {
  152. int ret;
  153. /* Set gpio pins for RS232/RS422 mode selection */
  154. writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL,
  155. &ipd->regs->gpcr_s);
  156. /* Select RS232 mode for uart a */
  157. writel(0, &ipd->regs->gppr[6]);
  158. /* Select RS232 mode for uart b */
  159. writel(0, &ipd->regs->gppr[7]);
  160. /* Switch both ports to 16650 mode */
  161. writel(readl(&ipd->regs->port_a.sscr) & ~SSCR_DMA_EN,
  162. &ipd->regs->port_a.sscr);
  163. writel(readl(&ipd->regs->port_b.sscr) & ~SSCR_DMA_EN,
  164. &ipd->regs->port_b.sscr);
  165. udelay(1000); /* Wait until mode switch is done */
  166. ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
  167. ioc3_serial_cells, ARRAY_SIZE(ioc3_serial_cells),
  168. &ipd->pdev->resource[0], 0, ipd->domain);
  169. if (ret) {
  170. dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
  171. return ret;
  172. }
  173. return 0;
  174. }
  175. static const struct resource ioc3_kbd_resources[] = {
  176. DEFINE_RES_MEM(offsetof(struct ioc3, serio),
  177. sizeof_field(struct ioc3, serio)),
  178. DEFINE_RES_IRQ(IOC3_IRQ_KBD)
  179. };
  180. static struct mfd_cell ioc3_kbd_cells[] = {
  181. {
  182. .name = "ioc3-kbd",
  183. .resources = ioc3_kbd_resources,
  184. .num_resources = ARRAY_SIZE(ioc3_kbd_resources),
  185. }
  186. };
  187. static int ioc3_kbd_setup(struct ioc3_priv_data *ipd)
  188. {
  189. int ret;
  190. ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
  191. ioc3_kbd_cells, ARRAY_SIZE(ioc3_kbd_cells),
  192. &ipd->pdev->resource[0], 0, ipd->domain);
  193. if (ret) {
  194. dev_err(&ipd->pdev->dev, "Failed to add 16550 subdevs\n");
  195. return ret;
  196. }
  197. return 0;
  198. }
  199. static const struct resource ioc3_eth_resources[] = {
  200. DEFINE_RES_MEM(offsetof(struct ioc3, eth),
  201. sizeof_field(struct ioc3, eth)),
  202. DEFINE_RES_MEM(offsetof(struct ioc3, ssram),
  203. sizeof_field(struct ioc3, ssram)),
  204. DEFINE_RES_IRQ(0)
  205. };
  206. static const struct resource ioc3_w1_resources[] = {
  207. DEFINE_RES_MEM(offsetof(struct ioc3, mcr),
  208. sizeof_field(struct ioc3, mcr)),
  209. };
  210. static struct sgi_w1_platform_data ioc3_w1_platform_data;
  211. static struct mfd_cell ioc3_eth_cells[] = {
  212. {
  213. .name = "ioc3-eth",
  214. .resources = ioc3_eth_resources,
  215. .num_resources = ARRAY_SIZE(ioc3_eth_resources),
  216. },
  217. {
  218. .name = "sgi_w1",
  219. .resources = ioc3_w1_resources,
  220. .num_resources = ARRAY_SIZE(ioc3_w1_resources),
  221. .platform_data = &ioc3_w1_platform_data,
  222. .pdata_size = sizeof(ioc3_w1_platform_data),
  223. }
  224. };
  225. static int ioc3_eth_setup(struct ioc3_priv_data *ipd)
  226. {
  227. int ret;
  228. /* Enable One-Wire bus */
  229. writel(GPCR_MLAN_EN, &ipd->regs->gpcr_s);
  230. /* Generate unique identifier */
  231. snprintf(ioc3_w1_platform_data.dev_id,
  232. sizeof(ioc3_w1_platform_data.dev_id), "ioc3-%012llx",
  233. ipd->pdev->resource->start);
  234. ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
  235. ioc3_eth_cells, ARRAY_SIZE(ioc3_eth_cells),
  236. &ipd->pdev->resource[0], ipd->pdev->irq, NULL);
  237. if (ret) {
  238. dev_err(&ipd->pdev->dev, "Failed to add ETH/W1 subdev\n");
  239. return ret;
  240. }
  241. return 0;
  242. }
  243. static const struct resource ioc3_m48t35_resources[] = {
  244. DEFINE_RES_MEM(IOC3_BYTEBUS_DEV0, M48T35_REG_SIZE)
  245. };
  246. static struct mfd_cell ioc3_m48t35_cells[] = {
  247. {
  248. .name = "rtc-m48t35",
  249. .resources = ioc3_m48t35_resources,
  250. .num_resources = ARRAY_SIZE(ioc3_m48t35_resources),
  251. }
  252. };
  253. static int ioc3_m48t35_setup(struct ioc3_priv_data *ipd)
  254. {
  255. int ret;
  256. ret = mfd_add_devices(&ipd->pdev->dev, PLATFORM_DEVID_AUTO,
  257. ioc3_m48t35_cells, ARRAY_SIZE(ioc3_m48t35_cells),
  258. &ipd->pdev->resource[0], 0, ipd->domain);
  259. if (ret)
  260. dev_err(&ipd->pdev->dev, "Failed to add M48T35 subdev\n");
  261. return ret;
  262. }
  263. static struct ds1685_rtc_platform_data ip30_rtc_platform_data = {
  264. .bcd_mode = false,
  265. .no_irq = false,
  266. .uie_unsupported = true,
  267. .access_type = ds1685_reg_indirect,
  268. };
  269. static const struct resource ioc3_rtc_ds1685_resources[] = {
  270. DEFINE_RES_MEM(IOC3_BYTEBUS_DEV1, 1),
  271. DEFINE_RES_MEM(IOC3_BYTEBUS_DEV2, 1),
  272. DEFINE_RES_IRQ(0)
  273. };
  274. static struct mfd_cell ioc3_ds1685_cells[] = {
  275. {
  276. .name = "rtc-ds1685",
  277. .resources = ioc3_rtc_ds1685_resources,
  278. .num_resources = ARRAY_SIZE(ioc3_rtc_ds1685_resources),
  279. .platform_data = &ip30_rtc_platform_data,
  280. .pdata_size = sizeof(ip30_rtc_platform_data),
  281. .id = PLATFORM_DEVID_NONE,
  282. }
  283. };
  284. static int ioc3_ds1685_setup(struct ioc3_priv_data *ipd)
  285. {
  286. int ret, irq;
  287. irq = ioc3_map_irq(ipd->pdev, 6, 0);
  288. ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_ds1685_cells,
  289. ARRAY_SIZE(ioc3_ds1685_cells),
  290. &ipd->pdev->resource[0], irq, NULL);
  291. if (ret)
  292. dev_err(&ipd->pdev->dev, "Failed to add DS1685 subdev\n");
  293. return ret;
  294. };
  295. static const struct resource ioc3_leds_resources[] = {
  296. DEFINE_RES_MEM(offsetof(struct ioc3, gppr[0]),
  297. sizeof_field(struct ioc3, gppr[0])),
  298. DEFINE_RES_MEM(offsetof(struct ioc3, gppr[1]),
  299. sizeof_field(struct ioc3, gppr[1])),
  300. };
  301. static struct mfd_cell ioc3_led_cells[] = {
  302. {
  303. .name = "ip30-leds",
  304. .resources = ioc3_leds_resources,
  305. .num_resources = ARRAY_SIZE(ioc3_leds_resources),
  306. .id = PLATFORM_DEVID_NONE,
  307. }
  308. };
  309. static int ioc3_led_setup(struct ioc3_priv_data *ipd)
  310. {
  311. int ret;
  312. ret = mfd_add_devices(&ipd->pdev->dev, 0, ioc3_led_cells,
  313. ARRAY_SIZE(ioc3_led_cells),
  314. &ipd->pdev->resource[0], 0, ipd->domain);
  315. if (ret)
  316. dev_err(&ipd->pdev->dev, "Failed to add LED subdev\n");
  317. return ret;
  318. }
  319. static int ip27_baseio_setup(struct ioc3_priv_data *ipd)
  320. {
  321. int ret, io_irq;
  322. io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
  323. PCI_INTERRUPT_INTB);
  324. ret = ioc3_irq_domain_setup(ipd, io_irq);
  325. if (ret)
  326. return ret;
  327. ret = ioc3_eth_setup(ipd);
  328. if (ret)
  329. return ret;
  330. ret = ioc3_serial_setup(ipd);
  331. if (ret)
  332. return ret;
  333. return ioc3_m48t35_setup(ipd);
  334. }
  335. static int ip27_baseio6g_setup(struct ioc3_priv_data *ipd)
  336. {
  337. int ret, io_irq;
  338. io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
  339. PCI_INTERRUPT_INTB);
  340. ret = ioc3_irq_domain_setup(ipd, io_irq);
  341. if (ret)
  342. return ret;
  343. ret = ioc3_eth_setup(ipd);
  344. if (ret)
  345. return ret;
  346. ret = ioc3_serial_setup(ipd);
  347. if (ret)
  348. return ret;
  349. ret = ioc3_m48t35_setup(ipd);
  350. if (ret)
  351. return ret;
  352. return ioc3_kbd_setup(ipd);
  353. }
  354. static int ip27_mio_setup(struct ioc3_priv_data *ipd)
  355. {
  356. int ret;
  357. ret = ioc3_irq_domain_setup(ipd, ipd->pdev->irq);
  358. if (ret)
  359. return ret;
  360. ret = ioc3_serial_setup(ipd);
  361. if (ret)
  362. return ret;
  363. return ioc3_kbd_setup(ipd);
  364. }
  365. static int ip30_sysboard_setup(struct ioc3_priv_data *ipd)
  366. {
  367. int ret, io_irq;
  368. io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
  369. PCI_INTERRUPT_INTB);
  370. ret = ioc3_irq_domain_setup(ipd, io_irq);
  371. if (ret)
  372. return ret;
  373. ret = ioc3_eth_setup(ipd);
  374. if (ret)
  375. return ret;
  376. ret = ioc3_serial_setup(ipd);
  377. if (ret)
  378. return ret;
  379. ret = ioc3_kbd_setup(ipd);
  380. if (ret)
  381. return ret;
  382. ret = ioc3_ds1685_setup(ipd);
  383. if (ret)
  384. return ret;
  385. return ioc3_led_setup(ipd);
  386. }
  387. static int ioc3_menet_setup(struct ioc3_priv_data *ipd)
  388. {
  389. int ret, io_irq;
  390. io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
  391. PCI_INTERRUPT_INTB);
  392. ret = ioc3_irq_domain_setup(ipd, io_irq);
  393. if (ret)
  394. return ret;
  395. ret = ioc3_eth_setup(ipd);
  396. if (ret)
  397. return ret;
  398. return ioc3_serial_setup(ipd);
  399. }
  400. static int ioc3_menet4_setup(struct ioc3_priv_data *ipd)
  401. {
  402. return ioc3_eth_setup(ipd);
  403. }
  404. static int ioc3_cad_duo_setup(struct ioc3_priv_data *ipd)
  405. {
  406. int ret, io_irq;
  407. io_irq = ioc3_map_irq(ipd->pdev, PCI_SLOT(ipd->pdev->devfn),
  408. PCI_INTERRUPT_INTB);
  409. ret = ioc3_irq_domain_setup(ipd, io_irq);
  410. if (ret)
  411. return ret;
  412. ret = ioc3_eth_setup(ipd);
  413. if (ret)
  414. return ret;
  415. return ioc3_kbd_setup(ipd);
  416. }
  417. /* Helper macro for filling ioc3_info array */
  418. #define IOC3_SID(_name, _sid, _setup) \
  419. { \
  420. .name = _name, \
  421. .sid = PCI_VENDOR_ID_SGI | (IOC3_SUBSYS_ ## _sid << 16), \
  422. .setup = _setup, \
  423. }
  424. static struct {
  425. const char *name;
  426. u32 sid;
  427. int (*setup)(struct ioc3_priv_data *ipd);
  428. } ioc3_infos[] = {
  429. IOC3_SID("IP27 BaseIO6G", IP27_BASEIO6G, &ip27_baseio6g_setup),
  430. IOC3_SID("IP27 MIO", IP27_MIO, &ip27_mio_setup),
  431. IOC3_SID("IP27 BaseIO", IP27_BASEIO, &ip27_baseio_setup),
  432. IOC3_SID("IP29 System Board", IP29_SYSBOARD, &ip27_baseio6g_setup),
  433. IOC3_SID("IP30 System Board", IP30_SYSBOARD, &ip30_sysboard_setup),
  434. IOC3_SID("MENET", MENET, &ioc3_menet_setup),
  435. IOC3_SID("MENET4", MENET4, &ioc3_menet4_setup)
  436. };
  437. #undef IOC3_SID
  438. static int ioc3_setup(struct ioc3_priv_data *ipd)
  439. {
  440. u32 sid;
  441. int i;
  442. /* Clear IRQs */
  443. writel(~0, &ipd->regs->sio_iec);
  444. writel(~0, &ipd->regs->sio_ir);
  445. writel(0, &ipd->regs->eth.eier);
  446. writel(~0, &ipd->regs->eth.eisr);
  447. /* Read subsystem vendor id and subsystem id */
  448. pci_read_config_dword(ipd->pdev, PCI_SUBSYSTEM_VENDOR_ID, &sid);
  449. for (i = 0; i < ARRAY_SIZE(ioc3_infos); i++)
  450. if (sid == ioc3_infos[i].sid) {
  451. pr_info("ioc3: %s\n", ioc3_infos[i].name);
  452. return ioc3_infos[i].setup(ipd);
  453. }
  454. /* Treat everything not identified by PCI subid as CAD DUO */
  455. pr_info("ioc3: CAD DUO\n");
  456. return ioc3_cad_duo_setup(ipd);
  457. }
  458. static int ioc3_mfd_probe(struct pci_dev *pdev,
  459. const struct pci_device_id *pci_id)
  460. {
  461. struct ioc3_priv_data *ipd;
  462. struct ioc3 __iomem *regs;
  463. int ret;
  464. ret = pci_enable_device(pdev);
  465. if (ret)
  466. return ret;
  467. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, IOC3_LATENCY);
  468. pci_set_master(pdev);
  469. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
  470. if (ret) {
  471. pr_err("%s: No usable DMA configuration, aborting.\n",
  472. pci_name(pdev));
  473. goto out_disable_device;
  474. }
  475. /* Set up per-IOC3 data */
  476. ipd = devm_kzalloc(&pdev->dev, sizeof(struct ioc3_priv_data),
  477. GFP_KERNEL);
  478. if (!ipd) {
  479. ret = -ENOMEM;
  480. goto out_disable_device;
  481. }
  482. ipd->pdev = pdev;
  483. /*
  484. * Map all IOC3 registers. These are shared between subdevices
  485. * so the main IOC3 module manages them.
  486. */
  487. regs = pci_ioremap_bar(pdev, 0);
  488. if (!regs) {
  489. dev_warn(&pdev->dev, "ioc3: Unable to remap PCI BAR for %s.\n",
  490. pci_name(pdev));
  491. ret = -ENOMEM;
  492. goto out_disable_device;
  493. }
  494. ipd->regs = regs;
  495. /* Track PCI-device specific data */
  496. pci_set_drvdata(pdev, ipd);
  497. ret = ioc3_setup(ipd);
  498. if (ret) {
  499. /* Remove all already added MFD devices */
  500. mfd_remove_devices(&ipd->pdev->dev);
  501. if (ipd->domain) {
  502. struct fwnode_handle *fn = ipd->domain->fwnode;
  503. irq_domain_remove(ipd->domain);
  504. irq_domain_free_fwnode(fn);
  505. free_irq(ipd->domain_irq, (void *)ipd);
  506. }
  507. pci_iounmap(pdev, regs);
  508. goto out_disable_device;
  509. }
  510. return 0;
  511. out_disable_device:
  512. pci_disable_device(pdev);
  513. return ret;
  514. }
  515. static void ioc3_mfd_remove(struct pci_dev *pdev)
  516. {
  517. struct ioc3_priv_data *ipd;
  518. ipd = pci_get_drvdata(pdev);
  519. /* Clear and disable all IRQs */
  520. writel(~0, &ipd->regs->sio_iec);
  521. writel(~0, &ipd->regs->sio_ir);
  522. /* Release resources */
  523. mfd_remove_devices(&ipd->pdev->dev);
  524. if (ipd->domain) {
  525. struct fwnode_handle *fn = ipd->domain->fwnode;
  526. irq_domain_remove(ipd->domain);
  527. irq_domain_free_fwnode(fn);
  528. free_irq(ipd->domain_irq, (void *)ipd);
  529. }
  530. pci_iounmap(pdev, ipd->regs);
  531. pci_disable_device(pdev);
  532. }
  533. static struct pci_device_id ioc3_mfd_id_table[] = {
  534. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
  535. { 0, },
  536. };
  537. MODULE_DEVICE_TABLE(pci, ioc3_mfd_id_table);
  538. static struct pci_driver ioc3_mfd_driver = {
  539. .name = "IOC3",
  540. .id_table = ioc3_mfd_id_table,
  541. .probe = ioc3_mfd_probe,
  542. .remove = ioc3_mfd_remove,
  543. };
  544. module_pci_driver(ioc3_mfd_driver);
  545. MODULE_AUTHOR("Thomas Bogendoerfer <[email protected]>");
  546. MODULE_DESCRIPTION("SGI IOC3 MFD driver");
  547. MODULE_LICENSE("GPL v2");