gpio-tegra.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mach-tegra/gpio.c
  4. *
  5. * Copyright (c) 2010 Google, Inc
  6. * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
  7. *
  8. * Author:
  9. * Erik Gilling <[email protected]>
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/irq.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/gpio/driver.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/module.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/irqdomain.h>
  22. #include <linux/irqchip/chained_irq.h>
  23. #include <linux/pinctrl/consumer.h>
  24. #include <linux/pm.h>
  25. #define GPIO_BANK(x) ((x) >> 5)
  26. #define GPIO_PORT(x) (((x) >> 3) & 0x3)
  27. #define GPIO_BIT(x) ((x) & 0x7)
  28. #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
  29. GPIO_PORT(x) * 4)
  30. #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
  31. #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
  32. #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
  33. #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
  34. #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
  35. #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
  36. #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
  37. #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
  38. #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
  39. #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
  40. #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
  41. #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
  42. #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
  43. #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
  44. #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
  45. #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
  46. #define GPIO_INT_LVL_MASK 0x010101
  47. #define GPIO_INT_LVL_EDGE_RISING 0x000101
  48. #define GPIO_INT_LVL_EDGE_FALLING 0x000100
  49. #define GPIO_INT_LVL_EDGE_BOTH 0x010100
  50. #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
  51. #define GPIO_INT_LVL_LEVEL_LOW 0x000000
  52. struct tegra_gpio_info;
  53. struct tegra_gpio_bank {
  54. unsigned int bank;
  55. /*
  56. * IRQ-core code uses raw locking, and thus, nested locking also
  57. * should be raw in order not to trip spinlock debug warnings.
  58. */
  59. raw_spinlock_t lvl_lock[4];
  60. /* Lock for updating debounce count register */
  61. spinlock_t dbc_lock[4];
  62. #ifdef CONFIG_PM_SLEEP
  63. u32 cnf[4];
  64. u32 out[4];
  65. u32 oe[4];
  66. u32 int_enb[4];
  67. u32 int_lvl[4];
  68. u32 wake_enb[4];
  69. u32 dbc_enb[4];
  70. #endif
  71. u32 dbc_cnt[4];
  72. };
  73. struct tegra_gpio_soc_config {
  74. bool debounce_supported;
  75. u32 bank_stride;
  76. u32 upper_offset;
  77. };
  78. struct tegra_gpio_info {
  79. struct device *dev;
  80. void __iomem *regs;
  81. struct tegra_gpio_bank *bank_info;
  82. const struct tegra_gpio_soc_config *soc;
  83. struct gpio_chip gc;
  84. u32 bank_count;
  85. unsigned int *irqs;
  86. };
  87. static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
  88. u32 val, u32 reg)
  89. {
  90. writel_relaxed(val, tgi->regs + reg);
  91. }
  92. static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
  93. {
  94. return readl_relaxed(tgi->regs + reg);
  95. }
  96. static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
  97. unsigned int bit)
  98. {
  99. return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  100. }
  101. static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
  102. unsigned int gpio, u32 value)
  103. {
  104. u32 val;
  105. val = 0x100 << GPIO_BIT(gpio);
  106. if (value)
  107. val |= 1 << GPIO_BIT(gpio);
  108. tegra_gpio_writel(tgi, val, reg);
  109. }
  110. static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
  111. {
  112. tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
  113. }
  114. static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
  115. {
  116. tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
  117. }
  118. static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
  119. {
  120. return pinctrl_gpio_request(chip->base + offset);
  121. }
  122. static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
  123. {
  124. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  125. pinctrl_gpio_free(chip->base + offset);
  126. tegra_gpio_disable(tgi, offset);
  127. }
  128. static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
  129. int value)
  130. {
  131. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  132. tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
  133. }
  134. static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
  135. {
  136. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  137. unsigned int bval = BIT(GPIO_BIT(offset));
  138. /* If gpio is in output mode then read from the out value */
  139. if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
  140. return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
  141. return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
  142. }
  143. static int tegra_gpio_direction_input(struct gpio_chip *chip,
  144. unsigned int offset)
  145. {
  146. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  147. int ret;
  148. tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
  149. tegra_gpio_enable(tgi, offset);
  150. ret = pinctrl_gpio_direction_input(chip->base + offset);
  151. if (ret < 0)
  152. dev_err(tgi->dev,
  153. "Failed to set pinctrl input direction of GPIO %d: %d",
  154. chip->base + offset, ret);
  155. return ret;
  156. }
  157. static int tegra_gpio_direction_output(struct gpio_chip *chip,
  158. unsigned int offset,
  159. int value)
  160. {
  161. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  162. int ret;
  163. tegra_gpio_set(chip, offset, value);
  164. tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
  165. tegra_gpio_enable(tgi, offset);
  166. ret = pinctrl_gpio_direction_output(chip->base + offset);
  167. if (ret < 0)
  168. dev_err(tgi->dev,
  169. "Failed to set pinctrl output direction of GPIO %d: %d",
  170. chip->base + offset, ret);
  171. return ret;
  172. }
  173. static int tegra_gpio_get_direction(struct gpio_chip *chip,
  174. unsigned int offset)
  175. {
  176. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  177. u32 pin_mask = BIT(GPIO_BIT(offset));
  178. u32 cnf, oe;
  179. cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
  180. if (!(cnf & pin_mask))
  181. return -EINVAL;
  182. oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
  183. if (oe & pin_mask)
  184. return GPIO_LINE_DIRECTION_OUT;
  185. return GPIO_LINE_DIRECTION_IN;
  186. }
  187. static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
  188. unsigned int debounce)
  189. {
  190. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  191. struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
  192. unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
  193. unsigned long flags;
  194. unsigned int port;
  195. if (!debounce_ms) {
  196. tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
  197. offset, 0);
  198. return 0;
  199. }
  200. debounce_ms = min(debounce_ms, 255U);
  201. port = GPIO_PORT(offset);
  202. /* There is only one debounce count register per port and hence
  203. * set the maximum of current and requested debounce time.
  204. */
  205. spin_lock_irqsave(&bank->dbc_lock[port], flags);
  206. if (bank->dbc_cnt[port] < debounce_ms) {
  207. tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
  208. bank->dbc_cnt[port] = debounce_ms;
  209. }
  210. spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
  211. tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
  212. return 0;
  213. }
  214. static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  215. unsigned long config)
  216. {
  217. u32 debounce;
  218. if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
  219. return -ENOTSUPP;
  220. debounce = pinconf_to_config_argument(config);
  221. return tegra_gpio_set_debounce(chip, offset, debounce);
  222. }
  223. static void tegra_gpio_irq_ack(struct irq_data *d)
  224. {
  225. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  226. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  227. unsigned int gpio = d->hwirq;
  228. tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
  229. }
  230. static void tegra_gpio_irq_mask(struct irq_data *d)
  231. {
  232. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  233. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  234. unsigned int gpio = d->hwirq;
  235. tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
  236. gpiochip_disable_irq(chip, gpio);
  237. }
  238. static void tegra_gpio_irq_unmask(struct irq_data *d)
  239. {
  240. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  241. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  242. unsigned int gpio = d->hwirq;
  243. gpiochip_enable_irq(chip, gpio);
  244. tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
  245. }
  246. static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  247. {
  248. unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
  249. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  250. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  251. struct tegra_gpio_bank *bank;
  252. unsigned long flags;
  253. int ret;
  254. u32 val;
  255. bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
  256. switch (type & IRQ_TYPE_SENSE_MASK) {
  257. case IRQ_TYPE_EDGE_RISING:
  258. lvl_type = GPIO_INT_LVL_EDGE_RISING;
  259. break;
  260. case IRQ_TYPE_EDGE_FALLING:
  261. lvl_type = GPIO_INT_LVL_EDGE_FALLING;
  262. break;
  263. case IRQ_TYPE_EDGE_BOTH:
  264. lvl_type = GPIO_INT_LVL_EDGE_BOTH;
  265. break;
  266. case IRQ_TYPE_LEVEL_HIGH:
  267. lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
  268. break;
  269. case IRQ_TYPE_LEVEL_LOW:
  270. lvl_type = GPIO_INT_LVL_LEVEL_LOW;
  271. break;
  272. default:
  273. return -EINVAL;
  274. }
  275. raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
  276. val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
  277. val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
  278. val |= lvl_type << GPIO_BIT(gpio);
  279. tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
  280. raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
  281. tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
  282. tegra_gpio_enable(tgi, gpio);
  283. ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
  284. if (ret) {
  285. dev_err(tgi->dev,
  286. "unable to lock Tegra GPIO %u as IRQ\n", gpio);
  287. tegra_gpio_disable(tgi, gpio);
  288. return ret;
  289. }
  290. if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  291. irq_set_handler_locked(d, handle_level_irq);
  292. else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
  293. irq_set_handler_locked(d, handle_edge_irq);
  294. if (d->parent_data)
  295. ret = irq_chip_set_type_parent(d, type);
  296. return ret;
  297. }
  298. static void tegra_gpio_irq_shutdown(struct irq_data *d)
  299. {
  300. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  301. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  302. unsigned int gpio = d->hwirq;
  303. tegra_gpio_irq_mask(d);
  304. gpiochip_unlock_as_irq(&tgi->gc, gpio);
  305. }
  306. static void tegra_gpio_irq_handler(struct irq_desc *desc)
  307. {
  308. struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
  309. struct irq_chip *chip = irq_desc_get_chip(desc);
  310. struct irq_domain *domain = tgi->gc.irq.domain;
  311. unsigned int irq = irq_desc_get_irq(desc);
  312. struct tegra_gpio_bank *bank = NULL;
  313. unsigned int port, pin, gpio, i;
  314. bool unmasked = false;
  315. unsigned long sta;
  316. u32 lvl;
  317. for (i = 0; i < tgi->bank_count; i++) {
  318. if (tgi->irqs[i] == irq) {
  319. bank = &tgi->bank_info[i];
  320. break;
  321. }
  322. }
  323. if (WARN_ON(bank == NULL))
  324. return;
  325. chained_irq_enter(chip, desc);
  326. for (port = 0; port < 4; port++) {
  327. gpio = tegra_gpio_compose(bank->bank, port, 0);
  328. sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
  329. tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
  330. lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
  331. for_each_set_bit(pin, &sta, 8) {
  332. int ret;
  333. tegra_gpio_writel(tgi, 1 << pin,
  334. GPIO_INT_CLR(tgi, gpio));
  335. /* if gpio is edge triggered, clear condition
  336. * before executing the handler so that we don't
  337. * miss edges
  338. */
  339. if (!unmasked && lvl & (0x100 << pin)) {
  340. unmasked = true;
  341. chained_irq_exit(chip, desc);
  342. }
  343. ret = generic_handle_domain_irq(domain, gpio + pin);
  344. WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
  345. }
  346. }
  347. if (!unmasked)
  348. chained_irq_exit(chip, desc);
  349. }
  350. static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
  351. unsigned int hwirq,
  352. unsigned int type,
  353. unsigned int *parent_hwirq,
  354. unsigned int *parent_type)
  355. {
  356. *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
  357. *parent_type = type;
  358. return 0;
  359. }
  360. static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
  361. union gpio_irq_fwspec *gfwspec,
  362. unsigned int parent_hwirq,
  363. unsigned int parent_type)
  364. {
  365. struct irq_fwspec *fwspec = &gfwspec->fwspec;
  366. fwspec->fwnode = chip->irq.parent_domain->fwnode;
  367. fwspec->param_count = 3;
  368. fwspec->param[0] = 0;
  369. fwspec->param[1] = parent_hwirq;
  370. fwspec->param[2] = parent_type;
  371. return 0;
  372. }
  373. #ifdef CONFIG_PM_SLEEP
  374. static int tegra_gpio_resume(struct device *dev)
  375. {
  376. struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
  377. unsigned int b, p;
  378. for (b = 0; b < tgi->bank_count; b++) {
  379. struct tegra_gpio_bank *bank = &tgi->bank_info[b];
  380. for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
  381. unsigned int gpio = (b << 5) | (p << 3);
  382. tegra_gpio_writel(tgi, bank->cnf[p],
  383. GPIO_CNF(tgi, gpio));
  384. if (tgi->soc->debounce_supported) {
  385. tegra_gpio_writel(tgi, bank->dbc_cnt[p],
  386. GPIO_DBC_CNT(tgi, gpio));
  387. tegra_gpio_writel(tgi, bank->dbc_enb[p],
  388. GPIO_MSK_DBC_EN(tgi, gpio));
  389. }
  390. tegra_gpio_writel(tgi, bank->out[p],
  391. GPIO_OUT(tgi, gpio));
  392. tegra_gpio_writel(tgi, bank->oe[p],
  393. GPIO_OE(tgi, gpio));
  394. tegra_gpio_writel(tgi, bank->int_lvl[p],
  395. GPIO_INT_LVL(tgi, gpio));
  396. tegra_gpio_writel(tgi, bank->int_enb[p],
  397. GPIO_INT_ENB(tgi, gpio));
  398. }
  399. }
  400. return 0;
  401. }
  402. static int tegra_gpio_suspend(struct device *dev)
  403. {
  404. struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
  405. unsigned int b, p;
  406. for (b = 0; b < tgi->bank_count; b++) {
  407. struct tegra_gpio_bank *bank = &tgi->bank_info[b];
  408. for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
  409. unsigned int gpio = (b << 5) | (p << 3);
  410. bank->cnf[p] = tegra_gpio_readl(tgi,
  411. GPIO_CNF(tgi, gpio));
  412. bank->out[p] = tegra_gpio_readl(tgi,
  413. GPIO_OUT(tgi, gpio));
  414. bank->oe[p] = tegra_gpio_readl(tgi,
  415. GPIO_OE(tgi, gpio));
  416. if (tgi->soc->debounce_supported) {
  417. bank->dbc_enb[p] = tegra_gpio_readl(tgi,
  418. GPIO_MSK_DBC_EN(tgi, gpio));
  419. bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
  420. bank->dbc_enb[p];
  421. }
  422. bank->int_enb[p] = tegra_gpio_readl(tgi,
  423. GPIO_INT_ENB(tgi, gpio));
  424. bank->int_lvl[p] = tegra_gpio_readl(tgi,
  425. GPIO_INT_LVL(tgi, gpio));
  426. /* Enable gpio irq for wake up source */
  427. tegra_gpio_writel(tgi, bank->wake_enb[p],
  428. GPIO_INT_ENB(tgi, gpio));
  429. }
  430. }
  431. return 0;
  432. }
  433. static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
  434. {
  435. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  436. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  437. struct tegra_gpio_bank *bank;
  438. unsigned int gpio = d->hwirq;
  439. u32 port, bit, mask;
  440. int err;
  441. bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
  442. port = GPIO_PORT(gpio);
  443. bit = GPIO_BIT(gpio);
  444. mask = BIT(bit);
  445. err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
  446. if (err)
  447. return err;
  448. if (d->parent_data) {
  449. err = irq_chip_set_wake_parent(d, enable);
  450. if (err) {
  451. irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
  452. return err;
  453. }
  454. }
  455. if (enable)
  456. bank->wake_enb[port] |= mask;
  457. else
  458. bank->wake_enb[port] &= ~mask;
  459. return 0;
  460. }
  461. #endif
  462. static int tegra_gpio_irq_set_affinity(struct irq_data *data,
  463. const struct cpumask *dest,
  464. bool force)
  465. {
  466. if (data->parent_data)
  467. return irq_chip_set_affinity_parent(data, dest, force);
  468. return -EINVAL;
  469. }
  470. static int tegra_gpio_irq_request_resources(struct irq_data *d)
  471. {
  472. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  473. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  474. tegra_gpio_enable(tgi, d->hwirq);
  475. return gpiochip_reqres_irq(chip, d->hwirq);
  476. }
  477. static void tegra_gpio_irq_release_resources(struct irq_data *d)
  478. {
  479. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  480. struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
  481. gpiochip_relres_irq(chip, d->hwirq);
  482. tegra_gpio_enable(tgi, d->hwirq);
  483. }
  484. static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
  485. {
  486. struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  487. seq_printf(s, dev_name(chip->parent));
  488. }
  489. static const struct irq_chip tegra_gpio_irq_chip = {
  490. .irq_shutdown = tegra_gpio_irq_shutdown,
  491. .irq_ack = tegra_gpio_irq_ack,
  492. .irq_mask = tegra_gpio_irq_mask,
  493. .irq_unmask = tegra_gpio_irq_unmask,
  494. .irq_set_type = tegra_gpio_irq_set_type,
  495. #ifdef CONFIG_PM_SLEEP
  496. .irq_set_wake = tegra_gpio_irq_set_wake,
  497. #endif
  498. .irq_print_chip = tegra_gpio_irq_print_chip,
  499. .irq_request_resources = tegra_gpio_irq_request_resources,
  500. .irq_release_resources = tegra_gpio_irq_release_resources,
  501. .flags = IRQCHIP_IMMUTABLE,
  502. };
  503. static const struct irq_chip tegra210_gpio_irq_chip = {
  504. .irq_shutdown = tegra_gpio_irq_shutdown,
  505. .irq_ack = tegra_gpio_irq_ack,
  506. .irq_mask = tegra_gpio_irq_mask,
  507. .irq_unmask = tegra_gpio_irq_unmask,
  508. .irq_set_affinity = tegra_gpio_irq_set_affinity,
  509. .irq_set_type = tegra_gpio_irq_set_type,
  510. #ifdef CONFIG_PM_SLEEP
  511. .irq_set_wake = tegra_gpio_irq_set_wake,
  512. #endif
  513. .irq_print_chip = tegra_gpio_irq_print_chip,
  514. .irq_request_resources = tegra_gpio_irq_request_resources,
  515. .irq_release_resources = tegra_gpio_irq_release_resources,
  516. .flags = IRQCHIP_IMMUTABLE,
  517. };
  518. #ifdef CONFIG_DEBUG_FS
  519. #include <linux/debugfs.h>
  520. static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
  521. {
  522. struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
  523. unsigned int i, j;
  524. for (i = 0; i < tgi->bank_count; i++) {
  525. for (j = 0; j < 4; j++) {
  526. unsigned int gpio = tegra_gpio_compose(i, j, 0);
  527. seq_printf(s,
  528. "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
  529. i, j,
  530. tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
  531. tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
  532. tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
  533. tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
  534. tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
  535. tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
  536. tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
  537. }
  538. }
  539. return 0;
  540. }
  541. static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
  542. {
  543. debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
  544. tegra_dbg_gpio_show);
  545. }
  546. #else
  547. static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
  548. {
  549. }
  550. #endif
  551. static const struct dev_pm_ops tegra_gpio_pm_ops = {
  552. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
  553. };
  554. static const struct of_device_id tegra_pmc_of_match[] = {
  555. { .compatible = "nvidia,tegra210-pmc", },
  556. { /* sentinel */ },
  557. };
  558. static int tegra_gpio_probe(struct platform_device *pdev)
  559. {
  560. struct tegra_gpio_bank *bank;
  561. struct tegra_gpio_info *tgi;
  562. struct gpio_irq_chip *irq;
  563. struct device_node *np;
  564. unsigned int i, j;
  565. int ret;
  566. tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
  567. if (!tgi)
  568. return -ENODEV;
  569. tgi->soc = of_device_get_match_data(&pdev->dev);
  570. tgi->dev = &pdev->dev;
  571. ret = platform_irq_count(pdev);
  572. if (ret < 0)
  573. return ret;
  574. tgi->bank_count = ret;
  575. if (!tgi->bank_count) {
  576. dev_err(&pdev->dev, "Missing IRQ resource\n");
  577. return -ENODEV;
  578. }
  579. tgi->gc.label = "tegra-gpio";
  580. tgi->gc.request = tegra_gpio_request;
  581. tgi->gc.free = tegra_gpio_free;
  582. tgi->gc.direction_input = tegra_gpio_direction_input;
  583. tgi->gc.get = tegra_gpio_get;
  584. tgi->gc.direction_output = tegra_gpio_direction_output;
  585. tgi->gc.set = tegra_gpio_set;
  586. tgi->gc.get_direction = tegra_gpio_get_direction;
  587. tgi->gc.base = 0;
  588. tgi->gc.ngpio = tgi->bank_count * 32;
  589. tgi->gc.parent = &pdev->dev;
  590. platform_set_drvdata(pdev, tgi);
  591. if (tgi->soc->debounce_supported)
  592. tgi->gc.set_config = tegra_gpio_set_config;
  593. tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
  594. sizeof(*tgi->bank_info), GFP_KERNEL);
  595. if (!tgi->bank_info)
  596. return -ENOMEM;
  597. tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
  598. sizeof(*tgi->irqs), GFP_KERNEL);
  599. if (!tgi->irqs)
  600. return -ENOMEM;
  601. for (i = 0; i < tgi->bank_count; i++) {
  602. ret = platform_get_irq(pdev, i);
  603. if (ret < 0)
  604. return ret;
  605. bank = &tgi->bank_info[i];
  606. bank->bank = i;
  607. tgi->irqs[i] = ret;
  608. for (j = 0; j < 4; j++) {
  609. raw_spin_lock_init(&bank->lvl_lock[j]);
  610. spin_lock_init(&bank->dbc_lock[j]);
  611. }
  612. }
  613. irq = &tgi->gc.irq;
  614. irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
  615. irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
  616. irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
  617. irq->handler = handle_simple_irq;
  618. irq->default_type = IRQ_TYPE_NONE;
  619. irq->parent_handler = tegra_gpio_irq_handler;
  620. irq->parent_handler_data = tgi;
  621. irq->num_parents = tgi->bank_count;
  622. irq->parents = tgi->irqs;
  623. np = of_find_matching_node(NULL, tegra_pmc_of_match);
  624. if (np) {
  625. irq->parent_domain = irq_find_host(np);
  626. of_node_put(np);
  627. if (!irq->parent_domain)
  628. return -EPROBE_DEFER;
  629. gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip);
  630. } else {
  631. gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip);
  632. }
  633. tgi->regs = devm_platform_ioremap_resource(pdev, 0);
  634. if (IS_ERR(tgi->regs))
  635. return PTR_ERR(tgi->regs);
  636. for (i = 0; i < tgi->bank_count; i++) {
  637. for (j = 0; j < 4; j++) {
  638. int gpio = tegra_gpio_compose(i, j, 0);
  639. tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
  640. }
  641. }
  642. ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
  643. if (ret < 0)
  644. return ret;
  645. tegra_gpio_debuginit(tgi);
  646. return 0;
  647. }
  648. static const struct tegra_gpio_soc_config tegra20_gpio_config = {
  649. .bank_stride = 0x80,
  650. .upper_offset = 0x800,
  651. };
  652. static const struct tegra_gpio_soc_config tegra30_gpio_config = {
  653. .bank_stride = 0x100,
  654. .upper_offset = 0x80,
  655. };
  656. static const struct tegra_gpio_soc_config tegra210_gpio_config = {
  657. .debounce_supported = true,
  658. .bank_stride = 0x100,
  659. .upper_offset = 0x80,
  660. };
  661. static const struct of_device_id tegra_gpio_of_match[] = {
  662. { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
  663. { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
  664. { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
  665. { },
  666. };
  667. MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
  668. static struct platform_driver tegra_gpio_driver = {
  669. .driver = {
  670. .name = "tegra-gpio",
  671. .pm = &tegra_gpio_pm_ops,
  672. .of_match_table = tegra_gpio_of_match,
  673. },
  674. .probe = tegra_gpio_probe,
  675. };
  676. module_platform_driver(tegra_gpio_driver);
  677. MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
  678. MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
  679. MODULE_AUTHOR("Stephen Warren <[email protected]>");
  680. MODULE_AUTHOR("Thierry Reding <[email protected]>");
  681. MODULE_AUTHOR("Erik Gilling <[email protected]>");
  682. MODULE_LICENSE("GPL v2");