gpio-rcar.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas R-Car GPIO Support
  4. *
  5. * Copyright (C) 2014 Renesas Electronics Corporation
  6. * Copyright (C) 2013 Magnus Damm
  7. */
  8. #include <linux/err.h>
  9. #include <linux/gpio/driver.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/ioport.h>
  14. #include <linux/irq.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/pinctrl/consumer.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/slab.h>
  23. struct gpio_rcar_bank_info {
  24. u32 iointsel;
  25. u32 inoutsel;
  26. u32 outdt;
  27. u32 posneg;
  28. u32 edglevel;
  29. u32 bothedge;
  30. u32 intmsk;
  31. };
  32. struct gpio_rcar_info {
  33. bool has_outdtsel;
  34. bool has_both_edge_trigger;
  35. bool has_always_in;
  36. bool has_inen;
  37. };
  38. struct gpio_rcar_priv {
  39. void __iomem *base;
  40. spinlock_t lock;
  41. struct device *dev;
  42. struct gpio_chip gpio_chip;
  43. unsigned int irq_parent;
  44. atomic_t wakeup_path;
  45. struct gpio_rcar_info info;
  46. struct gpio_rcar_bank_info bank_info;
  47. };
  48. #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
  49. #define INOUTSEL 0x04 /* General Input/Output Switching Register */
  50. #define OUTDT 0x08 /* General Output Register */
  51. #define INDT 0x0c /* General Input Register */
  52. #define INTDT 0x10 /* Interrupt Display Register */
  53. #define INTCLR 0x14 /* Interrupt Clear Register */
  54. #define INTMSK 0x18 /* Interrupt Mask Register */
  55. #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
  56. #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
  57. #define EDGLEVEL 0x24 /* Edge/level Select Register */
  58. #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
  59. #define OUTDTSEL 0x40 /* Output Data Select Register */
  60. #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
  61. #define INEN 0x50 /* General Input Enable Register */
  62. #define RCAR_MAX_GPIO_PER_BANK 32
  63. static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  64. {
  65. return ioread32(p->base + offs);
  66. }
  67. static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  68. u32 value)
  69. {
  70. iowrite32(value, p->base + offs);
  71. }
  72. static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  73. int bit, bool value)
  74. {
  75. u32 tmp = gpio_rcar_read(p, offs);
  76. if (value)
  77. tmp |= BIT(bit);
  78. else
  79. tmp &= ~BIT(bit);
  80. gpio_rcar_write(p, offs, tmp);
  81. }
  82. static void gpio_rcar_irq_disable(struct irq_data *d)
  83. {
  84. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  85. struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  86. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  87. gpio_rcar_write(p, INTMSK, ~BIT(hwirq));
  88. gpiochip_disable_irq(gc, hwirq);
  89. }
  90. static void gpio_rcar_irq_enable(struct irq_data *d)
  91. {
  92. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  93. struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  94. irq_hw_number_t hwirq = irqd_to_hwirq(d);
  95. gpiochip_enable_irq(gc, hwirq);
  96. gpio_rcar_write(p, MSKCLR, BIT(hwirq));
  97. }
  98. static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
  99. unsigned int hwirq,
  100. bool active_high_rising_edge,
  101. bool level_trigger,
  102. bool both)
  103. {
  104. unsigned long flags;
  105. /* follow steps in the GPIO documentation for
  106. * "Setting Edge-Sensitive Interrupt Input Mode" and
  107. * "Setting Level-Sensitive Interrupt Input Mode"
  108. */
  109. spin_lock_irqsave(&p->lock, flags);
  110. /* Configure positive or negative logic in POSNEG */
  111. gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
  112. /* Configure edge or level trigger in EDGLEVEL */
  113. gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
  114. /* Select one edge or both edges in BOTHEDGE */
  115. if (p->info.has_both_edge_trigger)
  116. gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
  117. /* Select "Interrupt Input Mode" in IOINTSEL */
  118. gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
  119. /* Write INTCLR in case of edge trigger */
  120. if (!level_trigger)
  121. gpio_rcar_write(p, INTCLR, BIT(hwirq));
  122. spin_unlock_irqrestore(&p->lock, flags);
  123. }
  124. static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
  125. {
  126. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  127. struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  128. unsigned int hwirq = irqd_to_hwirq(d);
  129. dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
  130. switch (type & IRQ_TYPE_SENSE_MASK) {
  131. case IRQ_TYPE_LEVEL_HIGH:
  132. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
  133. false);
  134. break;
  135. case IRQ_TYPE_LEVEL_LOW:
  136. gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
  137. false);
  138. break;
  139. case IRQ_TYPE_EDGE_RISING:
  140. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
  141. false);
  142. break;
  143. case IRQ_TYPE_EDGE_FALLING:
  144. gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
  145. false);
  146. break;
  147. case IRQ_TYPE_EDGE_BOTH:
  148. if (!p->info.has_both_edge_trigger)
  149. return -EINVAL;
  150. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
  151. true);
  152. break;
  153. default:
  154. return -EINVAL;
  155. }
  156. return 0;
  157. }
  158. static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
  159. {
  160. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  161. struct gpio_rcar_priv *p = gpiochip_get_data(gc);
  162. int error;
  163. if (p->irq_parent) {
  164. error = irq_set_irq_wake(p->irq_parent, on);
  165. if (error) {
  166. dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
  167. p->irq_parent);
  168. p->irq_parent = 0;
  169. }
  170. }
  171. if (on)
  172. atomic_inc(&p->wakeup_path);
  173. else
  174. atomic_dec(&p->wakeup_path);
  175. return 0;
  176. }
  177. static const struct irq_chip gpio_rcar_irq_chip = {
  178. .name = "gpio-rcar",
  179. .irq_mask = gpio_rcar_irq_disable,
  180. .irq_unmask = gpio_rcar_irq_enable,
  181. .irq_set_type = gpio_rcar_irq_set_type,
  182. .irq_set_wake = gpio_rcar_irq_set_wake,
  183. .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED |
  184. IRQCHIP_MASK_ON_SUSPEND,
  185. GPIOCHIP_IRQ_RESOURCE_HELPERS,
  186. };
  187. static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
  188. {
  189. struct gpio_rcar_priv *p = dev_id;
  190. u32 pending;
  191. unsigned int offset, irqs_handled = 0;
  192. while ((pending = gpio_rcar_read(p, INTDT) &
  193. gpio_rcar_read(p, INTMSK))) {
  194. offset = __ffs(pending);
  195. gpio_rcar_write(p, INTCLR, BIT(offset));
  196. generic_handle_domain_irq(p->gpio_chip.irq.domain,
  197. offset);
  198. irqs_handled++;
  199. }
  200. return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
  201. }
  202. static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
  203. unsigned int gpio,
  204. bool output)
  205. {
  206. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  207. unsigned long flags;
  208. /* follow steps in the GPIO documentation for
  209. * "Setting General Output Mode" and
  210. * "Setting General Input Mode"
  211. */
  212. spin_lock_irqsave(&p->lock, flags);
  213. /* Configure positive logic in POSNEG */
  214. gpio_rcar_modify_bit(p, POSNEG, gpio, false);
  215. /* Select "General Input/Output Mode" in IOINTSEL */
  216. gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
  217. /* Select Input Mode or Output Mode in INOUTSEL */
  218. gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
  219. /* Select General Output Register to output data in OUTDTSEL */
  220. if (p->info.has_outdtsel && output)
  221. gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
  222. spin_unlock_irqrestore(&p->lock, flags);
  223. }
  224. static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
  225. {
  226. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  227. int error;
  228. error = pm_runtime_get_sync(p->dev);
  229. if (error < 0) {
  230. pm_runtime_put(p->dev);
  231. return error;
  232. }
  233. error = pinctrl_gpio_request(chip->base + offset);
  234. if (error)
  235. pm_runtime_put(p->dev);
  236. return error;
  237. }
  238. static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
  239. {
  240. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  241. pinctrl_gpio_free(chip->base + offset);
  242. /*
  243. * Set the GPIO as an input to ensure that the next GPIO request won't
  244. * drive the GPIO pin as an output.
  245. */
  246. gpio_rcar_config_general_input_output_mode(chip, offset, false);
  247. pm_runtime_put(p->dev);
  248. }
  249. static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
  250. {
  251. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  252. if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
  253. return GPIO_LINE_DIRECTION_OUT;
  254. return GPIO_LINE_DIRECTION_IN;
  255. }
  256. static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
  257. {
  258. gpio_rcar_config_general_input_output_mode(chip, offset, false);
  259. return 0;
  260. }
  261. static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
  262. {
  263. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  264. u32 bit = BIT(offset);
  265. /*
  266. * Before R-Car Gen3, INDT does not show correct pin state when
  267. * configured as output, so use OUTDT in case of output pins
  268. */
  269. if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))
  270. return !!(gpio_rcar_read(p, OUTDT) & bit);
  271. else
  272. return !!(gpio_rcar_read(p, INDT) & bit);
  273. }
  274. static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
  275. unsigned long *bits)
  276. {
  277. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  278. u32 bankmask, outputs, m, val = 0;
  279. unsigned long flags;
  280. bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
  281. if (chip->valid_mask)
  282. bankmask &= chip->valid_mask[0];
  283. if (!bankmask)
  284. return 0;
  285. if (p->info.has_always_in) {
  286. bits[0] = gpio_rcar_read(p, INDT) & bankmask;
  287. return 0;
  288. }
  289. spin_lock_irqsave(&p->lock, flags);
  290. outputs = gpio_rcar_read(p, INOUTSEL);
  291. m = outputs & bankmask;
  292. if (m)
  293. val |= gpio_rcar_read(p, OUTDT) & m;
  294. m = ~outputs & bankmask;
  295. if (m)
  296. val |= gpio_rcar_read(p, INDT) & m;
  297. spin_unlock_irqrestore(&p->lock, flags);
  298. bits[0] = val;
  299. return 0;
  300. }
  301. static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
  302. {
  303. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  304. unsigned long flags;
  305. spin_lock_irqsave(&p->lock, flags);
  306. gpio_rcar_modify_bit(p, OUTDT, offset, value);
  307. spin_unlock_irqrestore(&p->lock, flags);
  308. }
  309. static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
  310. unsigned long *bits)
  311. {
  312. struct gpio_rcar_priv *p = gpiochip_get_data(chip);
  313. unsigned long flags;
  314. u32 val, bankmask;
  315. bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
  316. if (chip->valid_mask)
  317. bankmask &= chip->valid_mask[0];
  318. if (!bankmask)
  319. return;
  320. spin_lock_irqsave(&p->lock, flags);
  321. val = gpio_rcar_read(p, OUTDT);
  322. val &= ~bankmask;
  323. val |= (bankmask & bits[0]);
  324. gpio_rcar_write(p, OUTDT, val);
  325. spin_unlock_irqrestore(&p->lock, flags);
  326. }
  327. static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
  328. int value)
  329. {
  330. /* write GPIO value to output before selecting output mode of pin */
  331. gpio_rcar_set(chip, offset, value);
  332. gpio_rcar_config_general_input_output_mode(chip, offset, true);
  333. return 0;
  334. }
  335. static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
  336. .has_outdtsel = false,
  337. .has_both_edge_trigger = false,
  338. .has_always_in = false,
  339. .has_inen = false,
  340. };
  341. static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
  342. .has_outdtsel = true,
  343. .has_both_edge_trigger = true,
  344. .has_always_in = false,
  345. .has_inen = false,
  346. };
  347. static const struct gpio_rcar_info gpio_rcar_info_gen3 = {
  348. .has_outdtsel = true,
  349. .has_both_edge_trigger = true,
  350. .has_always_in = true,
  351. .has_inen = false,
  352. };
  353. static const struct gpio_rcar_info gpio_rcar_info_gen4 = {
  354. .has_outdtsel = true,
  355. .has_both_edge_trigger = true,
  356. .has_always_in = true,
  357. .has_inen = true,
  358. };
  359. static const struct of_device_id gpio_rcar_of_table[] = {
  360. {
  361. .compatible = "renesas,gpio-r8a779a0",
  362. .data = &gpio_rcar_info_gen4,
  363. }, {
  364. .compatible = "renesas,rcar-gen1-gpio",
  365. .data = &gpio_rcar_info_gen1,
  366. }, {
  367. .compatible = "renesas,rcar-gen2-gpio",
  368. .data = &gpio_rcar_info_gen2,
  369. }, {
  370. .compatible = "renesas,rcar-gen3-gpio",
  371. .data = &gpio_rcar_info_gen3,
  372. }, {
  373. .compatible = "renesas,rcar-gen4-gpio",
  374. .data = &gpio_rcar_info_gen4,
  375. }, {
  376. .compatible = "renesas,gpio-rcar",
  377. .data = &gpio_rcar_info_gen1,
  378. }, {
  379. /* Terminator */
  380. },
  381. };
  382. MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
  383. static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
  384. {
  385. struct device_node *np = p->dev->of_node;
  386. const struct gpio_rcar_info *info;
  387. struct of_phandle_args args;
  388. int ret;
  389. info = of_device_get_match_data(p->dev);
  390. p->info = *info;
  391. ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
  392. *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
  393. if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
  394. dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
  395. *npins, RCAR_MAX_GPIO_PER_BANK);
  396. *npins = RCAR_MAX_GPIO_PER_BANK;
  397. }
  398. return 0;
  399. }
  400. static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)
  401. {
  402. u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);
  403. /* Select "Input Enable" in INEN */
  404. if (p->gpio_chip.valid_mask)
  405. mask &= p->gpio_chip.valid_mask[0];
  406. if (mask)
  407. gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);
  408. }
  409. static int gpio_rcar_probe(struct platform_device *pdev)
  410. {
  411. struct gpio_rcar_priv *p;
  412. struct gpio_chip *gpio_chip;
  413. struct gpio_irq_chip *girq;
  414. struct device *dev = &pdev->dev;
  415. const char *name = dev_name(dev);
  416. unsigned int npins;
  417. int ret;
  418. p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
  419. if (!p)
  420. return -ENOMEM;
  421. p->dev = dev;
  422. spin_lock_init(&p->lock);
  423. /* Get device configuration from DT node */
  424. ret = gpio_rcar_parse_dt(p, &npins);
  425. if (ret < 0)
  426. return ret;
  427. platform_set_drvdata(pdev, p);
  428. pm_runtime_enable(dev);
  429. ret = platform_get_irq(pdev, 0);
  430. if (ret < 0)
  431. goto err0;
  432. p->irq_parent = ret;
  433. p->base = devm_platform_ioremap_resource(pdev, 0);
  434. if (IS_ERR(p->base)) {
  435. ret = PTR_ERR(p->base);
  436. goto err0;
  437. }
  438. gpio_chip = &p->gpio_chip;
  439. gpio_chip->request = gpio_rcar_request;
  440. gpio_chip->free = gpio_rcar_free;
  441. gpio_chip->get_direction = gpio_rcar_get_direction;
  442. gpio_chip->direction_input = gpio_rcar_direction_input;
  443. gpio_chip->get = gpio_rcar_get;
  444. gpio_chip->get_multiple = gpio_rcar_get_multiple;
  445. gpio_chip->direction_output = gpio_rcar_direction_output;
  446. gpio_chip->set = gpio_rcar_set;
  447. gpio_chip->set_multiple = gpio_rcar_set_multiple;
  448. gpio_chip->label = name;
  449. gpio_chip->parent = dev;
  450. gpio_chip->owner = THIS_MODULE;
  451. gpio_chip->base = -1;
  452. gpio_chip->ngpio = npins;
  453. girq = &gpio_chip->irq;
  454. gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip);
  455. /* This will let us handle the parent IRQ in the driver */
  456. girq->parent_handler = NULL;
  457. girq->num_parents = 0;
  458. girq->parents = NULL;
  459. girq->default_type = IRQ_TYPE_NONE;
  460. girq->handler = handle_level_irq;
  461. ret = gpiochip_add_data(gpio_chip, p);
  462. if (ret) {
  463. dev_err(dev, "failed to add GPIO controller\n");
  464. goto err0;
  465. }
  466. irq_domain_set_pm_device(gpio_chip->irq.domain, dev);
  467. ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,
  468. IRQF_SHARED, name, p);
  469. if (ret) {
  470. dev_err(dev, "failed to request IRQ\n");
  471. goto err1;
  472. }
  473. if (p->info.has_inen) {
  474. pm_runtime_get_sync(dev);
  475. gpio_rcar_enable_inputs(p);
  476. pm_runtime_put(dev);
  477. }
  478. dev_info(dev, "driving %d GPIOs\n", npins);
  479. return 0;
  480. err1:
  481. gpiochip_remove(gpio_chip);
  482. err0:
  483. pm_runtime_disable(dev);
  484. return ret;
  485. }
  486. static int gpio_rcar_remove(struct platform_device *pdev)
  487. {
  488. struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
  489. gpiochip_remove(&p->gpio_chip);
  490. pm_runtime_disable(&pdev->dev);
  491. return 0;
  492. }
  493. #ifdef CONFIG_PM_SLEEP
  494. static int gpio_rcar_suspend(struct device *dev)
  495. {
  496. struct gpio_rcar_priv *p = dev_get_drvdata(dev);
  497. p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
  498. p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
  499. p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
  500. p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
  501. p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
  502. p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
  503. if (p->info.has_both_edge_trigger)
  504. p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
  505. if (atomic_read(&p->wakeup_path))
  506. device_set_wakeup_path(dev);
  507. return 0;
  508. }
  509. static int gpio_rcar_resume(struct device *dev)
  510. {
  511. struct gpio_rcar_priv *p = dev_get_drvdata(dev);
  512. unsigned int offset;
  513. u32 mask;
  514. for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
  515. if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
  516. continue;
  517. mask = BIT(offset);
  518. /* I/O pin */
  519. if (!(p->bank_info.iointsel & mask)) {
  520. if (p->bank_info.inoutsel & mask)
  521. gpio_rcar_direction_output(
  522. &p->gpio_chip, offset,
  523. !!(p->bank_info.outdt & mask));
  524. else
  525. gpio_rcar_direction_input(&p->gpio_chip,
  526. offset);
  527. } else {
  528. /* Interrupt pin */
  529. gpio_rcar_config_interrupt_input_mode(
  530. p,
  531. offset,
  532. !(p->bank_info.posneg & mask),
  533. !(p->bank_info.edglevel & mask),
  534. !!(p->bank_info.bothedge & mask));
  535. if (p->bank_info.intmsk & mask)
  536. gpio_rcar_write(p, MSKCLR, mask);
  537. }
  538. }
  539. if (p->info.has_inen)
  540. gpio_rcar_enable_inputs(p);
  541. return 0;
  542. }
  543. #endif /* CONFIG_PM_SLEEP*/
  544. static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
  545. static struct platform_driver gpio_rcar_device_driver = {
  546. .probe = gpio_rcar_probe,
  547. .remove = gpio_rcar_remove,
  548. .driver = {
  549. .name = "gpio_rcar",
  550. .pm = &gpio_rcar_pm_ops,
  551. .of_match_table = of_match_ptr(gpio_rcar_of_table),
  552. }
  553. };
  554. module_platform_driver(gpio_rcar_device_driver);
  555. MODULE_AUTHOR("Magnus Damm");
  556. MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
  557. MODULE_LICENSE("GPL v2");