gpio-mt7621.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2009-2011 Gabor Juhos <[email protected]>
  4. * Copyright (C) 2013 John Crispin <[email protected]>
  5. */
  6. #include <linux/err.h>
  7. #include <linux/gpio/driver.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/spinlock.h>
  13. #define MTK_BANK_CNT 3
  14. #define MTK_BANK_WIDTH 32
  15. #define GPIO_BANK_STRIDE 0x04
  16. #define GPIO_REG_CTRL 0x00
  17. #define GPIO_REG_POL 0x10
  18. #define GPIO_REG_DATA 0x20
  19. #define GPIO_REG_DSET 0x30
  20. #define GPIO_REG_DCLR 0x40
  21. #define GPIO_REG_REDGE 0x50
  22. #define GPIO_REG_FEDGE 0x60
  23. #define GPIO_REG_HLVL 0x70
  24. #define GPIO_REG_LLVL 0x80
  25. #define GPIO_REG_STAT 0x90
  26. #define GPIO_REG_EDGE 0xA0
  27. struct mtk_gc {
  28. struct irq_chip irq_chip;
  29. struct gpio_chip chip;
  30. spinlock_t lock;
  31. int bank;
  32. u32 rising;
  33. u32 falling;
  34. u32 hlevel;
  35. u32 llevel;
  36. };
  37. /**
  38. * struct mtk - state container for
  39. * data of the platform driver. It is 3
  40. * separate gpio-chip each one with its
  41. * own irq_chip.
  42. * @dev: device instance
  43. * @base: memory base address
  44. * @gpio_irq: irq number from the device tree
  45. * @gc_map: array of the gpio chips
  46. */
  47. struct mtk {
  48. struct device *dev;
  49. void __iomem *base;
  50. int gpio_irq;
  51. struct mtk_gc gc_map[MTK_BANK_CNT];
  52. };
  53. static inline struct mtk_gc *
  54. to_mediatek_gpio(struct gpio_chip *chip)
  55. {
  56. return container_of(chip, struct mtk_gc, chip);
  57. }
  58. static inline void
  59. mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
  60. {
  61. struct gpio_chip *gc = &rg->chip;
  62. struct mtk *mtk = gpiochip_get_data(gc);
  63. offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
  64. gc->write_reg(mtk->base + offset, val);
  65. }
  66. static inline u32
  67. mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
  68. {
  69. struct gpio_chip *gc = &rg->chip;
  70. struct mtk *mtk = gpiochip_get_data(gc);
  71. offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
  72. return gc->read_reg(mtk->base + offset);
  73. }
  74. static irqreturn_t
  75. mediatek_gpio_irq_handler(int irq, void *data)
  76. {
  77. struct gpio_chip *gc = data;
  78. struct mtk_gc *rg = to_mediatek_gpio(gc);
  79. irqreturn_t ret = IRQ_NONE;
  80. unsigned long pending;
  81. int bit;
  82. pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
  83. for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
  84. generic_handle_domain_irq(gc->irq.domain, bit);
  85. mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
  86. ret |= IRQ_HANDLED;
  87. }
  88. return ret;
  89. }
  90. static void
  91. mediatek_gpio_irq_unmask(struct irq_data *d)
  92. {
  93. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  94. struct mtk_gc *rg = to_mediatek_gpio(gc);
  95. int pin = d->hwirq;
  96. unsigned long flags;
  97. u32 rise, fall, high, low;
  98. gpiochip_enable_irq(gc, d->hwirq);
  99. spin_lock_irqsave(&rg->lock, flags);
  100. rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
  101. fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
  102. high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
  103. low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
  104. mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
  105. mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
  106. mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
  107. mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
  108. spin_unlock_irqrestore(&rg->lock, flags);
  109. }
  110. static void
  111. mediatek_gpio_irq_mask(struct irq_data *d)
  112. {
  113. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  114. struct mtk_gc *rg = to_mediatek_gpio(gc);
  115. int pin = d->hwirq;
  116. unsigned long flags;
  117. u32 rise, fall, high, low;
  118. spin_lock_irqsave(&rg->lock, flags);
  119. rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
  120. fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
  121. high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
  122. low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
  123. mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
  124. mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
  125. mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
  126. mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
  127. spin_unlock_irqrestore(&rg->lock, flags);
  128. gpiochip_disable_irq(gc, d->hwirq);
  129. }
  130. static int
  131. mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
  132. {
  133. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  134. struct mtk_gc *rg = to_mediatek_gpio(gc);
  135. int pin = d->hwirq;
  136. u32 mask = BIT(pin);
  137. if (type == IRQ_TYPE_PROBE) {
  138. if ((rg->rising | rg->falling |
  139. rg->hlevel | rg->llevel) & mask)
  140. return 0;
  141. type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  142. }
  143. rg->rising &= ~mask;
  144. rg->falling &= ~mask;
  145. rg->hlevel &= ~mask;
  146. rg->llevel &= ~mask;
  147. switch (type & IRQ_TYPE_SENSE_MASK) {
  148. case IRQ_TYPE_EDGE_BOTH:
  149. rg->rising |= mask;
  150. rg->falling |= mask;
  151. break;
  152. case IRQ_TYPE_EDGE_RISING:
  153. rg->rising |= mask;
  154. break;
  155. case IRQ_TYPE_EDGE_FALLING:
  156. rg->falling |= mask;
  157. break;
  158. case IRQ_TYPE_LEVEL_HIGH:
  159. rg->hlevel |= mask;
  160. break;
  161. case IRQ_TYPE_LEVEL_LOW:
  162. rg->llevel |= mask;
  163. break;
  164. }
  165. return 0;
  166. }
  167. static int
  168. mediatek_gpio_xlate(struct gpio_chip *chip,
  169. const struct of_phandle_args *spec, u32 *flags)
  170. {
  171. int gpio = spec->args[0];
  172. struct mtk_gc *rg = to_mediatek_gpio(chip);
  173. if (rg->bank != gpio / MTK_BANK_WIDTH)
  174. return -EINVAL;
  175. if (flags)
  176. *flags = spec->args[1];
  177. return gpio % MTK_BANK_WIDTH;
  178. }
  179. static const struct irq_chip mt7621_irq_chip = {
  180. .name = "mt7621-gpio",
  181. .irq_mask_ack = mediatek_gpio_irq_mask,
  182. .irq_mask = mediatek_gpio_irq_mask,
  183. .irq_unmask = mediatek_gpio_irq_unmask,
  184. .irq_set_type = mediatek_gpio_irq_type,
  185. .flags = IRQCHIP_IMMUTABLE,
  186. GPIOCHIP_IRQ_RESOURCE_HELPERS,
  187. };
  188. static int
  189. mediatek_gpio_bank_probe(struct device *dev, int bank)
  190. {
  191. struct mtk *mtk = dev_get_drvdata(dev);
  192. struct mtk_gc *rg;
  193. void __iomem *dat, *set, *ctrl, *diro;
  194. int ret;
  195. rg = &mtk->gc_map[bank];
  196. memset(rg, 0, sizeof(*rg));
  197. spin_lock_init(&rg->lock);
  198. rg->bank = bank;
  199. dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
  200. set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
  201. ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
  202. diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
  203. ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
  204. BGPIOF_NO_SET_ON_INPUT);
  205. if (ret) {
  206. dev_err(dev, "bgpio_init() failed\n");
  207. return ret;
  208. }
  209. rg->chip.of_gpio_n_cells = 2;
  210. rg->chip.of_xlate = mediatek_gpio_xlate;
  211. rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
  212. dev_name(dev), bank);
  213. if (!rg->chip.label)
  214. return -ENOMEM;
  215. rg->chip.offset = bank * MTK_BANK_WIDTH;
  216. if (mtk->gpio_irq) {
  217. struct gpio_irq_chip *girq;
  218. /*
  219. * Directly request the irq here instead of passing
  220. * a flow-handler because the irq is shared.
  221. */
  222. ret = devm_request_irq(dev, mtk->gpio_irq,
  223. mediatek_gpio_irq_handler, IRQF_SHARED,
  224. rg->chip.label, &rg->chip);
  225. if (ret) {
  226. dev_err(dev, "Error requesting IRQ %d: %d\n",
  227. mtk->gpio_irq, ret);
  228. return ret;
  229. }
  230. girq = &rg->chip.irq;
  231. gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
  232. /* This will let us handle the parent IRQ in the driver */
  233. girq->parent_handler = NULL;
  234. girq->num_parents = 0;
  235. girq->parents = NULL;
  236. girq->default_type = IRQ_TYPE_NONE;
  237. girq->handler = handle_simple_irq;
  238. }
  239. ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
  240. if (ret < 0) {
  241. dev_err(dev, "Could not register gpio %d, ret=%d\n",
  242. rg->chip.ngpio, ret);
  243. return ret;
  244. }
  245. /* set polarity to low for all gpios */
  246. mtk_gpio_w32(rg, GPIO_REG_POL, 0);
  247. dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
  248. return 0;
  249. }
  250. static int
  251. mediatek_gpio_probe(struct platform_device *pdev)
  252. {
  253. struct device *dev = &pdev->dev;
  254. struct mtk *mtk;
  255. int i;
  256. int ret;
  257. mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
  258. if (!mtk)
  259. return -ENOMEM;
  260. mtk->base = devm_platform_ioremap_resource(pdev, 0);
  261. if (IS_ERR(mtk->base))
  262. return PTR_ERR(mtk->base);
  263. mtk->gpio_irq = platform_get_irq(pdev, 0);
  264. if (mtk->gpio_irq < 0)
  265. return mtk->gpio_irq;
  266. mtk->dev = dev;
  267. platform_set_drvdata(pdev, mtk);
  268. for (i = 0; i < MTK_BANK_CNT; i++) {
  269. ret = mediatek_gpio_bank_probe(dev, i);
  270. if (ret)
  271. return ret;
  272. }
  273. return 0;
  274. }
  275. static const struct of_device_id mediatek_gpio_match[] = {
  276. { .compatible = "mediatek,mt7621-gpio" },
  277. {},
  278. };
  279. MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
  280. static struct platform_driver mediatek_gpio_driver = {
  281. .probe = mediatek_gpio_probe,
  282. .driver = {
  283. .name = "mt7621_gpio",
  284. .of_match_table = mediatek_gpio_match,
  285. },
  286. };
  287. builtin_platform_driver(mediatek_gpio_driver);