skx_common.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
  4. * Originally split out from the skx_edac driver.
  5. *
  6. * Copyright (c) 2018, Intel Corporation.
  7. */
  8. #ifndef _SKX_COMM_EDAC_H
  9. #define _SKX_COMM_EDAC_H
  10. #include <linux/bits.h>
  11. #include <asm/mce.h>
  12. #define MSG_SIZE 1024
  13. /*
  14. * Debug macros
  15. */
  16. #define skx_printk(level, fmt, arg...) \
  17. edac_printk(level, "skx", fmt, ##arg)
  18. #define skx_mc_printk(mci, level, fmt, arg...) \
  19. edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
  20. /*
  21. * Get a bit field at register value <v>, from bit <lo> to bit <hi>
  22. */
  23. #define GET_BITFIELD(v, lo, hi) \
  24. (((v) & GENMASK_ULL((hi), (lo))) >> (lo))
  25. #define SKX_NUM_IMC 2 /* Memory controllers per socket */
  26. #define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
  27. #define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
  28. #define I10NM_NUM_DDR_IMC 4
  29. #define I10NM_NUM_DDR_CHANNELS 2
  30. #define I10NM_NUM_DDR_DIMMS 2
  31. #define I10NM_NUM_HBM_IMC 16
  32. #define I10NM_NUM_HBM_CHANNELS 2
  33. #define I10NM_NUM_HBM_DIMMS 1
  34. #define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
  35. #define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
  36. #define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
  37. #define MAX(a, b) ((a) > (b) ? (a) : (b))
  38. #define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
  39. #define NUM_CHANNELS MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
  40. #define NUM_DIMMS MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)
  41. #define IS_DIMM_PRESENT(r) GET_BITFIELD(r, 15, 15)
  42. #define IS_NVDIMM_PRESENT(r, i) GET_BITFIELD(r, i, i)
  43. #define MCI_MISC_ECC_MODE(m) (((m) >> 59) & 15)
  44. #define MCI_MISC_ECC_DDRT 8 /* read from DDRT */
  45. /*
  46. * Each cpu socket contains some pci devices that provide global
  47. * information, and also some that are local to each of the two
  48. * memory controllers on the die.
  49. */
  50. struct skx_dev {
  51. struct list_head list;
  52. u8 bus[4];
  53. int seg;
  54. struct pci_dev *sad_all;
  55. struct pci_dev *util_all;
  56. struct pci_dev *uracu; /* for i10nm CPU */
  57. struct pci_dev *pcu_cr3; /* for HBM memory detection */
  58. u32 mcroute;
  59. struct skx_imc {
  60. struct mem_ctl_info *mci;
  61. struct pci_dev *mdev; /* for i10nm CPU */
  62. void __iomem *mbase; /* for i10nm CPU */
  63. int chan_mmio_sz; /* for i10nm CPU */
  64. int num_channels; /* channels per memory controller */
  65. int num_dimms; /* dimms per channel */
  66. bool hbm_mc;
  67. u8 mc; /* system wide mc# */
  68. u8 lmc; /* socket relative mc# */
  69. u8 src_id, node_id;
  70. struct skx_channel {
  71. struct pci_dev *cdev;
  72. struct pci_dev *edev;
  73. u32 retry_rd_err_log_s;
  74. u32 retry_rd_err_log_d;
  75. u32 retry_rd_err_log_d2;
  76. struct skx_dimm {
  77. u8 close_pg;
  78. u8 bank_xor_enable;
  79. u8 fine_grain_bank;
  80. u8 rowbits;
  81. u8 colbits;
  82. } dimms[NUM_DIMMS];
  83. } chan[NUM_CHANNELS];
  84. } imc[NUM_IMC];
  85. };
  86. struct skx_pvt {
  87. struct skx_imc *imc;
  88. };
  89. enum type {
  90. SKX,
  91. I10NM,
  92. SPR
  93. };
  94. enum {
  95. INDEX_SOCKET,
  96. INDEX_MEMCTRL,
  97. INDEX_CHANNEL,
  98. INDEX_DIMM,
  99. INDEX_CS,
  100. INDEX_NM_FIRST,
  101. INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
  102. INDEX_NM_CHANNEL,
  103. INDEX_NM_DIMM,
  104. INDEX_NM_CS,
  105. INDEX_MAX
  106. };
  107. #define BIT_NM_MEMCTRL BIT_ULL(INDEX_NM_MEMCTRL)
  108. #define BIT_NM_CHANNEL BIT_ULL(INDEX_NM_CHANNEL)
  109. #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
  110. #define BIT_NM_CS BIT_ULL(INDEX_NM_CS)
  111. struct decoded_addr {
  112. struct mce *mce;
  113. struct skx_dev *dev;
  114. u64 addr;
  115. int socket;
  116. int imc;
  117. int channel;
  118. u64 chan_addr;
  119. int sktways;
  120. int chanways;
  121. int dimm;
  122. int cs;
  123. int rank;
  124. int channel_rank;
  125. u64 rank_address;
  126. int row;
  127. int column;
  128. int bank_address;
  129. int bank_group;
  130. bool decoded_by_adxl;
  131. };
  132. struct res_config {
  133. enum type type;
  134. /* Configuration agent device ID */
  135. unsigned int decs_did;
  136. /* Default bus number configuration register offset */
  137. int busno_cfg_offset;
  138. /* Per DDR channel memory-mapped I/O size */
  139. int ddr_chan_mmio_sz;
  140. /* Per HBM channel memory-mapped I/O size */
  141. int hbm_chan_mmio_sz;
  142. bool support_ddr5;
  143. /* SAD device number and function number */
  144. unsigned int sad_all_devfn;
  145. int sad_all_offset;
  146. /* Offsets of retry_rd_err_log registers */
  147. u32 *offsets_scrub;
  148. u32 *offsets_scrub_hbm0;
  149. u32 *offsets_scrub_hbm1;
  150. u32 *offsets_demand;
  151. u32 *offsets_demand2;
  152. u32 *offsets_demand_hbm0;
  153. u32 *offsets_demand_hbm1;
  154. };
  155. typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
  156. struct res_config *cfg);
  157. typedef bool (*skx_decode_f)(struct decoded_addr *res);
  158. typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);
  159. int __init skx_adxl_get(void);
  160. void __exit skx_adxl_put(void);
  161. void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
  162. void skx_set_mem_cfg(bool mem_cfg_2lm);
  163. int skx_get_src_id(struct skx_dev *d, int off, u8 *id);
  164. int skx_get_node_id(struct skx_dev *d, u8 *id);
  165. int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);
  166. int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);
  167. int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
  168. struct skx_imc *imc, int chan, int dimmno,
  169. struct res_config *cfg);
  170. int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
  171. int chan, int dimmno, const char *mod_str);
  172. int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
  173. const char *ctl_name, const char *mod_str,
  174. get_dimm_config_f get_dimm_config,
  175. struct res_config *cfg);
  176. int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
  177. void *data);
  178. void skx_remove(void);
  179. #endif /* _SKX_COMM_EDAC_H */