skx_base.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * EDAC driver for Intel(R) Xeon(R) Skylake processors
  4. * Copyright (c) 2016, Intel Corporation.
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/processor.h>
  8. #include <asm/cpu_device_id.h>
  9. #include <asm/intel-family.h>
  10. #include <asm/mce.h>
  11. #include "edac_module.h"
  12. #include "skx_common.h"
  13. #define EDAC_MOD_STR "skx_edac"
  14. /*
  15. * Debug macros
  16. */
  17. #define skx_printk(level, fmt, arg...) \
  18. edac_printk(level, "skx", fmt, ##arg)
  19. #define skx_mc_printk(mci, level, fmt, arg...) \
  20. edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
  21. static struct list_head *skx_edac_list;
  22. static u64 skx_tolm, skx_tohm;
  23. static int skx_num_sockets;
  24. static unsigned int nvdimm_count;
  25. #define MASK26 0x3FFFFFF /* Mask for 2^26 */
  26. #define MASK29 0x1FFFFFFF /* Mask for 2^29 */
  27. static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
  28. {
  29. struct skx_dev *d;
  30. list_for_each_entry(d, skx_edac_list, list) {
  31. if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
  32. return d;
  33. }
  34. return NULL;
  35. }
  36. enum munittype {
  37. CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD,
  38. ERRCHAN0, ERRCHAN1, ERRCHAN2,
  39. };
  40. struct munit {
  41. u16 did;
  42. u16 devfn[SKX_NUM_IMC];
  43. u8 busidx;
  44. u8 per_socket;
  45. enum munittype mtype;
  46. };
  47. /*
  48. * List of PCI device ids that we need together with some device
  49. * number and function numbers to tell which memory controller the
  50. * device belongs to.
  51. */
  52. static const struct munit skx_all_munits[] = {
  53. { 0x2054, { }, 1, 1, SAD_ALL },
  54. { 0x2055, { }, 1, 1, UTIL_ALL },
  55. { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
  56. { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
  57. { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
  58. { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 },
  59. { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 },
  60. { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 },
  61. { 0x208e, { }, 1, 0, SAD },
  62. { }
  63. };
  64. static int get_all_munits(const struct munit *m)
  65. {
  66. struct pci_dev *pdev, *prev;
  67. struct skx_dev *d;
  68. u32 reg;
  69. int i = 0, ndev = 0;
  70. prev = NULL;
  71. for (;;) {
  72. pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
  73. if (!pdev)
  74. break;
  75. ndev++;
  76. if (m->per_socket == SKX_NUM_IMC) {
  77. for (i = 0; i < SKX_NUM_IMC; i++)
  78. if (m->devfn[i] == pdev->devfn)
  79. break;
  80. if (i == SKX_NUM_IMC)
  81. goto fail;
  82. }
  83. d = get_skx_dev(pdev->bus, m->busidx);
  84. if (!d)
  85. goto fail;
  86. /* Be sure that the device is enabled */
  87. if (unlikely(pci_enable_device(pdev) < 0)) {
  88. skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n",
  89. PCI_VENDOR_ID_INTEL, m->did);
  90. goto fail;
  91. }
  92. switch (m->mtype) {
  93. case CHAN0:
  94. case CHAN1:
  95. case CHAN2:
  96. pci_dev_get(pdev);
  97. d->imc[i].chan[m->mtype].cdev = pdev;
  98. break;
  99. case ERRCHAN0:
  100. case ERRCHAN1:
  101. case ERRCHAN2:
  102. pci_dev_get(pdev);
  103. d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev;
  104. break;
  105. case SAD_ALL:
  106. pci_dev_get(pdev);
  107. d->sad_all = pdev;
  108. break;
  109. case UTIL_ALL:
  110. pci_dev_get(pdev);
  111. d->util_all = pdev;
  112. break;
  113. case SAD:
  114. /*
  115. * one of these devices per core, including cores
  116. * that don't exist on this SKU. Ignore any that
  117. * read a route table of zero, make sure all the
  118. * non-zero values match.
  119. */
  120. pci_read_config_dword(pdev, 0xB4, &reg);
  121. if (reg != 0) {
  122. if (d->mcroute == 0) {
  123. d->mcroute = reg;
  124. } else if (d->mcroute != reg) {
  125. skx_printk(KERN_ERR, "mcroute mismatch\n");
  126. goto fail;
  127. }
  128. }
  129. ndev--;
  130. break;
  131. }
  132. prev = pdev;
  133. }
  134. return ndev;
  135. fail:
  136. pci_dev_put(pdev);
  137. return -ENODEV;
  138. }
  139. static struct res_config skx_cfg = {
  140. .type = SKX,
  141. .decs_did = 0x2016,
  142. .busno_cfg_offset = 0xcc,
  143. };
  144. static const struct x86_cpu_id skx_cpuids[] = {
  145. X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cfg),
  146. { }
  147. };
  148. MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
  149. static bool skx_check_ecc(u32 mcmtr)
  150. {
  151. return !!GET_BITFIELD(mcmtr, 2, 2);
  152. }
  153. static int skx_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg)
  154. {
  155. struct skx_pvt *pvt = mci->pvt_info;
  156. u32 mtr, mcmtr, amap, mcddrtcfg;
  157. struct skx_imc *imc = pvt->imc;
  158. struct dimm_info *dimm;
  159. int i, j;
  160. int ndimms;
  161. /* Only the mcmtr on the first channel is effective */
  162. pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr);
  163. for (i = 0; i < SKX_NUM_CHANNELS; i++) {
  164. ndimms = 0;
  165. pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
  166. pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg);
  167. for (j = 0; j < SKX_NUM_DIMMS; j++) {
  168. dimm = edac_get_dimm(mci, i, j, 0);
  169. pci_read_config_dword(imc->chan[i].cdev,
  170. 0x80 + 4 * j, &mtr);
  171. if (IS_DIMM_PRESENT(mtr)) {
  172. ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg);
  173. } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) {
  174. ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
  175. EDAC_MOD_STR);
  176. nvdimm_count++;
  177. }
  178. }
  179. if (ndimms && !skx_check_ecc(mcmtr)) {
  180. skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
  181. return -ENODEV;
  182. }
  183. }
  184. return 0;
  185. }
  186. #define SKX_MAX_SAD 24
  187. #define SKX_GET_SAD(d, i, reg) \
  188. pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg))
  189. #define SKX_GET_ILV(d, i, reg) \
  190. pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg))
  191. #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31)
  192. #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27)
  193. #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
  194. #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
  195. #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4)
  196. #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
  197. #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
  198. #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
  199. #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
  200. static void skx_show_retry_rd_err_log(struct decoded_addr *res,
  201. char *msg, int len,
  202. bool scrub_err)
  203. {
  204. u32 log0, log1, log2, log3, log4;
  205. u32 corr0, corr1, corr2, corr3;
  206. struct pci_dev *edev;
  207. int n;
  208. edev = res->dev->imc[res->imc].chan[res->channel].edev;
  209. pci_read_config_dword(edev, 0x154, &log0);
  210. pci_read_config_dword(edev, 0x148, &log1);
  211. pci_read_config_dword(edev, 0x150, &log2);
  212. pci_read_config_dword(edev, 0x15c, &log3);
  213. pci_read_config_dword(edev, 0x114, &log4);
  214. n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]",
  215. log0, log1, log2, log3, log4);
  216. pci_read_config_dword(edev, 0x104, &corr0);
  217. pci_read_config_dword(edev, 0x108, &corr1);
  218. pci_read_config_dword(edev, 0x10c, &corr2);
  219. pci_read_config_dword(edev, 0x110, &corr3);
  220. if (len - n > 0)
  221. snprintf(msg + n, len - n,
  222. " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
  223. corr0 & 0xffff, corr0 >> 16,
  224. corr1 & 0xffff, corr1 >> 16,
  225. corr2 & 0xffff, corr2 >> 16,
  226. corr3 & 0xffff, corr3 >> 16);
  227. }
  228. static bool skx_sad_decode(struct decoded_addr *res)
  229. {
  230. struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list);
  231. u64 addr = res->addr;
  232. int i, idx, tgt, lchan, shift;
  233. u32 sad, ilv;
  234. u64 limit, prev_limit;
  235. int remote = 0;
  236. /* Simple sanity check for I/O space or out of range */
  237. if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
  238. edac_dbg(0, "Address 0x%llx out of range\n", addr);
  239. return false;
  240. }
  241. restart:
  242. prev_limit = 0;
  243. for (i = 0; i < SKX_MAX_SAD; i++) {
  244. SKX_GET_SAD(d, i, sad);
  245. limit = SKX_SAD_LIMIT(sad);
  246. if (SKX_SAD_ENABLE(sad)) {
  247. if (addr >= prev_limit && addr <= limit)
  248. goto sad_found;
  249. }
  250. prev_limit = limit + 1;
  251. }
  252. edac_dbg(0, "No SAD entry for 0x%llx\n", addr);
  253. return false;
  254. sad_found:
  255. SKX_GET_ILV(d, i, ilv);
  256. switch (SKX_SAD_INTERLEAVE(sad)) {
  257. case 0:
  258. idx = GET_BITFIELD(addr, 6, 8);
  259. break;
  260. case 1:
  261. idx = GET_BITFIELD(addr, 8, 10);
  262. break;
  263. case 2:
  264. idx = GET_BITFIELD(addr, 12, 14);
  265. break;
  266. case 3:
  267. idx = GET_BITFIELD(addr, 30, 32);
  268. break;
  269. }
  270. tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
  271. /* If point to another node, find it and start over */
  272. if (SKX_ILV_REMOTE(tgt)) {
  273. if (remote) {
  274. edac_dbg(0, "Double remote!\n");
  275. return false;
  276. }
  277. remote = 1;
  278. list_for_each_entry(d, skx_edac_list, list) {
  279. if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
  280. goto restart;
  281. }
  282. edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
  283. return false;
  284. }
  285. if (SKX_SAD_MOD3(sad) == 0) {
  286. lchan = SKX_ILV_TARGET(tgt);
  287. } else {
  288. switch (SKX_SAD_MOD3MODE(sad)) {
  289. case 0:
  290. shift = 6;
  291. break;
  292. case 1:
  293. shift = 8;
  294. break;
  295. case 2:
  296. shift = 12;
  297. break;
  298. default:
  299. edac_dbg(0, "illegal mod3mode\n");
  300. return false;
  301. }
  302. switch (SKX_SAD_MOD3ASMOD2(sad)) {
  303. case 0:
  304. lchan = (addr >> shift) % 3;
  305. break;
  306. case 1:
  307. lchan = (addr >> shift) % 2;
  308. break;
  309. case 2:
  310. lchan = (addr >> shift) % 2;
  311. lchan = (lchan << 1) | !lchan;
  312. break;
  313. case 3:
  314. lchan = ((addr >> shift) % 2) << 1;
  315. break;
  316. }
  317. lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
  318. }
  319. res->dev = d;
  320. res->socket = d->imc[0].src_id;
  321. res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
  322. res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
  323. edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n",
  324. res->addr, res->socket, res->imc, res->channel);
  325. return true;
  326. }
  327. #define SKX_MAX_TAD 8
  328. #define SKX_GET_TADBASE(d, mc, i, reg) \
  329. pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg))
  330. #define SKX_GET_TADWAYNESS(d, mc, i, reg) \
  331. pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg))
  332. #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \
  333. pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg))
  334. #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26)
  335. #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
  336. #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
  337. #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
  338. #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26)
  339. #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11))
  340. #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1)
  341. /* which bit used for both socket and channel interleave */
  342. static int skx_granularity[] = { 6, 8, 12, 30 };
  343. static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
  344. {
  345. addr >>= shift;
  346. addr /= ways;
  347. addr <<= shift;
  348. return addr | (lowbits & ((1ull << shift) - 1));
  349. }
  350. static bool skx_tad_decode(struct decoded_addr *res)
  351. {
  352. int i;
  353. u32 base, wayness, chnilvoffset;
  354. int skt_interleave_bit, chn_interleave_bit;
  355. u64 channel_addr;
  356. for (i = 0; i < SKX_MAX_TAD; i++) {
  357. SKX_GET_TADBASE(res->dev, res->imc, i, base);
  358. SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
  359. if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
  360. goto tad_found;
  361. }
  362. edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr);
  363. return false;
  364. tad_found:
  365. res->sktways = SKX_TAD_SKTWAYS(wayness);
  366. res->chanways = SKX_TAD_CHNWAYS(wayness);
  367. skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
  368. chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
  369. SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
  370. channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
  371. if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
  372. /* Must handle channel first, then socket */
  373. channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
  374. res->chanways, channel_addr);
  375. channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
  376. res->sktways, channel_addr);
  377. } else {
  378. /* Handle socket then channel. Preserve low bits from original address */
  379. channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
  380. res->sktways, res->addr);
  381. channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
  382. res->chanways, res->addr);
  383. }
  384. res->chan_addr = channel_addr;
  385. edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n",
  386. res->addr, res->chan_addr, res->sktways, res->chanways);
  387. return true;
  388. }
  389. #define SKX_MAX_RIR 4
  390. #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \
  391. pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
  392. 0x108 + 4 * (i), &(reg))
  393. #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \
  394. pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \
  395. 0x120 + 16 * (idx) + 4 * (i), &(reg))
  396. #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
  397. #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
  398. #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
  399. #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
  400. #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
  401. static bool skx_rir_decode(struct decoded_addr *res)
  402. {
  403. int i, idx, chan_rank;
  404. int shift;
  405. u32 rirway, rirlv;
  406. u64 rank_addr, prev_limit = 0, limit;
  407. if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
  408. shift = 6;
  409. else
  410. shift = 13;
  411. for (i = 0; i < SKX_MAX_RIR; i++) {
  412. SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
  413. limit = SKX_RIR_LIMIT(rirway);
  414. if (SKX_RIR_VALID(rirway)) {
  415. if (prev_limit <= res->chan_addr &&
  416. res->chan_addr <= limit)
  417. goto rir_found;
  418. }
  419. prev_limit = limit;
  420. }
  421. edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr);
  422. return false;
  423. rir_found:
  424. rank_addr = res->chan_addr >> shift;
  425. rank_addr /= SKX_RIR_WAYS(rirway);
  426. rank_addr <<= shift;
  427. rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
  428. res->rank_address = rank_addr;
  429. idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
  430. SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
  431. res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
  432. chan_rank = SKX_RIR_CHAN_RANK(rirlv);
  433. res->channel_rank = chan_rank;
  434. res->dimm = chan_rank / 4;
  435. res->rank = chan_rank % 4;
  436. edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n",
  437. res->addr, res->dimm, res->rank,
  438. res->channel_rank, res->rank_address);
  439. return true;
  440. }
  441. static u8 skx_close_row[] = {
  442. 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34
  443. };
  444. static u8 skx_close_column[] = {
  445. 3, 4, 5, 14, 19, 23, 24, 25, 26, 27
  446. };
  447. static u8 skx_open_row[] = {
  448. 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34
  449. };
  450. static u8 skx_open_column[] = {
  451. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
  452. };
  453. static u8 skx_open_fine_column[] = {
  454. 3, 4, 5, 7, 8, 9, 10, 11, 12, 13
  455. };
  456. static int skx_bits(u64 addr, int nbits, u8 *bits)
  457. {
  458. int i, res = 0;
  459. for (i = 0; i < nbits; i++)
  460. res |= ((addr >> bits[i]) & 1) << i;
  461. return res;
  462. }
  463. static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
  464. {
  465. int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
  466. if (do_xor)
  467. ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
  468. return ret;
  469. }
  470. static bool skx_mad_decode(struct decoded_addr *r)
  471. {
  472. struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
  473. int bg0 = dimm->fine_grain_bank ? 6 : 13;
  474. if (dimm->close_pg) {
  475. r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
  476. r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
  477. r->column |= 0x400; /* C10 is autoprecharge, always set */
  478. r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
  479. r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
  480. } else {
  481. r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
  482. if (dimm->fine_grain_bank)
  483. r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
  484. else
  485. r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
  486. r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
  487. r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
  488. }
  489. r->row &= (1u << dimm->rowbits) - 1;
  490. edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n",
  491. r->addr, r->row, r->column, r->bank_address,
  492. r->bank_group);
  493. return true;
  494. }
  495. static bool skx_decode(struct decoded_addr *res)
  496. {
  497. return skx_sad_decode(res) && skx_tad_decode(res) &&
  498. skx_rir_decode(res) && skx_mad_decode(res);
  499. }
  500. static struct notifier_block skx_mce_dec = {
  501. .notifier_call = skx_mce_check_error,
  502. .priority = MCE_PRIO_EDAC,
  503. };
  504. #ifdef CONFIG_EDAC_DEBUG
  505. /*
  506. * Debug feature.
  507. * Exercise the address decode logic by writing an address to
  508. * /sys/kernel/debug/edac/skx_test/addr.
  509. */
  510. static struct dentry *skx_test;
  511. static int debugfs_u64_set(void *data, u64 val)
  512. {
  513. struct mce m;
  514. pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
  515. memset(&m, 0, sizeof(m));
  516. /* ADDRV + MemRd + Unknown channel */
  517. m.status = MCI_STATUS_ADDRV + 0x90;
  518. /* One corrected error */
  519. m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
  520. m.addr = val;
  521. skx_mce_check_error(NULL, 0, &m);
  522. return 0;
  523. }
  524. DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
  525. static void setup_skx_debug(void)
  526. {
  527. skx_test = edac_debugfs_create_dir("skx_test");
  528. if (!skx_test)
  529. return;
  530. if (!edac_debugfs_create_file("addr", 0200, skx_test,
  531. NULL, &fops_u64_wo)) {
  532. debugfs_remove(skx_test);
  533. skx_test = NULL;
  534. }
  535. }
  536. static void teardown_skx_debug(void)
  537. {
  538. debugfs_remove_recursive(skx_test);
  539. }
  540. #else
  541. static inline void setup_skx_debug(void) {}
  542. static inline void teardown_skx_debug(void) {}
  543. #endif /*CONFIG_EDAC_DEBUG*/
  544. /*
  545. * skx_init:
  546. * make sure we are running on the correct cpu model
  547. * search for all the devices we need
  548. * check which DIMMs are present.
  549. */
  550. static int __init skx_init(void)
  551. {
  552. const struct x86_cpu_id *id;
  553. struct res_config *cfg;
  554. const struct munit *m;
  555. const char *owner;
  556. int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8};
  557. u8 mc = 0, src_id, node_id;
  558. struct skx_dev *d;
  559. edac_dbg(2, "\n");
  560. owner = edac_get_owner();
  561. if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
  562. return -EBUSY;
  563. if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
  564. return -ENODEV;
  565. id = x86_match_cpu(skx_cpuids);
  566. if (!id)
  567. return -ENODEV;
  568. cfg = (struct res_config *)id->driver_data;
  569. rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm);
  570. if (rc)
  571. return rc;
  572. rc = skx_get_all_bus_mappings(cfg, &skx_edac_list);
  573. if (rc < 0)
  574. goto fail;
  575. if (rc == 0) {
  576. edac_dbg(2, "No memory controllers found\n");
  577. return -ENODEV;
  578. }
  579. skx_num_sockets = rc;
  580. for (m = skx_all_munits; m->did; m++) {
  581. rc = get_all_munits(m);
  582. if (rc < 0)
  583. goto fail;
  584. if (rc != m->per_socket * skx_num_sockets) {
  585. edac_dbg(2, "Expected %d, got %d of 0x%x\n",
  586. m->per_socket * skx_num_sockets, rc, m->did);
  587. rc = -ENODEV;
  588. goto fail;
  589. }
  590. }
  591. list_for_each_entry(d, skx_edac_list, list) {
  592. rc = skx_get_src_id(d, 0xf0, &src_id);
  593. if (rc < 0)
  594. goto fail;
  595. rc = skx_get_node_id(d, &node_id);
  596. if (rc < 0)
  597. goto fail;
  598. edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
  599. for (i = 0; i < SKX_NUM_IMC; i++) {
  600. d->imc[i].mc = mc++;
  601. d->imc[i].lmc = i;
  602. d->imc[i].src_id = src_id;
  603. d->imc[i].node_id = node_id;
  604. rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
  605. "Skylake Socket", EDAC_MOD_STR,
  606. skx_get_dimm_config, cfg);
  607. if (rc < 0)
  608. goto fail;
  609. }
  610. }
  611. skx_set_decode(skx_decode, skx_show_retry_rd_err_log);
  612. if (nvdimm_count && skx_adxl_get() != -ENODEV) {
  613. skx_set_decode(NULL, skx_show_retry_rd_err_log);
  614. } else {
  615. if (nvdimm_count)
  616. skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n");
  617. skx_set_decode(skx_decode, skx_show_retry_rd_err_log);
  618. }
  619. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  620. opstate_init();
  621. setup_skx_debug();
  622. mce_register_decode_chain(&skx_mce_dec);
  623. return 0;
  624. fail:
  625. skx_remove();
  626. return rc;
  627. }
  628. static void __exit skx_exit(void)
  629. {
  630. edac_dbg(2, "\n");
  631. mce_unregister_decode_chain(&skx_mce_dec);
  632. teardown_skx_debug();
  633. if (nvdimm_count)
  634. skx_adxl_put();
  635. skx_remove();
  636. }
  637. module_init(skx_init);
  638. module_exit(skx_exit);
  639. module_param(edac_op_state, int, 0444);
  640. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
  641. MODULE_LICENSE("GPL v2");
  642. MODULE_AUTHOR("Tony Luck");
  643. MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");