qcom_edac.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/edac.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/kernel.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/soc/qcom/llcc-qcom.h>
  12. #include "edac_mc.h"
  13. #include "edac_device.h"
  14. #define EDAC_LLCC "qcom_llcc"
  15. #define LLCC_ERP_PANIC_ON_CE 1
  16. #ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
  17. #define LLCC_ERP_PANIC_ON_UE 1
  18. #else
  19. #define LLCC_ERP_PANIC_ON_UE 0
  20. #endif
  21. #define TRP_SYN_REG_CNT 6
  22. #define DRP_SYN_REG_CNT 8
  23. #define LLCC_COMMON_STATUS0_V2 0x0003000c
  24. #define LLCC_COMMON_STATUS0_V21 0x0003400c
  25. #define LLCC_COMMON_STATUS0 edac_regs[LLCC_COMMON_STATUS0_num]
  26. #define LLCC_LB_CNT_MASK GENMASK(31, 28)
  27. #define LLCC_LB_CNT_SHIFT 28
  28. /* Single & double bit syndrome register offsets */
  29. #define TRP_ECC_SB_ERR_SYN0 0x0002034c
  30. #define TRP_ECC_DB_ERR_SYN0 0x00020370
  31. #define DRP_ECC_SB_ERR_SYN0_V2 0x0004204c
  32. #define DRP_ECC_SB_ERR_SYN0_V21 0x0005204c
  33. #define DRP_ECC_SB_ERR_SYN0 edac_regs[DRP_ECC_SB_ERR_SYN0_num]
  34. #define DRP_ECC_DB_ERR_SYN0_V2 0x00042070
  35. #define DRP_ECC_DB_ERR_SYN0_V21 0x00052070
  36. #define DRP_ECC_DB_ERR_SYN0 edac_regs[DRP_ECC_DB_ERR_SYN0_num]
  37. /* Error register offsets */
  38. #define TRP_ECC_ERROR_STATUS1 0x00020348
  39. #define TRP_ECC_ERROR_STATUS0 0x00020344
  40. #define DRP_ECC_ERROR_STATUS1_V2 0x00042048
  41. #define DRP_ECC_ERROR_STATUS1_V21 0x00052048
  42. #define DRP_ECC_ERROR_STATUS1 edac_regs[DRP_ECC_ERROR_STATUS1_num]
  43. #define DRP_ECC_ERROR_STATUS0_V2 0x00042044
  44. #define DRP_ECC_ERROR_STATUS0_V21 0x00052044
  45. #define DRP_ECC_ERROR_STATUS0 edac_regs[DRP_ECC_ERROR_STATUS0_num]
  46. /* TRP, DRP interrupt register offsets */
  47. #define DRP_INTERRUPT_STATUS_V2 0x00041000
  48. #define DRP_INTERRUPT_STATUS_V21 0x00050020
  49. #define DRP_INTERRUPT_STATUS edac_regs[DRP_INTERRUPT_STATUS_num]
  50. #define TRP_INTERRUPT_0_STATUS 0x00020480
  51. #define DRP_INTERRUPT_CLEAR_V2 0x00041008
  52. #define DRP_INTERRUPT_CLEAR_V21 0x00050028
  53. #define DRP_INTERRUPT_CLEAR edac_regs[DRP_INTERRUPT_CLEAR_num]
  54. #define DRP_ECC_ERROR_CNTR_CLEAR_V2 0x00040004
  55. #define DRP_ECC_ERROR_CNTR_CLEAR_V21 0x00050004
  56. #define DRP_ECC_ERROR_CNTR_CLEAR edac_regs[DRP_ECC_ERROR_CNTR_CLEAR_num]
  57. #define TRP_INTERRUPT_0_CLEAR 0x00020484
  58. #define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440
  59. /* Mask and shift macros */
  60. #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)
  61. #define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16)
  62. #define ECC_DB_ERR_WAYS_SHIFT BIT(4)
  63. #define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)
  64. #define ECC_SB_ERR_COUNT_SHIFT BIT(4)
  65. #define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0)
  66. #define SB_ECC_ERROR BIT(0)
  67. #define DB_ECC_ERROR BIT(1)
  68. #define DRP_TRP_INT_CLEAR GENMASK(1, 0)
  69. #define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
  70. /* Config registers offsets*/
  71. #define DRP_ECC_ERROR_CFG_V2 0x00040000
  72. #define DRP_ECC_ERROR_CFG_V21 0x00050000
  73. #define DRP_ECC_ERROR_CFG edac_regs[DRP_ECC_ERROR_CFG_num]
  74. /* Tag RAM, Data RAM interrupt register offsets */
  75. #define CMN_INTERRUPT_0_ENABLE_V2 0x0003001c
  76. #define CMN_INTERRUPT_0_ENABLE_V21 0x0003401c
  77. #define CMN_INTERRUPT_0_ENABLE edac_regs[CMN_INTERRUPT_0_ENABLE_num]
  78. #define CMN_INTERRUPT_2_ENABLE_V2 0x0003003c
  79. #define CMN_INTERRUPT_2_ENABLE_V21 0x0003403c
  80. #define CMN_INTERRUPT_2_ENABLE edac_regs[CMN_INTERRUPT_2_ENABLE_num]
  81. #define TRP_INTERRUPT_0_ENABLE 0x00020488
  82. #define DRP_INTERRUPT_ENABLE_V2 0x0004100c
  83. #define DRP_INTERRUPT_ENABLE_V21 0x0005002C
  84. #define DRP_INTERRUPT_ENABLE edac_regs[DRP_INTERRUPT_ENABLE_num]
  85. #define SB_ERROR_THRESHOLD 0x1
  86. #define SB_ERROR_THRESHOLD_SHIFT 24
  87. #define SB_DB_TRP_INTERRUPT_ENABLE 0x3
  88. #define TRP0_INTERRUPT_ENABLE 0x1
  89. #define DRP0_INTERRUPT_ENABLE BIT(6)
  90. #define SB_DB_DRP_INTERRUPT_ENABLE 0x3
  91. enum {
  92. LLCC_DRAM_CE = 0,
  93. LLCC_DRAM_UE,
  94. LLCC_TRAM_CE,
  95. LLCC_TRAM_UE,
  96. };
  97. enum {
  98. LLCC_COMMON_STATUS0_num = 0,
  99. DRP_ECC_SB_ERR_SYN0_num,
  100. DRP_ECC_DB_ERR_SYN0_num,
  101. DRP_ECC_ERROR_STATUS1_num,
  102. DRP_ECC_ERROR_STATUS0_num,
  103. DRP_INTERRUPT_STATUS_num,
  104. DRP_INTERRUPT_CLEAR_num,
  105. DRP_ECC_ERROR_CNTR_CLEAR_num,
  106. DRP_ECC_ERROR_CFG_num,
  107. CMN_INTERRUPT_0_ENABLE_num,
  108. CMN_INTERRUPT_2_ENABLE_num,
  109. DRP_INTERRUPT_ENABLE_num,
  110. EDAC_REGS_MAX,
  111. };
  112. static int poll_msec = 5000;
  113. module_param(poll_msec, int, 0444);
  114. static unsigned int edac_regs_v2[EDAC_REGS_MAX] = {
  115. LLCC_COMMON_STATUS0_V2,
  116. DRP_ECC_SB_ERR_SYN0_V2,
  117. DRP_ECC_DB_ERR_SYN0_V2,
  118. DRP_ECC_ERROR_STATUS1_V2,
  119. DRP_ECC_ERROR_STATUS0_V2,
  120. DRP_INTERRUPT_STATUS_V2,
  121. DRP_INTERRUPT_CLEAR_V2,
  122. DRP_ECC_ERROR_CNTR_CLEAR_V2,
  123. DRP_ECC_ERROR_CFG_V2,
  124. CMN_INTERRUPT_0_ENABLE_V2,
  125. CMN_INTERRUPT_2_ENABLE_V2,
  126. DRP_INTERRUPT_ENABLE_V2,
  127. };
  128. static unsigned int edac_regs_v21[EDAC_REGS_MAX] = {
  129. LLCC_COMMON_STATUS0_V21,
  130. DRP_ECC_SB_ERR_SYN0_V21,
  131. DRP_ECC_DB_ERR_SYN0_V21,
  132. DRP_ECC_ERROR_STATUS1_V21,
  133. DRP_ECC_ERROR_STATUS0_V21,
  134. DRP_INTERRUPT_STATUS_V21,
  135. DRP_INTERRUPT_CLEAR_V21,
  136. DRP_ECC_ERROR_CNTR_CLEAR_V21,
  137. DRP_ECC_ERROR_CFG_V21,
  138. CMN_INTERRUPT_0_ENABLE_V21,
  139. CMN_INTERRUPT_2_ENABLE_V21,
  140. DRP_INTERRUPT_ENABLE_V21,
  141. };
  142. static unsigned int *edac_regs = edac_regs_v2;
  143. static struct llcc_edac_reg_data edac_reg_data_v2[] = {
  144. [LLCC_DRAM_CE] = {
  145. .name = "DRAM Single-bit",
  146. .synd_reg = DRP_ECC_SB_ERR_SYN0_V2,
  147. .count_status_reg = DRP_ECC_ERROR_STATUS1_V2,
  148. .ways_status_reg = DRP_ECC_ERROR_STATUS0_V2,
  149. .reg_cnt = DRP_SYN_REG_CNT,
  150. .count_mask = ECC_SB_ERR_COUNT_MASK,
  151. .ways_mask = ECC_SB_ERR_WAYS_MASK,
  152. .count_shift = ECC_SB_ERR_COUNT_SHIFT,
  153. },
  154. [LLCC_DRAM_UE] = {
  155. .name = "DRAM Double-bit",
  156. .synd_reg = DRP_ECC_DB_ERR_SYN0_V2,
  157. .count_status_reg = DRP_ECC_ERROR_STATUS1_V2,
  158. .ways_status_reg = DRP_ECC_ERROR_STATUS0_V2,
  159. .reg_cnt = DRP_SYN_REG_CNT,
  160. .count_mask = ECC_DB_ERR_COUNT_MASK,
  161. .ways_mask = ECC_DB_ERR_WAYS_MASK,
  162. .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
  163. },
  164. [LLCC_TRAM_CE] = {
  165. .name = "TRAM Single-bit",
  166. .synd_reg = TRP_ECC_SB_ERR_SYN0,
  167. .count_status_reg = TRP_ECC_ERROR_STATUS1,
  168. .ways_status_reg = TRP_ECC_ERROR_STATUS0,
  169. .reg_cnt = TRP_SYN_REG_CNT,
  170. .count_mask = ECC_SB_ERR_COUNT_MASK,
  171. .ways_mask = ECC_SB_ERR_WAYS_MASK,
  172. .count_shift = ECC_SB_ERR_COUNT_SHIFT,
  173. },
  174. [LLCC_TRAM_UE] = {
  175. .name = "TRAM Double-bit",
  176. .synd_reg = TRP_ECC_DB_ERR_SYN0,
  177. .count_status_reg = TRP_ECC_ERROR_STATUS1,
  178. .ways_status_reg = TRP_ECC_ERROR_STATUS0,
  179. .reg_cnt = TRP_SYN_REG_CNT,
  180. .count_mask = ECC_DB_ERR_COUNT_MASK,
  181. .ways_mask = ECC_DB_ERR_WAYS_MASK,
  182. .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
  183. },
  184. };
  185. static struct llcc_edac_reg_data edac_reg_data_v21[] = {
  186. [LLCC_DRAM_CE] = {
  187. .name = "DRAM Single-bit",
  188. .synd_reg = DRP_ECC_SB_ERR_SYN0_V21,
  189. .count_status_reg = DRP_ECC_ERROR_STATUS1_V21,
  190. .ways_status_reg = DRP_ECC_ERROR_STATUS0_V21,
  191. .reg_cnt = DRP_SYN_REG_CNT,
  192. .count_mask = ECC_SB_ERR_COUNT_MASK,
  193. .ways_mask = ECC_SB_ERR_WAYS_MASK,
  194. .count_shift = ECC_SB_ERR_COUNT_SHIFT,
  195. },
  196. [LLCC_DRAM_UE] = {
  197. .name = "DRAM Double-bit",
  198. .synd_reg = DRP_ECC_DB_ERR_SYN0_V21,
  199. .count_status_reg = DRP_ECC_ERROR_STATUS1_V21,
  200. .ways_status_reg = DRP_ECC_ERROR_STATUS0_V21,
  201. .reg_cnt = DRP_SYN_REG_CNT,
  202. .count_mask = ECC_DB_ERR_COUNT_MASK,
  203. .ways_mask = ECC_DB_ERR_WAYS_MASK,
  204. .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
  205. },
  206. [LLCC_TRAM_CE] = {
  207. .name = "TRAM Single-bit",
  208. .synd_reg = TRP_ECC_SB_ERR_SYN0,
  209. .count_status_reg = TRP_ECC_ERROR_STATUS1,
  210. .ways_status_reg = TRP_ECC_ERROR_STATUS0,
  211. .reg_cnt = TRP_SYN_REG_CNT,
  212. .count_mask = ECC_SB_ERR_COUNT_MASK,
  213. .ways_mask = ECC_SB_ERR_WAYS_MASK,
  214. .count_shift = ECC_SB_ERR_COUNT_SHIFT,
  215. },
  216. [LLCC_TRAM_UE] = {
  217. .name = "TRAM Double-bit",
  218. .synd_reg = TRP_ECC_DB_ERR_SYN0,
  219. .count_status_reg = TRP_ECC_ERROR_STATUS1,
  220. .ways_status_reg = TRP_ECC_ERROR_STATUS0,
  221. .reg_cnt = TRP_SYN_REG_CNT,
  222. .count_mask = ECC_DB_ERR_COUNT_MASK,
  223. .ways_mask = ECC_DB_ERR_WAYS_MASK,
  224. .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
  225. },
  226. };
  227. static struct llcc_edac_reg_data *edac_reg_data = edac_reg_data_v2;
  228. static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
  229. {
  230. u32 sb_err_threshold;
  231. int ret;
  232. /*
  233. * Configure interrupt enable registers such that Tag, Data RAM related
  234. * interrupts are propagated to interrupt controller for servicing
  235. */
  236. ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_0_ENABLE,
  237. TRP0_INTERRUPT_ENABLE,
  238. TRP0_INTERRUPT_ENABLE);
  239. if (ret)
  240. return ret;
  241. ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
  242. SB_DB_TRP_INTERRUPT_ENABLE,
  243. SB_DB_TRP_INTERRUPT_ENABLE);
  244. if (ret)
  245. return ret;
  246. sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
  247. ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
  248. sb_err_threshold);
  249. if (ret)
  250. return ret;
  251. ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_0_ENABLE,
  252. DRP0_INTERRUPT_ENABLE,
  253. DRP0_INTERRUPT_ENABLE);
  254. if (ret)
  255. return ret;
  256. ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
  257. SB_DB_DRP_INTERRUPT_ENABLE);
  258. return ret;
  259. }
  260. /* Clear the error interrupt and counter registers */
  261. static int
  262. qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv)
  263. {
  264. int ret = 0;
  265. switch (err_type) {
  266. case LLCC_DRAM_CE:
  267. case LLCC_DRAM_UE:
  268. ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
  269. DRP_TRP_INT_CLEAR);
  270. if (ret)
  271. return ret;
  272. ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
  273. DRP_TRP_CNT_CLEAR);
  274. if (ret)
  275. return ret;
  276. break;
  277. case LLCC_TRAM_CE:
  278. case LLCC_TRAM_UE:
  279. ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
  280. DRP_TRP_INT_CLEAR);
  281. if (ret)
  282. return ret;
  283. ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
  284. DRP_TRP_CNT_CLEAR);
  285. if (ret)
  286. return ret;
  287. break;
  288. default:
  289. ret = -EINVAL;
  290. edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
  291. err_type);
  292. }
  293. return ret;
  294. }
  295. /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
  296. static int
  297. dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
  298. {
  299. struct llcc_edac_reg_data reg_data = edac_reg_data[err_type];
  300. int err_cnt, err_ways, ret, i;
  301. u32 synd_reg, synd_val;
  302. for (i = 0; i < reg_data.reg_cnt; i++) {
  303. synd_reg = reg_data.synd_reg + (i * 4);
  304. ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
  305. &synd_val);
  306. if (ret)
  307. goto clear;
  308. edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
  309. reg_data.name, i, synd_val);
  310. }
  311. ret = regmap_read(drv->regmap,
  312. drv->offsets[bank] + reg_data.count_status_reg,
  313. &err_cnt);
  314. if (ret)
  315. goto clear;
  316. err_cnt &= reg_data.count_mask;
  317. err_cnt >>= reg_data.count_shift;
  318. edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n",
  319. reg_data.name, err_cnt);
  320. ret = regmap_read(drv->regmap,
  321. drv->offsets[bank] + reg_data.ways_status_reg,
  322. &err_ways);
  323. if (ret)
  324. goto clear;
  325. err_ways &= reg_data.ways_mask;
  326. err_ways >>= reg_data.ways_shift;
  327. edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error ways: 0x%4x\n",
  328. reg_data.name, err_ways);
  329. clear:
  330. return qcom_llcc_clear_error_status(err_type, drv);
  331. }
  332. static void llcc_edac_handle_ce(struct edac_device_ctl_info *edac_dev,
  333. int inst_nr, int block_nr, const char *msg)
  334. {
  335. edac_device_handle_ce(edac_dev, inst_nr, block_nr, msg);
  336. #ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_CE
  337. panic("EDAC %s CE: %s\n", edac_dev->ctl_name, msg);
  338. #endif
  339. }
  340. static int
  341. dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
  342. {
  343. struct llcc_drv_data *drv = edev_ctl->dev->platform_data;
  344. int ret;
  345. ret = dump_syn_reg_values(drv, bank, err_type);
  346. if (ret)
  347. return ret;
  348. switch (err_type) {
  349. case LLCC_DRAM_CE:
  350. llcc_edac_handle_ce(edev_ctl, 0, bank,
  351. "LLCC Data RAM correctable Error");
  352. break;
  353. case LLCC_DRAM_UE:
  354. edac_device_handle_ue(edev_ctl, 0, bank,
  355. "LLCC Data RAM uncorrectable Error");
  356. break;
  357. case LLCC_TRAM_CE:
  358. llcc_edac_handle_ce(edev_ctl, 0, bank,
  359. "LLCC Tag RAM correctable Error");
  360. break;
  361. case LLCC_TRAM_UE:
  362. edac_device_handle_ue(edev_ctl, 0, bank,
  363. "LLCC Tag RAM uncorrectable Error");
  364. break;
  365. default:
  366. ret = -EINVAL;
  367. edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
  368. err_type);
  369. }
  370. return ret;
  371. }
  372. static irqreturn_t
  373. llcc_ecc_irq_handler(int irq, void *edev_ctl)
  374. {
  375. struct edac_device_ctl_info *edac_dev_ctl = edev_ctl;
  376. struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data;
  377. irqreturn_t irq_rc = IRQ_NONE;
  378. u32 drp_error, trp_error, i;
  379. bool irq_handled = false;
  380. int ret;
  381. /* Iterate over the banks and look for Tag RAM or Data RAM errors */
  382. for (i = 0; i < drv->num_banks; i++) {
  383. ret = regmap_read(drv->regmap,
  384. drv->offsets[i] + DRP_INTERRUPT_STATUS,
  385. &drp_error);
  386. if (!ret && (drp_error & SB_ECC_ERROR)) {
  387. edac_printk(KERN_CRIT, EDAC_LLCC,
  388. "Single Bit Error detected in Data RAM\n");
  389. ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
  390. } else if (!ret && (drp_error & DB_ECC_ERROR)) {
  391. edac_printk(KERN_CRIT, EDAC_LLCC,
  392. "Double Bit Error detected in Data RAM\n");
  393. ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
  394. }
  395. if (!ret)
  396. irq_handled = true;
  397. ret = regmap_read(drv->regmap,
  398. drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
  399. &trp_error);
  400. if (!ret && (trp_error & SB_ECC_ERROR)) {
  401. edac_printk(KERN_CRIT, EDAC_LLCC,
  402. "Single Bit Error detected in Tag RAM\n");
  403. ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
  404. } else if (!ret && (trp_error & DB_ECC_ERROR)) {
  405. edac_printk(KERN_CRIT, EDAC_LLCC,
  406. "Double Bit Error detected in Tag RAM\n");
  407. ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
  408. }
  409. if (!ret)
  410. irq_handled = true;
  411. }
  412. if (irq_handled)
  413. irq_rc = IRQ_HANDLED;
  414. return irq_rc;
  415. }
  416. static void qcom_llcc_poll_cache_errors(struct edac_device_ctl_info *edev_ctl)
  417. {
  418. llcc_ecc_irq_handler(0, edev_ctl);
  419. }
  420. static int qcom_llcc_edac_probe(struct platform_device *pdev)
  421. {
  422. struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
  423. struct edac_device_ctl_info *edev_ctl;
  424. struct device *dev = &pdev->dev;
  425. int ecc_irq;
  426. int rc;
  427. if (llcc_driv_data->llcc_ver > 20) {
  428. edac_reg_data = edac_reg_data_v21;
  429. edac_regs = edac_regs_v21;
  430. }
  431. /* Allocate edac control info */
  432. edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
  433. llcc_driv_data->num_banks, 1,
  434. NULL, 0,
  435. edac_device_alloc_index());
  436. if (!edev_ctl)
  437. return -ENOMEM;
  438. edev_ctl->dev = dev;
  439. edev_ctl->mod_name = dev_name(dev);
  440. edev_ctl->dev_name = dev_name(dev);
  441. edev_ctl->ctl_name = "llcc";
  442. edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
  443. /* Request for ecc irq */
  444. ecc_irq = llcc_driv_data->ecc_irq;
  445. if (ecc_irq < 0) {
  446. dev_info(dev, "No ECC IRQ; defaulting to polling mode\n");
  447. edev_ctl->poll_msec = poll_msec;
  448. edev_ctl->edac_check = qcom_llcc_poll_cache_errors;
  449. }
  450. rc = edac_device_add_device(edev_ctl);
  451. if (rc)
  452. goto out_mem;
  453. if (ecc_irq >= 0) {
  454. rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
  455. if (rc)
  456. goto out_dev;
  457. rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
  458. IRQF_SHARED | IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  459. "llcc_ecc", edev_ctl);
  460. if (rc)
  461. goto out_dev;
  462. }
  463. platform_set_drvdata(pdev, edev_ctl);
  464. return rc;
  465. out_dev:
  466. edac_device_del_device(edev_ctl->dev);
  467. out_mem:
  468. edac_device_free_ctl_info(edev_ctl);
  469. return rc;
  470. }
  471. static int qcom_llcc_edac_remove(struct platform_device *pdev)
  472. {
  473. struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
  474. edac_device_del_device(edev_ctl->dev);
  475. edac_device_free_ctl_info(edev_ctl);
  476. return 0;
  477. }
  478. static struct platform_driver qcom_llcc_edac_driver = {
  479. .probe = qcom_llcc_edac_probe,
  480. .remove = qcom_llcc_edac_remove,
  481. .driver = {
  482. .name = "qcom_llcc_edac",
  483. },
  484. };
  485. module_platform_driver(qcom_llcc_edac_driver);
  486. MODULE_DESCRIPTION("QCOM EDAC driver");
  487. MODULE_LICENSE("GPL v2");