pnd2_edac.h 5.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Register bitfield descriptions for Pondicherry2 memory controller.
  4. *
  5. * Copyright (c) 2016, Intel Corporation.
  6. */
  7. #ifndef _PND2_REGS_H
  8. #define _PND2_REGS_H
  9. struct b_cr_touud_lo_pci {
  10. u32 lock : 1;
  11. u32 reserved_1 : 19;
  12. u32 touud : 12;
  13. };
  14. #define b_cr_touud_lo_pci_port 0x4c
  15. #define b_cr_touud_lo_pci_offset 0xa8
  16. #define b_cr_touud_lo_pci_r_opcode 0x04
  17. struct b_cr_touud_hi_pci {
  18. u32 touud : 7;
  19. u32 reserved_0 : 25;
  20. };
  21. #define b_cr_touud_hi_pci_port 0x4c
  22. #define b_cr_touud_hi_pci_offset 0xac
  23. #define b_cr_touud_hi_pci_r_opcode 0x04
  24. struct b_cr_tolud_pci {
  25. u32 lock : 1;
  26. u32 reserved_0 : 19;
  27. u32 tolud : 12;
  28. };
  29. #define b_cr_tolud_pci_port 0x4c
  30. #define b_cr_tolud_pci_offset 0xbc
  31. #define b_cr_tolud_pci_r_opcode 0x04
  32. struct b_cr_mchbar_lo_pci {
  33. u32 enable : 1;
  34. u32 pad_3_1 : 3;
  35. u32 pad_14_4: 11;
  36. u32 base: 17;
  37. };
  38. struct b_cr_mchbar_hi_pci {
  39. u32 base : 7;
  40. u32 pad_31_7 : 25;
  41. };
  42. /* Symmetric region */
  43. struct b_cr_slice_channel_hash {
  44. u64 slice_1_disabled : 1;
  45. u64 hvm_mode : 1;
  46. u64 interleave_mode : 2;
  47. u64 slice_0_mem_disabled : 1;
  48. u64 reserved_0 : 1;
  49. u64 slice_hash_mask : 14;
  50. u64 reserved_1 : 11;
  51. u64 enable_pmi_dual_data_mode : 1;
  52. u64 ch_1_disabled : 1;
  53. u64 reserved_2 : 1;
  54. u64 sym_slice0_channel_enabled : 2;
  55. u64 sym_slice1_channel_enabled : 2;
  56. u64 ch_hash_mask : 14;
  57. u64 reserved_3 : 11;
  58. u64 lock : 1;
  59. };
  60. #define b_cr_slice_channel_hash_port 0x4c
  61. #define b_cr_slice_channel_hash_offset 0x4c58
  62. #define b_cr_slice_channel_hash_r_opcode 0x06
  63. struct b_cr_mot_out_base_mchbar {
  64. u32 reserved_0 : 14;
  65. u32 mot_out_base : 15;
  66. u32 reserved_1 : 1;
  67. u32 tr_en : 1;
  68. u32 imr_en : 1;
  69. };
  70. #define b_cr_mot_out_base_mchbar_port 0x4c
  71. #define b_cr_mot_out_base_mchbar_offset 0x6af0
  72. #define b_cr_mot_out_base_mchbar_r_opcode 0x00
  73. struct b_cr_mot_out_mask_mchbar {
  74. u32 reserved_0 : 14;
  75. u32 mot_out_mask : 15;
  76. u32 reserved_1 : 1;
  77. u32 ia_iwb_en : 1;
  78. u32 gt_iwb_en : 1;
  79. };
  80. #define b_cr_mot_out_mask_mchbar_port 0x4c
  81. #define b_cr_mot_out_mask_mchbar_offset 0x6af4
  82. #define b_cr_mot_out_mask_mchbar_r_opcode 0x00
  83. struct b_cr_asym_mem_region0_mchbar {
  84. u32 pad : 4;
  85. u32 slice0_asym_base : 11;
  86. u32 pad_18_15 : 4;
  87. u32 slice0_asym_limit : 11;
  88. u32 slice0_asym_channel_select : 1;
  89. u32 slice0_asym_enable : 1;
  90. };
  91. #define b_cr_asym_mem_region0_mchbar_port 0x4c
  92. #define b_cr_asym_mem_region0_mchbar_offset 0x6e40
  93. #define b_cr_asym_mem_region0_mchbar_r_opcode 0x00
  94. struct b_cr_asym_mem_region1_mchbar {
  95. u32 pad : 4;
  96. u32 slice1_asym_base : 11;
  97. u32 pad_18_15 : 4;
  98. u32 slice1_asym_limit : 11;
  99. u32 slice1_asym_channel_select : 1;
  100. u32 slice1_asym_enable : 1;
  101. };
  102. #define b_cr_asym_mem_region1_mchbar_port 0x4c
  103. #define b_cr_asym_mem_region1_mchbar_offset 0x6e44
  104. #define b_cr_asym_mem_region1_mchbar_r_opcode 0x00
  105. /* Some bit fields moved in above two structs on Denverton */
  106. struct b_cr_asym_mem_region_denverton {
  107. u32 pad : 4;
  108. u32 slice_asym_base : 8;
  109. u32 pad_19_12 : 8;
  110. u32 slice_asym_limit : 8;
  111. u32 pad_28_30 : 3;
  112. u32 slice_asym_enable : 1;
  113. };
  114. struct b_cr_asym_2way_mem_region_mchbar {
  115. u32 pad : 2;
  116. u32 asym_2way_intlv_mode : 2;
  117. u32 asym_2way_base : 11;
  118. u32 pad_16_15 : 2;
  119. u32 asym_2way_limit : 11;
  120. u32 pad_30_28 : 3;
  121. u32 asym_2way_interleave_enable : 1;
  122. };
  123. #define b_cr_asym_2way_mem_region_mchbar_port 0x4c
  124. #define b_cr_asym_2way_mem_region_mchbar_offset 0x6e50
  125. #define b_cr_asym_2way_mem_region_mchbar_r_opcode 0x00
  126. /* Apollo Lake d-unit */
  127. struct d_cr_drp0 {
  128. u32 rken0 : 1;
  129. u32 rken1 : 1;
  130. u32 ddmen : 1;
  131. u32 rsvd3 : 1;
  132. u32 dwid : 2;
  133. u32 dden : 3;
  134. u32 rsvd13_9 : 5;
  135. u32 rsien : 1;
  136. u32 bahen : 1;
  137. u32 rsvd18_16 : 3;
  138. u32 caswizzle : 2;
  139. u32 eccen : 1;
  140. u32 dramtype : 3;
  141. u32 blmode : 3;
  142. u32 addrdec : 2;
  143. u32 dramdevice_pr : 2;
  144. };
  145. #define d_cr_drp0_offset 0x1400
  146. #define d_cr_drp0_r_opcode 0x00
  147. /* Denverton d-unit */
  148. struct d_cr_dsch {
  149. u32 ch0en : 1;
  150. u32 ch1en : 1;
  151. u32 ddr4en : 1;
  152. u32 coldwake : 1;
  153. u32 newbypdis : 1;
  154. u32 chan_width : 1;
  155. u32 rsvd6_6 : 1;
  156. u32 ooodis : 1;
  157. u32 rsvd18_8 : 11;
  158. u32 ic : 1;
  159. u32 rsvd31_20 : 12;
  160. };
  161. #define d_cr_dsch_port 0x16
  162. #define d_cr_dsch_offset 0x0
  163. #define d_cr_dsch_r_opcode 0x0
  164. struct d_cr_ecc_ctrl {
  165. u32 eccen : 1;
  166. u32 rsvd31_1 : 31;
  167. };
  168. #define d_cr_ecc_ctrl_offset 0x180
  169. #define d_cr_ecc_ctrl_r_opcode 0x0
  170. struct d_cr_drp {
  171. u32 rken0 : 1;
  172. u32 rken1 : 1;
  173. u32 rken2 : 1;
  174. u32 rken3 : 1;
  175. u32 dimmdwid0 : 2;
  176. u32 dimmdden0 : 2;
  177. u32 dimmdwid1 : 2;
  178. u32 dimmdden1 : 2;
  179. u32 rsvd15_12 : 4;
  180. u32 dimmflip : 1;
  181. u32 rsvd31_17 : 15;
  182. };
  183. #define d_cr_drp_offset 0x158
  184. #define d_cr_drp_r_opcode 0x0
  185. struct d_cr_dmap {
  186. u32 ba0 : 5;
  187. u32 ba1 : 5;
  188. u32 bg0 : 5; /* if ddr3, ba2 = bg0 */
  189. u32 bg1 : 5; /* if ddr3, ba3 = bg1 */
  190. u32 rs0 : 5;
  191. u32 rs1 : 5;
  192. u32 rsvd : 2;
  193. };
  194. #define d_cr_dmap_offset 0x174
  195. #define d_cr_dmap_r_opcode 0x0
  196. struct d_cr_dmap1 {
  197. u32 ca11 : 6;
  198. u32 bxor : 1;
  199. u32 rsvd : 25;
  200. };
  201. #define d_cr_dmap1_offset 0xb4
  202. #define d_cr_dmap1_r_opcode 0x0
  203. struct d_cr_dmap2 {
  204. u32 row0 : 5;
  205. u32 row1 : 5;
  206. u32 row2 : 5;
  207. u32 row3 : 5;
  208. u32 row4 : 5;
  209. u32 row5 : 5;
  210. u32 rsvd : 2;
  211. };
  212. #define d_cr_dmap2_offset 0x148
  213. #define d_cr_dmap2_r_opcode 0x0
  214. struct d_cr_dmap3 {
  215. u32 row6 : 5;
  216. u32 row7 : 5;
  217. u32 row8 : 5;
  218. u32 row9 : 5;
  219. u32 row10 : 5;
  220. u32 row11 : 5;
  221. u32 rsvd : 2;
  222. };
  223. #define d_cr_dmap3_offset 0x14c
  224. #define d_cr_dmap3_r_opcode 0x0
  225. struct d_cr_dmap4 {
  226. u32 row12 : 5;
  227. u32 row13 : 5;
  228. u32 row14 : 5;
  229. u32 row15 : 5;
  230. u32 row16 : 5;
  231. u32 row17 : 5;
  232. u32 rsvd : 2;
  233. };
  234. #define d_cr_dmap4_offset 0x150
  235. #define d_cr_dmap4_r_opcode 0x0
  236. struct d_cr_dmap5 {
  237. u32 ca3 : 4;
  238. u32 ca4 : 4;
  239. u32 ca5 : 4;
  240. u32 ca6 : 4;
  241. u32 ca7 : 4;
  242. u32 ca8 : 4;
  243. u32 ca9 : 4;
  244. u32 rsvd : 4;
  245. };
  246. #define d_cr_dmap5_offset 0x154
  247. #define d_cr_dmap5_r_opcode 0x0
  248. #endif /* _PND2_REGS_H */