i5400_edac.c 40 KB

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  1. /*
  2. * Intel 5400 class Memory Controllers kernel module (Seaburg)
  3. *
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * Copyright (c) 2008 by:
  8. * Ben Woodard <[email protected]>
  9. * Mauro Carvalho Chehab
  10. *
  11. * Red Hat Inc. https://www.redhat.com
  12. *
  13. * Forked and adapted from the i5000_edac driver which was
  14. * written by Douglas Thompson Linux Networx <[email protected]>
  15. *
  16. * This module is based on the following document:
  17. *
  18. * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
  19. * http://developer.intel.com/design/chipsets/datashts/313070.htm
  20. *
  21. * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
  22. * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
  23. * 4 dimm's, each with up to 8GB.
  24. *
  25. */
  26. #include <linux/module.h>
  27. #include <linux/init.h>
  28. #include <linux/pci.h>
  29. #include <linux/pci_ids.h>
  30. #include <linux/slab.h>
  31. #include <linux/edac.h>
  32. #include <linux/mmzone.h>
  33. #include "edac_module.h"
  34. /*
  35. * Alter this version for the I5400 module when modifications are made
  36. */
  37. #define I5400_REVISION " Ver: 1.0.0"
  38. #define EDAC_MOD_STR "i5400_edac"
  39. #define i5400_printk(level, fmt, arg...) \
  40. edac_printk(level, "i5400", fmt, ##arg)
  41. #define i5400_mc_printk(mci, level, fmt, arg...) \
  42. edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)
  43. /* Limits for i5400 */
  44. #define MAX_BRANCHES 2
  45. #define CHANNELS_PER_BRANCH 2
  46. #define DIMMS_PER_CHANNEL 4
  47. #define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH)
  48. /* Device 16,
  49. * Function 0: System Address
  50. * Function 1: Memory Branch Map, Control, Errors Register
  51. * Function 2: FSB Error Registers
  52. *
  53. * All 3 functions of Device 16 (0,1,2) share the SAME DID and
  54. * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2),
  55. * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1
  56. * for device 21 (0,1).
  57. */
  58. /* OFFSETS for Function 0 */
  59. #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
  60. #define MAXCH 0x56 /* Max Channel Number */
  61. #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
  62. /* OFFSETS for Function 1 */
  63. #define TOLM 0x6C
  64. #define REDMEMB 0x7C
  65. #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */
  66. #define MIR0 0x80
  67. #define MIR1 0x84
  68. #define AMIR0 0x8c
  69. #define AMIR1 0x90
  70. /* Fatal error registers */
  71. #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */
  72. #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
  73. #define NERR_FAT_FBD 0x9c
  74. #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */
  75. /* Non-fatal error register */
  76. #define NERR_NF_FBD 0xa4
  77. /* Enable error mask */
  78. #define EMASK_FBD 0xa8
  79. #define ERR0_FBD 0xac
  80. #define ERR1_FBD 0xb0
  81. #define ERR2_FBD 0xb4
  82. #define MCERR_FBD 0xb8
  83. /* No OFFSETS for Device 16 Function 2 */
  84. /*
  85. * Device 21,
  86. * Function 0: Memory Map Branch 0
  87. *
  88. * Device 22,
  89. * Function 0: Memory Map Branch 1
  90. */
  91. /* OFFSETS for Function 0 */
  92. #define AMBPRESENT_0 0x64
  93. #define AMBPRESENT_1 0x66
  94. #define MTR0 0x80
  95. #define MTR1 0x82
  96. #define MTR2 0x84
  97. #define MTR3 0x86
  98. /* OFFSETS for Function 1 */
  99. #define NRECFGLOG 0x74
  100. #define RECFGLOG 0x78
  101. #define NRECMEMA 0xbe
  102. #define NRECMEMB 0xc0
  103. #define NRECFB_DIMMA 0xc4
  104. #define NRECFB_DIMMB 0xc8
  105. #define NRECFB_DIMMC 0xcc
  106. #define NRECFB_DIMMD 0xd0
  107. #define NRECFB_DIMME 0xd4
  108. #define NRECFB_DIMMF 0xd8
  109. #define REDMEMA 0xdC
  110. #define RECMEMA 0xf0
  111. #define RECMEMB 0xf4
  112. #define RECFB_DIMMA 0xf8
  113. #define RECFB_DIMMB 0xec
  114. #define RECFB_DIMMC 0xf0
  115. #define RECFB_DIMMD 0xf4
  116. #define RECFB_DIMME 0xf8
  117. #define RECFB_DIMMF 0xfC
  118. /*
  119. * Error indicator bits and masks
  120. * Error masks are according with Table 5-17 of i5400 datasheet
  121. */
  122. enum error_mask {
  123. EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
  124. EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
  125. EMASK_M3 = 1<<2, /* Reserved */
  126. EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
  127. EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
  128. EMASK_M6 = 1<<5, /* Unsupported on i5400 */
  129. EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
  130. EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
  131. EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
  132. EMASK_M10 = 1<<9, /* Unsupported on i5400 */
  133. EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
  134. EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
  135. EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
  136. EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
  137. EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
  138. EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
  139. EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
  140. EMASK_M18 = 1<<17, /* Unsupported on i5400 */
  141. EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
  142. EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
  143. EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
  144. EMASK_M22 = 1<<21, /* SPD protocol Error */
  145. EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
  146. EMASK_M24 = 1<<23, /* Refresh error */
  147. EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
  148. EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
  149. EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
  150. EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
  151. EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
  152. };
  153. /*
  154. * Names to translate bit error into something useful
  155. */
  156. static const char *error_name[] = {
  157. [0] = "Memory Write error on non-redundant retry",
  158. [1] = "Memory or FB-DIMM configuration CRC read error",
  159. /* Reserved */
  160. [3] = "Uncorrectable Data ECC on Replay",
  161. [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
  162. /* M6 Unsupported on i5400 */
  163. [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
  164. [7] = "Aliased Uncorrectable Patrol Data ECC",
  165. [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
  166. /* M10 Unsupported on i5400 */
  167. [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
  168. [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
  169. [12] = "Memory Write error on first attempt",
  170. [13] = "FB-DIMM Configuration Write error on first attempt",
  171. [14] = "Memory or FB-DIMM configuration CRC read error",
  172. [15] = "Channel Failed-Over Occurred",
  173. [16] = "Correctable Non-Mirrored Demand Data ECC",
  174. /* M18 Unsupported on i5400 */
  175. [18] = "Correctable Resilver- or Spare-Copy Data ECC",
  176. [19] = "Correctable Patrol Data ECC",
  177. [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
  178. [21] = "SPD protocol Error",
  179. [22] = "Non-Redundant Fast Reset Timeout",
  180. [23] = "Refresh error",
  181. [24] = "Memory Write error on redundant retry",
  182. [25] = "Redundant Fast Reset Timeout",
  183. [26] = "Correctable Counter Threshold Exceeded",
  184. [27] = "DIMM-Spare Copy Completed",
  185. [28] = "DIMM-Isolation Completed",
  186. };
  187. /* Fatal errors */
  188. #define ERROR_FAT_MASK (EMASK_M1 | \
  189. EMASK_M2 | \
  190. EMASK_M23)
  191. /* Correctable errors */
  192. #define ERROR_NF_CORRECTABLE (EMASK_M27 | \
  193. EMASK_M20 | \
  194. EMASK_M19 | \
  195. EMASK_M18 | \
  196. EMASK_M17 | \
  197. EMASK_M16)
  198. #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
  199. EMASK_M28)
  200. #define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
  201. #define ERROR_NF_NORTH_CRC (EMASK_M21)
  202. /* Recoverable errors */
  203. #define ERROR_NF_RECOVERABLE (EMASK_M26 | \
  204. EMASK_M25 | \
  205. EMASK_M24 | \
  206. EMASK_M15 | \
  207. EMASK_M14 | \
  208. EMASK_M13 | \
  209. EMASK_M12 | \
  210. EMASK_M11 | \
  211. EMASK_M9 | \
  212. EMASK_M8 | \
  213. EMASK_M7 | \
  214. EMASK_M5)
  215. /* uncorrectable errors */
  216. #define ERROR_NF_UNCORRECTABLE (EMASK_M4)
  217. /* mask to all non-fatal errors */
  218. #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
  219. ERROR_NF_UNCORRECTABLE | \
  220. ERROR_NF_RECOVERABLE | \
  221. ERROR_NF_DIMM_SPARE | \
  222. ERROR_NF_SPD_PROTOCOL | \
  223. ERROR_NF_NORTH_CRC)
  224. /*
  225. * Define error masks for the several registers
  226. */
  227. /* Enable all fatal and non fatal errors */
  228. #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
  229. /* mask for fatal error registers */
  230. #define FERR_FAT_MASK ERROR_FAT_MASK
  231. /* masks for non-fatal error register */
  232. static inline int to_nf_mask(unsigned int mask)
  233. {
  234. return (mask & EMASK_M29) | (mask >> 3);
  235. };
  236. static inline int from_nf_ferr(unsigned int mask)
  237. {
  238. return (mask & EMASK_M29) | /* Bit 28 */
  239. (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
  240. };
  241. #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
  242. #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
  243. #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
  244. #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
  245. #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
  246. #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
  247. #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
  248. /* Defines to extract the vaious fields from the
  249. * MTRx - Memory Technology Registers
  250. */
  251. #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10))
  252. #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9))
  253. #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4)
  254. #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
  255. #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
  256. #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1)
  257. #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
  258. #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
  259. #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
  260. #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
  261. #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
  262. /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
  263. static inline int extract_fbdchan_indx(u32 x)
  264. {
  265. return (x>>28) & 0x3;
  266. }
  267. /* Device name and register DID (Device ID) */
  268. struct i5400_dev_info {
  269. const char *ctl_name; /* name for this device */
  270. u16 fsb_mapping_errors; /* DID for the branchmap,control */
  271. };
  272. /* Table of devices attributes supported by this driver */
  273. static const struct i5400_dev_info i5400_devs[] = {
  274. {
  275. .ctl_name = "I5400",
  276. .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR,
  277. },
  278. };
  279. struct i5400_dimm_info {
  280. int megabytes; /* size, 0 means not present */
  281. };
  282. /* driver private data structure */
  283. struct i5400_pvt {
  284. struct pci_dev *system_address; /* 16.0 */
  285. struct pci_dev *branchmap_werrors; /* 16.1 */
  286. struct pci_dev *fsb_error_regs; /* 16.2 */
  287. struct pci_dev *branch_0; /* 21.0 */
  288. struct pci_dev *branch_1; /* 22.0 */
  289. u16 tolm; /* top of low memory */
  290. union {
  291. u64 ambase; /* AMB BAR */
  292. struct {
  293. u32 ambase_bottom;
  294. u32 ambase_top;
  295. } u __packed;
  296. };
  297. u16 mir0, mir1;
  298. u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
  299. u16 b0_ambpresent0; /* Branch 0, Channel 0 */
  300. u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
  301. u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
  302. u16 b1_ambpresent0; /* Branch 1, Channel 8 */
  303. u16 b1_ambpresent1; /* Branch 1, Channel 1 */
  304. /* DIMM information matrix, allocating architecture maximums */
  305. struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS];
  306. /* Actual values for this controller */
  307. int maxch; /* Max channels */
  308. int maxdimmperch; /* Max DIMMs per channel */
  309. };
  310. /* I5400 MCH error information retrieved from Hardware */
  311. struct i5400_error_info {
  312. /* These registers are always read from the MC */
  313. u32 ferr_fat_fbd; /* First Errors Fatal */
  314. u32 nerr_fat_fbd; /* Next Errors Fatal */
  315. u32 ferr_nf_fbd; /* First Errors Non-Fatal */
  316. u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
  317. /* These registers are input ONLY if there was a Recoverable Error */
  318. u32 redmemb; /* Recoverable Mem Data Error log B */
  319. u16 recmema; /* Recoverable Mem Error log A */
  320. u32 recmemb; /* Recoverable Mem Error log B */
  321. /* These registers are input ONLY if there was a Non-Rec Error */
  322. u16 nrecmema; /* Non-Recoverable Mem log A */
  323. u32 nrecmemb; /* Non-Recoverable Mem log B */
  324. };
  325. /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
  326. 5400 better to use an inline function than a macro in this case */
  327. static inline int nrec_bank(struct i5400_error_info *info)
  328. {
  329. return ((info->nrecmema) >> 12) & 0x7;
  330. }
  331. static inline int nrec_rank(struct i5400_error_info *info)
  332. {
  333. return ((info->nrecmema) >> 8) & 0xf;
  334. }
  335. static inline int nrec_buf_id(struct i5400_error_info *info)
  336. {
  337. return ((info->nrecmema)) & 0xff;
  338. }
  339. static inline int nrec_rdwr(struct i5400_error_info *info)
  340. {
  341. return (info->nrecmemb) >> 31;
  342. }
  343. /* This applies to both NREC and REC string so it can be used with nrec_rdwr
  344. and rec_rdwr */
  345. static inline const char *rdwr_str(int rdwr)
  346. {
  347. return rdwr ? "Write" : "Read";
  348. }
  349. static inline int nrec_cas(struct i5400_error_info *info)
  350. {
  351. return ((info->nrecmemb) >> 16) & 0x1fff;
  352. }
  353. static inline int nrec_ras(struct i5400_error_info *info)
  354. {
  355. return (info->nrecmemb) & 0xffff;
  356. }
  357. static inline int rec_bank(struct i5400_error_info *info)
  358. {
  359. return ((info->recmema) >> 12) & 0x7;
  360. }
  361. static inline int rec_rank(struct i5400_error_info *info)
  362. {
  363. return ((info->recmema) >> 8) & 0xf;
  364. }
  365. static inline int rec_rdwr(struct i5400_error_info *info)
  366. {
  367. return (info->recmemb) >> 31;
  368. }
  369. static inline int rec_cas(struct i5400_error_info *info)
  370. {
  371. return ((info->recmemb) >> 16) & 0x1fff;
  372. }
  373. static inline int rec_ras(struct i5400_error_info *info)
  374. {
  375. return (info->recmemb) & 0xffff;
  376. }
  377. static struct edac_pci_ctl_info *i5400_pci;
  378. /*
  379. * i5400_get_error_info Retrieve the hardware error information from
  380. * the hardware and cache it in the 'info'
  381. * structure
  382. */
  383. static void i5400_get_error_info(struct mem_ctl_info *mci,
  384. struct i5400_error_info *info)
  385. {
  386. struct i5400_pvt *pvt;
  387. u32 value;
  388. pvt = mci->pvt_info;
  389. /* read in the 1st FATAL error register */
  390. pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
  391. /* Mask only the bits that the doc says are valid
  392. */
  393. value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
  394. /* If there is an error, then read in the
  395. NEXT FATAL error register and the Memory Error Log Register A
  396. */
  397. if (value & FERR_FAT_MASK) {
  398. info->ferr_fat_fbd = value;
  399. /* harvest the various error data we need */
  400. pci_read_config_dword(pvt->branchmap_werrors,
  401. NERR_FAT_FBD, &info->nerr_fat_fbd);
  402. pci_read_config_word(pvt->branchmap_werrors,
  403. NRECMEMA, &info->nrecmema);
  404. pci_read_config_dword(pvt->branchmap_werrors,
  405. NRECMEMB, &info->nrecmemb);
  406. /* Clear the error bits, by writing them back */
  407. pci_write_config_dword(pvt->branchmap_werrors,
  408. FERR_FAT_FBD, value);
  409. } else {
  410. info->ferr_fat_fbd = 0;
  411. info->nerr_fat_fbd = 0;
  412. info->nrecmema = 0;
  413. info->nrecmemb = 0;
  414. }
  415. /* read in the 1st NON-FATAL error register */
  416. pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
  417. /* If there is an error, then read in the 1st NON-FATAL error
  418. * register as well */
  419. if (value & FERR_NF_MASK) {
  420. info->ferr_nf_fbd = value;
  421. /* harvest the various error data we need */
  422. pci_read_config_dword(pvt->branchmap_werrors,
  423. NERR_NF_FBD, &info->nerr_nf_fbd);
  424. pci_read_config_word(pvt->branchmap_werrors,
  425. RECMEMA, &info->recmema);
  426. pci_read_config_dword(pvt->branchmap_werrors,
  427. RECMEMB, &info->recmemb);
  428. pci_read_config_dword(pvt->branchmap_werrors,
  429. REDMEMB, &info->redmemb);
  430. /* Clear the error bits, by writing them back */
  431. pci_write_config_dword(pvt->branchmap_werrors,
  432. FERR_NF_FBD, value);
  433. } else {
  434. info->ferr_nf_fbd = 0;
  435. info->nerr_nf_fbd = 0;
  436. info->recmema = 0;
  437. info->recmemb = 0;
  438. info->redmemb = 0;
  439. }
  440. }
  441. /*
  442. * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
  443. * struct i5400_error_info *info,
  444. * int handle_errors);
  445. *
  446. * handle the Intel FATAL and unrecoverable errors, if any
  447. */
  448. static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
  449. struct i5400_error_info *info,
  450. unsigned long allErrors)
  451. {
  452. char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
  453. int branch;
  454. int channel;
  455. int bank;
  456. int buf_id;
  457. int rank;
  458. int rdwr;
  459. int ras, cas;
  460. int errnum;
  461. char *type = NULL;
  462. enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED;
  463. if (!allErrors)
  464. return; /* if no error, return now */
  465. if (allErrors & ERROR_FAT_MASK) {
  466. type = "FATAL";
  467. tp_event = HW_EVENT_ERR_FATAL;
  468. } else if (allErrors & FERR_NF_UNCORRECTABLE)
  469. type = "NON-FATAL uncorrected";
  470. else
  471. type = "NON-FATAL recoverable";
  472. /* ONLY ONE of the possible error bits will be set, as per the docs */
  473. branch = extract_fbdchan_indx(info->ferr_fat_fbd);
  474. channel = branch;
  475. /* Use the NON-Recoverable macros to extract data */
  476. bank = nrec_bank(info);
  477. rank = nrec_rank(info);
  478. buf_id = nrec_buf_id(info);
  479. rdwr = nrec_rdwr(info);
  480. ras = nrec_ras(info);
  481. cas = nrec_cas(info);
  482. edac_dbg(0, "\t\t%s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
  483. type, rank, channel, channel + 1, branch >> 1, bank,
  484. buf_id, rdwr_str(rdwr), ras, cas);
  485. /* Only 1 bit will be on */
  486. errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
  487. /* Form out message */
  488. snprintf(msg, sizeof(msg),
  489. "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)",
  490. bank, buf_id, ras, cas, allErrors, error_name[errnum]);
  491. edac_mc_handle_error(tp_event, mci, 1, 0, 0, 0,
  492. branch >> 1, -1, rank,
  493. rdwr ? "Write error" : "Read error",
  494. msg);
  495. }
  496. /*
  497. * i5400_process_fatal_error_info(struct mem_ctl_info *mci,
  498. * struct i5400_error_info *info,
  499. * int handle_errors);
  500. *
  501. * handle the Intel NON-FATAL errors, if any
  502. */
  503. static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
  504. struct i5400_error_info *info)
  505. {
  506. char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
  507. unsigned long allErrors;
  508. int branch;
  509. int channel;
  510. int bank;
  511. int rank;
  512. int rdwr;
  513. int ras, cas;
  514. int errnum;
  515. /* mask off the Error bits that are possible */
  516. allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
  517. if (!allErrors)
  518. return; /* if no error, return now */
  519. /* ONLY ONE of the possible error bits will be set, as per the docs */
  520. if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
  521. i5400_proccess_non_recoverable_info(mci, info, allErrors);
  522. return;
  523. }
  524. /* Correctable errors */
  525. if (allErrors & ERROR_NF_CORRECTABLE) {
  526. edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors);
  527. branch = extract_fbdchan_indx(info->ferr_nf_fbd);
  528. channel = 0;
  529. if (REC_ECC_LOCATOR_ODD(info->redmemb))
  530. channel = 1;
  531. /* Convert channel to be based from zero, instead of
  532. * from branch base of 0 */
  533. channel += branch;
  534. bank = rec_bank(info);
  535. rank = rec_rank(info);
  536. rdwr = rec_rdwr(info);
  537. ras = rec_ras(info);
  538. cas = rec_cas(info);
  539. /* Only 1 bit will be on */
  540. errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
  541. edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
  542. rank, channel, branch >> 1, bank,
  543. rdwr_str(rdwr), ras, cas);
  544. /* Form out message */
  545. snprintf(msg, sizeof(msg),
  546. "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
  547. "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
  548. branch >> 1, bank, rdwr_str(rdwr), ras, cas,
  549. allErrors, error_name[errnum]);
  550. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
  551. branch >> 1, channel % 2, rank,
  552. rdwr ? "Write error" : "Read error",
  553. msg);
  554. return;
  555. }
  556. /* Miscellaneous errors */
  557. errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
  558. branch = extract_fbdchan_indx(info->ferr_nf_fbd);
  559. i5400_mc_printk(mci, KERN_EMERG,
  560. "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
  561. branch >> 1, allErrors, error_name[errnum]);
  562. }
  563. /*
  564. * i5400_process_error_info Process the error info that is
  565. * in the 'info' structure, previously retrieved from hardware
  566. */
  567. static void i5400_process_error_info(struct mem_ctl_info *mci,
  568. struct i5400_error_info *info)
  569. { u32 allErrors;
  570. /* First handle any fatal errors that occurred */
  571. allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
  572. i5400_proccess_non_recoverable_info(mci, info, allErrors);
  573. /* now handle any non-fatal errors that occurred */
  574. i5400_process_nonfatal_error_info(mci, info);
  575. }
  576. /*
  577. * i5400_clear_error Retrieve any error from the hardware
  578. * but do NOT process that error.
  579. * Used for 'clearing' out of previous errors
  580. * Called by the Core module.
  581. */
  582. static void i5400_clear_error(struct mem_ctl_info *mci)
  583. {
  584. struct i5400_error_info info;
  585. i5400_get_error_info(mci, &info);
  586. }
  587. /*
  588. * i5400_check_error Retrieve and process errors reported by the
  589. * hardware. Called by the Core module.
  590. */
  591. static void i5400_check_error(struct mem_ctl_info *mci)
  592. {
  593. struct i5400_error_info info;
  594. i5400_get_error_info(mci, &info);
  595. i5400_process_error_info(mci, &info);
  596. }
  597. /*
  598. * i5400_put_devices 'put' all the devices that we have
  599. * reserved via 'get'
  600. */
  601. static void i5400_put_devices(struct mem_ctl_info *mci)
  602. {
  603. struct i5400_pvt *pvt;
  604. pvt = mci->pvt_info;
  605. /* Decrement usage count for devices */
  606. pci_dev_put(pvt->branch_1);
  607. pci_dev_put(pvt->branch_0);
  608. pci_dev_put(pvt->fsb_error_regs);
  609. pci_dev_put(pvt->branchmap_werrors);
  610. }
  611. /*
  612. * i5400_get_devices Find and perform 'get' operation on the MCH's
  613. * device/functions we want to reference for this driver
  614. *
  615. * Need to 'get' device 16 func 1 and func 2
  616. */
  617. static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
  618. {
  619. struct i5400_pvt *pvt;
  620. struct pci_dev *pdev;
  621. pvt = mci->pvt_info;
  622. pvt->branchmap_werrors = NULL;
  623. pvt->fsb_error_regs = NULL;
  624. pvt->branch_0 = NULL;
  625. pvt->branch_1 = NULL;
  626. /* Attempt to 'get' the MCH register we want */
  627. pdev = NULL;
  628. while (1) {
  629. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  630. PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
  631. if (!pdev) {
  632. /* End of list, leave */
  633. i5400_printk(KERN_ERR,
  634. "'system address,Process Bus' "
  635. "device not found:"
  636. "vendor 0x%x device 0x%x ERR func 1 "
  637. "(broken BIOS?)\n",
  638. PCI_VENDOR_ID_INTEL,
  639. PCI_DEVICE_ID_INTEL_5400_ERR);
  640. return -ENODEV;
  641. }
  642. /* Store device 16 func 1 */
  643. if (PCI_FUNC(pdev->devfn) == 1)
  644. break;
  645. }
  646. pvt->branchmap_werrors = pdev;
  647. pdev = NULL;
  648. while (1) {
  649. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  650. PCI_DEVICE_ID_INTEL_5400_ERR, pdev);
  651. if (!pdev) {
  652. /* End of list, leave */
  653. i5400_printk(KERN_ERR,
  654. "'system address,Process Bus' "
  655. "device not found:"
  656. "vendor 0x%x device 0x%x ERR func 2 "
  657. "(broken BIOS?)\n",
  658. PCI_VENDOR_ID_INTEL,
  659. PCI_DEVICE_ID_INTEL_5400_ERR);
  660. pci_dev_put(pvt->branchmap_werrors);
  661. return -ENODEV;
  662. }
  663. /* Store device 16 func 2 */
  664. if (PCI_FUNC(pdev->devfn) == 2)
  665. break;
  666. }
  667. pvt->fsb_error_regs = pdev;
  668. edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
  669. pci_name(pvt->system_address),
  670. pvt->system_address->vendor, pvt->system_address->device);
  671. edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
  672. pci_name(pvt->branchmap_werrors),
  673. pvt->branchmap_werrors->vendor,
  674. pvt->branchmap_werrors->device);
  675. edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
  676. pci_name(pvt->fsb_error_regs),
  677. pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
  678. pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
  679. PCI_DEVICE_ID_INTEL_5400_FBD0, NULL);
  680. if (!pvt->branch_0) {
  681. i5400_printk(KERN_ERR,
  682. "MC: 'BRANCH 0' device not found:"
  683. "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
  684. PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0);
  685. pci_dev_put(pvt->fsb_error_regs);
  686. pci_dev_put(pvt->branchmap_werrors);
  687. return -ENODEV;
  688. }
  689. /* If this device claims to have more than 2 channels then
  690. * fetch Branch 1's information
  691. */
  692. if (pvt->maxch < CHANNELS_PER_BRANCH)
  693. return 0;
  694. pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
  695. PCI_DEVICE_ID_INTEL_5400_FBD1, NULL);
  696. if (!pvt->branch_1) {
  697. i5400_printk(KERN_ERR,
  698. "MC: 'BRANCH 1' device not found:"
  699. "vendor 0x%x device 0x%x Func 0 "
  700. "(broken BIOS?)\n",
  701. PCI_VENDOR_ID_INTEL,
  702. PCI_DEVICE_ID_INTEL_5400_FBD1);
  703. pci_dev_put(pvt->branch_0);
  704. pci_dev_put(pvt->fsb_error_regs);
  705. pci_dev_put(pvt->branchmap_werrors);
  706. return -ENODEV;
  707. }
  708. return 0;
  709. }
  710. /*
  711. * determine_amb_present
  712. *
  713. * the information is contained in DIMMS_PER_CHANNEL different
  714. * registers determining which of the DIMMS_PER_CHANNEL requires
  715. * knowing which channel is in question
  716. *
  717. * 2 branches, each with 2 channels
  718. * b0_ambpresent0 for channel '0'
  719. * b0_ambpresent1 for channel '1'
  720. * b1_ambpresent0 for channel '2'
  721. * b1_ambpresent1 for channel '3'
  722. */
  723. static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
  724. {
  725. int amb_present;
  726. if (channel < CHANNELS_PER_BRANCH) {
  727. if (channel & 0x1)
  728. amb_present = pvt->b0_ambpresent1;
  729. else
  730. amb_present = pvt->b0_ambpresent0;
  731. } else {
  732. if (channel & 0x1)
  733. amb_present = pvt->b1_ambpresent1;
  734. else
  735. amb_present = pvt->b1_ambpresent0;
  736. }
  737. return amb_present;
  738. }
  739. /*
  740. * determine_mtr(pvt, dimm, channel)
  741. *
  742. * return the proper MTR register as determine by the dimm and desired channel
  743. */
  744. static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
  745. {
  746. int mtr;
  747. int n;
  748. /* There is one MTR for each slot pair of FB-DIMMs,
  749. Each slot pair may be at branch 0 or branch 1.
  750. */
  751. n = dimm;
  752. if (n >= DIMMS_PER_CHANNEL) {
  753. edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n",
  754. dimm);
  755. return 0;
  756. }
  757. if (channel < CHANNELS_PER_BRANCH)
  758. mtr = pvt->b0_mtr[n];
  759. else
  760. mtr = pvt->b1_mtr[n];
  761. return mtr;
  762. }
  763. /*
  764. */
  765. static void decode_mtr(int slot_row, u16 mtr)
  766. {
  767. int ans;
  768. ans = MTR_DIMMS_PRESENT(mtr);
  769. edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
  770. slot_row, mtr, ans ? "" : "NOT ");
  771. if (!ans)
  772. return;
  773. edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
  774. edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
  775. MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
  776. edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
  777. edac_dbg(2, "\t\tNUMRANK: %s\n",
  778. MTR_DIMM_RANK(mtr) ? "double" : "single");
  779. edac_dbg(2, "\t\tNUMROW: %s\n",
  780. MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
  781. MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
  782. MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
  783. "65,536 - 16 rows");
  784. edac_dbg(2, "\t\tNUMCOL: %s\n",
  785. MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
  786. MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
  787. MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
  788. "reserved");
  789. }
  790. static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
  791. struct i5400_dimm_info *dinfo)
  792. {
  793. int mtr;
  794. int amb_present_reg;
  795. int addrBits;
  796. mtr = determine_mtr(pvt, dimm, channel);
  797. if (MTR_DIMMS_PRESENT(mtr)) {
  798. amb_present_reg = determine_amb_present_reg(pvt, channel);
  799. /* Determine if there is a DIMM present in this DIMM slot */
  800. if (amb_present_reg & (1 << dimm)) {
  801. /* Start with the number of bits for a Bank
  802. * on the DRAM */
  803. addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
  804. /* Add thenumber of ROW bits */
  805. addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
  806. /* add the number of COLUMN bits */
  807. addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
  808. /* add the number of RANK bits */
  809. addrBits += MTR_DIMM_RANK(mtr);
  810. addrBits += 6; /* add 64 bits per DIMM */
  811. addrBits -= 20; /* divide by 2^^20 */
  812. addrBits -= 3; /* 8 bits per bytes */
  813. dinfo->megabytes = 1 << addrBits;
  814. }
  815. }
  816. }
  817. /*
  818. * calculate_dimm_size
  819. *
  820. * also will output a DIMM matrix map, if debug is enabled, for viewing
  821. * how the DIMMs are populated
  822. */
  823. static void calculate_dimm_size(struct i5400_pvt *pvt)
  824. {
  825. struct i5400_dimm_info *dinfo;
  826. int dimm, max_dimms;
  827. char *p, *mem_buffer;
  828. int space, n;
  829. int channel, branch;
  830. /* ================= Generate some debug output ================= */
  831. space = PAGE_SIZE;
  832. mem_buffer = p = kmalloc(space, GFP_KERNEL);
  833. if (p == NULL) {
  834. i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
  835. __FILE__, __func__);
  836. return;
  837. }
  838. /* Scan all the actual DIMMS
  839. * and calculate the information for each DIMM
  840. * Start with the highest dimm first, to display it first
  841. * and work toward the 0th dimm
  842. */
  843. max_dimms = pvt->maxdimmperch;
  844. for (dimm = max_dimms - 1; dimm >= 0; dimm--) {
  845. /* on an odd dimm, first output a 'boundary' marker,
  846. * then reset the message buffer */
  847. if (dimm & 0x1) {
  848. n = snprintf(p, space, "---------------------------"
  849. "-------------------------------");
  850. p += n;
  851. space -= n;
  852. edac_dbg(2, "%s\n", mem_buffer);
  853. p = mem_buffer;
  854. space = PAGE_SIZE;
  855. }
  856. n = snprintf(p, space, "dimm %2d ", dimm);
  857. p += n;
  858. space -= n;
  859. for (channel = 0; channel < pvt->maxch; channel++) {
  860. dinfo = &pvt->dimm_info[dimm][channel];
  861. handle_channel(pvt, dimm, channel, dinfo);
  862. n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
  863. p += n;
  864. space -= n;
  865. }
  866. edac_dbg(2, "%s\n", mem_buffer);
  867. p = mem_buffer;
  868. space = PAGE_SIZE;
  869. }
  870. /* Output the last bottom 'boundary' marker */
  871. n = snprintf(p, space, "---------------------------"
  872. "-------------------------------");
  873. p += n;
  874. space -= n;
  875. edac_dbg(2, "%s\n", mem_buffer);
  876. p = mem_buffer;
  877. space = PAGE_SIZE;
  878. /* now output the 'channel' labels */
  879. n = snprintf(p, space, " ");
  880. p += n;
  881. space -= n;
  882. for (channel = 0; channel < pvt->maxch; channel++) {
  883. n = snprintf(p, space, "channel %d | ", channel);
  884. p += n;
  885. space -= n;
  886. }
  887. space -= n;
  888. edac_dbg(2, "%s\n", mem_buffer);
  889. p = mem_buffer;
  890. space = PAGE_SIZE;
  891. n = snprintf(p, space, " ");
  892. p += n;
  893. for (branch = 0; branch < MAX_BRANCHES; branch++) {
  894. n = snprintf(p, space, " branch %d | ", branch);
  895. p += n;
  896. space -= n;
  897. }
  898. /* output the last message and free buffer */
  899. edac_dbg(2, "%s\n", mem_buffer);
  900. kfree(mem_buffer);
  901. }
  902. /*
  903. * i5400_get_mc_regs read in the necessary registers and
  904. * cache locally
  905. *
  906. * Fills in the private data members
  907. */
  908. static void i5400_get_mc_regs(struct mem_ctl_info *mci)
  909. {
  910. struct i5400_pvt *pvt;
  911. u32 actual_tolm;
  912. u16 limit;
  913. int slot_row;
  914. int way0, way1;
  915. pvt = mci->pvt_info;
  916. pci_read_config_dword(pvt->system_address, AMBASE,
  917. &pvt->u.ambase_bottom);
  918. pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
  919. &pvt->u.ambase_top);
  920. edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
  921. (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
  922. /* Get the Branch Map regs */
  923. pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
  924. pvt->tolm >>= 12;
  925. edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n",
  926. pvt->tolm, pvt->tolm);
  927. actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
  928. edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
  929. actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
  930. pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
  931. pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
  932. /* Get the MIR[0-1] regs */
  933. limit = (pvt->mir0 >> 4) & 0x0fff;
  934. way0 = pvt->mir0 & 0x1;
  935. way1 = pvt->mir0 & 0x2;
  936. edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
  937. limit, way1, way0);
  938. limit = (pvt->mir1 >> 4) & 0xfff;
  939. way0 = pvt->mir1 & 0x1;
  940. way1 = pvt->mir1 & 0x2;
  941. edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
  942. limit, way1, way0);
  943. /* Get the set of MTR[0-3] regs by each branch */
  944. for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {
  945. int where = MTR0 + (slot_row * sizeof(u16));
  946. /* Branch 0 set of MTR registers */
  947. pci_read_config_word(pvt->branch_0, where,
  948. &pvt->b0_mtr[slot_row]);
  949. edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
  950. slot_row, where, pvt->b0_mtr[slot_row]);
  951. if (pvt->maxch < CHANNELS_PER_BRANCH) {
  952. pvt->b1_mtr[slot_row] = 0;
  953. continue;
  954. }
  955. /* Branch 1 set of MTR registers */
  956. pci_read_config_word(pvt->branch_1, where,
  957. &pvt->b1_mtr[slot_row]);
  958. edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
  959. slot_row, where, pvt->b1_mtr[slot_row]);
  960. }
  961. /* Read and dump branch 0's MTRs */
  962. edac_dbg(2, "Memory Technology Registers:\n");
  963. edac_dbg(2, " Branch 0:\n");
  964. for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
  965. decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
  966. pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
  967. &pvt->b0_ambpresent0);
  968. edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
  969. pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
  970. &pvt->b0_ambpresent1);
  971. edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
  972. /* Only if we have 2 branchs (4 channels) */
  973. if (pvt->maxch < CHANNELS_PER_BRANCH) {
  974. pvt->b1_ambpresent0 = 0;
  975. pvt->b1_ambpresent1 = 0;
  976. } else {
  977. /* Read and dump branch 1's MTRs */
  978. edac_dbg(2, " Branch 1:\n");
  979. for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
  980. decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
  981. pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
  982. &pvt->b1_ambpresent0);
  983. edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
  984. pvt->b1_ambpresent0);
  985. pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
  986. &pvt->b1_ambpresent1);
  987. edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
  988. pvt->b1_ambpresent1);
  989. }
  990. /* Go and determine the size of each DIMM and place in an
  991. * orderly matrix */
  992. calculate_dimm_size(pvt);
  993. }
  994. /*
  995. * i5400_init_dimms Initialize the 'dimms' table within
  996. * the mci control structure with the
  997. * addressing of memory.
  998. *
  999. * return:
  1000. * 0 success
  1001. * 1 no actual memory found on this MC
  1002. */
  1003. static int i5400_init_dimms(struct mem_ctl_info *mci)
  1004. {
  1005. struct i5400_pvt *pvt;
  1006. struct dimm_info *dimm;
  1007. int ndimms;
  1008. int mtr;
  1009. int size_mb;
  1010. int channel, slot;
  1011. pvt = mci->pvt_info;
  1012. ndimms = 0;
  1013. /*
  1014. * FIXME: remove pvt->dimm_info[slot][channel] and use the 3
  1015. * layers here.
  1016. */
  1017. for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size;
  1018. channel++) {
  1019. for (slot = 0; slot < mci->layers[2].size; slot++) {
  1020. mtr = determine_mtr(pvt, slot, channel);
  1021. /* if no DIMMS on this slot, continue */
  1022. if (!MTR_DIMMS_PRESENT(mtr))
  1023. continue;
  1024. dimm = edac_get_dimm(mci, channel / 2, channel % 2, slot);
  1025. size_mb = pvt->dimm_info[slot][channel].megabytes;
  1026. edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n",
  1027. channel / 2, channel % 2, slot,
  1028. size_mb / 1000, size_mb % 1000);
  1029. dimm->nr_pages = size_mb << 8;
  1030. dimm->grain = 8;
  1031. dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ?
  1032. DEV_X8 : DEV_X4;
  1033. dimm->mtype = MEM_FB_DDR2;
  1034. /*
  1035. * The eccc mechanism is SDDC (aka SECC), with
  1036. * is similar to Chipkill.
  1037. */
  1038. dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ?
  1039. EDAC_S8ECD8ED : EDAC_S4ECD4ED;
  1040. ndimms++;
  1041. }
  1042. }
  1043. /*
  1044. * When just one memory is provided, it should be at location (0,0,0).
  1045. * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+.
  1046. */
  1047. if (ndimms == 1)
  1048. mci->dimms[0]->edac_mode = EDAC_SECDED;
  1049. return (ndimms == 0);
  1050. }
  1051. /*
  1052. * i5400_enable_error_reporting
  1053. * Turn on the memory reporting features of the hardware
  1054. */
  1055. static void i5400_enable_error_reporting(struct mem_ctl_info *mci)
  1056. {
  1057. struct i5400_pvt *pvt;
  1058. u32 fbd_error_mask;
  1059. pvt = mci->pvt_info;
  1060. /* Read the FBD Error Mask Register */
  1061. pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
  1062. &fbd_error_mask);
  1063. /* Enable with a '0' */
  1064. fbd_error_mask &= ~(ENABLE_EMASK_ALL);
  1065. pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
  1066. fbd_error_mask);
  1067. }
  1068. /*
  1069. * i5400_probe1 Probe for ONE instance of device to see if it is
  1070. * present.
  1071. * return:
  1072. * 0 for FOUND a device
  1073. * < 0 for error code
  1074. */
  1075. static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
  1076. {
  1077. struct mem_ctl_info *mci;
  1078. struct i5400_pvt *pvt;
  1079. struct edac_mc_layer layers[3];
  1080. if (dev_idx >= ARRAY_SIZE(i5400_devs))
  1081. return -EINVAL;
  1082. edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
  1083. pdev->bus->number,
  1084. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
  1085. /* We only are looking for func 0 of the set */
  1086. if (PCI_FUNC(pdev->devfn) != 0)
  1087. return -ENODEV;
  1088. /*
  1089. * allocate a new MC control structure
  1090. *
  1091. * This drivers uses the DIMM slot as "csrow" and the rest as "channel".
  1092. */
  1093. layers[0].type = EDAC_MC_LAYER_BRANCH;
  1094. layers[0].size = MAX_BRANCHES;
  1095. layers[0].is_virt_csrow = false;
  1096. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  1097. layers[1].size = CHANNELS_PER_BRANCH;
  1098. layers[1].is_virt_csrow = false;
  1099. layers[2].type = EDAC_MC_LAYER_SLOT;
  1100. layers[2].size = DIMMS_PER_CHANNEL;
  1101. layers[2].is_virt_csrow = true;
  1102. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
  1103. if (mci == NULL)
  1104. return -ENOMEM;
  1105. edac_dbg(0, "MC: mci = %p\n", mci);
  1106. mci->pdev = &pdev->dev; /* record ptr to the generic device */
  1107. pvt = mci->pvt_info;
  1108. pvt->system_address = pdev; /* Record this device in our private */
  1109. pvt->maxch = MAX_CHANNELS;
  1110. pvt->maxdimmperch = DIMMS_PER_CHANNEL;
  1111. /* 'get' the pci devices we want to reserve for our use */
  1112. if (i5400_get_devices(mci, dev_idx))
  1113. goto fail0;
  1114. /* Time to get serious */
  1115. i5400_get_mc_regs(mci); /* retrieve the hardware registers */
  1116. mci->mc_idx = 0;
  1117. mci->mtype_cap = MEM_FLAG_FB_DDR2;
  1118. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  1119. mci->edac_cap = EDAC_FLAG_NONE;
  1120. mci->mod_name = "i5400_edac.c";
  1121. mci->ctl_name = i5400_devs[dev_idx].ctl_name;
  1122. mci->dev_name = pci_name(pdev);
  1123. mci->ctl_page_to_phys = NULL;
  1124. /* Set the function pointer to an actual operation function */
  1125. mci->edac_check = i5400_check_error;
  1126. /* initialize the MC control structure 'dimms' table
  1127. * with the mapping and control information */
  1128. if (i5400_init_dimms(mci)) {
  1129. edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n");
  1130. mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */
  1131. } else {
  1132. edac_dbg(1, "MC: Enable error reporting now\n");
  1133. i5400_enable_error_reporting(mci);
  1134. }
  1135. /* add this new MC control structure to EDAC's list of MCs */
  1136. if (edac_mc_add_mc(mci)) {
  1137. edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
  1138. /* FIXME: perhaps some code should go here that disables error
  1139. * reporting if we just enabled it
  1140. */
  1141. goto fail1;
  1142. }
  1143. i5400_clear_error(mci);
  1144. /* allocating generic PCI control info */
  1145. i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  1146. if (!i5400_pci) {
  1147. printk(KERN_WARNING
  1148. "%s(): Unable to create PCI control\n",
  1149. __func__);
  1150. printk(KERN_WARNING
  1151. "%s(): PCI error report via EDAC not setup\n",
  1152. __func__);
  1153. }
  1154. return 0;
  1155. /* Error exit unwinding stack */
  1156. fail1:
  1157. i5400_put_devices(mci);
  1158. fail0:
  1159. edac_mc_free(mci);
  1160. return -ENODEV;
  1161. }
  1162. /*
  1163. * i5400_init_one constructor for one instance of device
  1164. *
  1165. * returns:
  1166. * negative on error
  1167. * count (>= 0)
  1168. */
  1169. static int i5400_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1170. {
  1171. int rc;
  1172. edac_dbg(0, "MC:\n");
  1173. /* wake up device */
  1174. rc = pci_enable_device(pdev);
  1175. if (rc)
  1176. return rc;
  1177. /* now probe and enable the device */
  1178. return i5400_probe1(pdev, id->driver_data);
  1179. }
  1180. /*
  1181. * i5400_remove_one destructor for one instance of device
  1182. *
  1183. */
  1184. static void i5400_remove_one(struct pci_dev *pdev)
  1185. {
  1186. struct mem_ctl_info *mci;
  1187. edac_dbg(0, "\n");
  1188. if (i5400_pci)
  1189. edac_pci_release_generic_ctl(i5400_pci);
  1190. mci = edac_mc_del_mc(&pdev->dev);
  1191. if (!mci)
  1192. return;
  1193. /* retrieve references to resources, and free those resources */
  1194. i5400_put_devices(mci);
  1195. pci_disable_device(pdev);
  1196. edac_mc_free(mci);
  1197. }
  1198. /*
  1199. * pci_device_id table for which devices we are looking for
  1200. *
  1201. * The "E500P" device is the first device supported.
  1202. */
  1203. static const struct pci_device_id i5400_pci_tbl[] = {
  1204. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)},
  1205. {0,} /* 0 terminated list. */
  1206. };
  1207. MODULE_DEVICE_TABLE(pci, i5400_pci_tbl);
  1208. /*
  1209. * i5400_driver pci_driver structure for this module
  1210. *
  1211. */
  1212. static struct pci_driver i5400_driver = {
  1213. .name = "i5400_edac",
  1214. .probe = i5400_init_one,
  1215. .remove = i5400_remove_one,
  1216. .id_table = i5400_pci_tbl,
  1217. };
  1218. /*
  1219. * i5400_init Module entry function
  1220. * Try to initialize this module for its devices
  1221. */
  1222. static int __init i5400_init(void)
  1223. {
  1224. int pci_rc;
  1225. edac_dbg(2, "MC:\n");
  1226. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  1227. opstate_init();
  1228. pci_rc = pci_register_driver(&i5400_driver);
  1229. return (pci_rc < 0) ? pci_rc : 0;
  1230. }
  1231. /*
  1232. * i5400_exit() Module exit function
  1233. * Unregister the driver
  1234. */
  1235. static void __exit i5400_exit(void)
  1236. {
  1237. edac_dbg(2, "MC:\n");
  1238. pci_unregister_driver(&i5400_driver);
  1239. }
  1240. module_init(i5400_init);
  1241. module_exit(i5400_exit);
  1242. MODULE_LICENSE("GPL");
  1243. MODULE_AUTHOR("Ben Woodard <[email protected]>");
  1244. MODULE_AUTHOR("Mauro Carvalho Chehab");
  1245. MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
  1246. MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - "
  1247. I5400_REVISION);
  1248. module_param(edac_op_state, int, 0444);
  1249. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");