ghes_edac.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GHES/EDAC Linux driver
  4. *
  5. * Copyright (c) 2013 by Mauro Carvalho Chehab
  6. *
  7. * Red Hat Inc. https://www.redhat.com
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <acpi/ghes.h>
  11. #include <linux/edac.h>
  12. #include <linux/dmi.h>
  13. #include "edac_module.h"
  14. #include <ras/ras_event.h>
  15. #define OTHER_DETAIL_LEN 400
  16. struct ghes_pvt {
  17. struct mem_ctl_info *mci;
  18. /* Buffers for the error handling routine */
  19. char other_detail[OTHER_DETAIL_LEN];
  20. char msg[80];
  21. };
  22. static refcount_t ghes_refcount = REFCOUNT_INIT(0);
  23. /*
  24. * Access to ghes_pvt must be protected by ghes_lock. The spinlock
  25. * also provides the necessary (implicit) memory barrier for the SMP
  26. * case to make the pointer visible on another CPU.
  27. */
  28. static struct ghes_pvt *ghes_pvt;
  29. /*
  30. * This driver's representation of the system hardware, as collected
  31. * from DMI.
  32. */
  33. static struct ghes_hw_desc {
  34. int num_dimms;
  35. struct dimm_info *dimms;
  36. } ghes_hw;
  37. /* GHES registration mutex */
  38. static DEFINE_MUTEX(ghes_reg_mutex);
  39. /*
  40. * Sync with other, potentially concurrent callers of
  41. * ghes_edac_report_mem_error(). We don't know what the
  42. * "inventive" firmware would do.
  43. */
  44. static DEFINE_SPINLOCK(ghes_lock);
  45. /* "ghes_edac.force_load=1" skips the platform check */
  46. static bool __read_mostly force_load;
  47. module_param(force_load, bool, 0);
  48. static bool system_scanned;
  49. /* Memory Device - Type 17 of SMBIOS spec */
  50. struct memdev_dmi_entry {
  51. u8 type;
  52. u8 length;
  53. u16 handle;
  54. u16 phys_mem_array_handle;
  55. u16 mem_err_info_handle;
  56. u16 total_width;
  57. u16 data_width;
  58. u16 size;
  59. u8 form_factor;
  60. u8 device_set;
  61. u8 device_locator;
  62. u8 bank_locator;
  63. u8 memory_type;
  64. u16 type_detail;
  65. u16 speed;
  66. u8 manufacturer;
  67. u8 serial_number;
  68. u8 asset_tag;
  69. u8 part_number;
  70. u8 attributes;
  71. u32 extended_size;
  72. u16 conf_mem_clk_speed;
  73. } __attribute__((__packed__));
  74. static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
  75. {
  76. struct dimm_info *dimm;
  77. mci_for_each_dimm(mci, dimm) {
  78. if (dimm->smbios_handle == handle)
  79. return dimm;
  80. }
  81. return NULL;
  82. }
  83. static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
  84. {
  85. const char *bank = NULL, *device = NULL;
  86. dmi_memdev_name(handle, &bank, &device);
  87. /*
  88. * Set to a NULL string when both bank and device are zero. In this case,
  89. * the label assigned by default will be preserved.
  90. */
  91. snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
  92. (bank && *bank) ? bank : "",
  93. (bank && *bank && device && *device) ? " " : "",
  94. (device && *device) ? device : "");
  95. }
  96. static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
  97. {
  98. u16 rdr_mask = BIT(7) | BIT(13);
  99. if (entry->size == 0xffff) {
  100. pr_info("Can't get DIMM%i size\n", dimm->idx);
  101. dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
  102. } else if (entry->size == 0x7fff) {
  103. dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
  104. } else {
  105. if (entry->size & BIT(15))
  106. dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
  107. else
  108. dimm->nr_pages = MiB_TO_PAGES(entry->size);
  109. }
  110. switch (entry->memory_type) {
  111. case 0x12:
  112. if (entry->type_detail & BIT(13))
  113. dimm->mtype = MEM_RDDR;
  114. else
  115. dimm->mtype = MEM_DDR;
  116. break;
  117. case 0x13:
  118. if (entry->type_detail & BIT(13))
  119. dimm->mtype = MEM_RDDR2;
  120. else
  121. dimm->mtype = MEM_DDR2;
  122. break;
  123. case 0x14:
  124. dimm->mtype = MEM_FB_DDR2;
  125. break;
  126. case 0x18:
  127. if (entry->type_detail & BIT(12))
  128. dimm->mtype = MEM_NVDIMM;
  129. else if (entry->type_detail & BIT(13))
  130. dimm->mtype = MEM_RDDR3;
  131. else
  132. dimm->mtype = MEM_DDR3;
  133. break;
  134. case 0x1a:
  135. if (entry->type_detail & BIT(12))
  136. dimm->mtype = MEM_NVDIMM;
  137. else if (entry->type_detail & BIT(13))
  138. dimm->mtype = MEM_RDDR4;
  139. else
  140. dimm->mtype = MEM_DDR4;
  141. break;
  142. default:
  143. if (entry->type_detail & BIT(6))
  144. dimm->mtype = MEM_RMBS;
  145. else if ((entry->type_detail & rdr_mask) == rdr_mask)
  146. dimm->mtype = MEM_RDR;
  147. else if (entry->type_detail & BIT(7))
  148. dimm->mtype = MEM_SDR;
  149. else if (entry->type_detail & BIT(9))
  150. dimm->mtype = MEM_EDO;
  151. else
  152. dimm->mtype = MEM_UNKNOWN;
  153. }
  154. /*
  155. * Actually, we can only detect if the memory has bits for
  156. * checksum or not
  157. */
  158. if (entry->total_width == entry->data_width)
  159. dimm->edac_mode = EDAC_NONE;
  160. else
  161. dimm->edac_mode = EDAC_SECDED;
  162. dimm->dtype = DEV_UNKNOWN;
  163. dimm->grain = 128; /* Likely, worse case */
  164. dimm_setup_label(dimm, entry->handle);
  165. if (dimm->nr_pages) {
  166. edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
  167. dimm->idx, edac_mem_types[dimm->mtype],
  168. PAGES_TO_MiB(dimm->nr_pages),
  169. (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
  170. edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
  171. entry->memory_type, entry->type_detail,
  172. entry->total_width, entry->data_width);
  173. }
  174. dimm->smbios_handle = entry->handle;
  175. }
  176. static void enumerate_dimms(const struct dmi_header *dh, void *arg)
  177. {
  178. struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
  179. struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
  180. struct dimm_info *d;
  181. if (dh->type != DMI_ENTRY_MEM_DEVICE)
  182. return;
  183. /* Enlarge the array with additional 16 */
  184. if (!hw->num_dimms || !(hw->num_dimms % 16)) {
  185. struct dimm_info *new;
  186. new = krealloc_array(hw->dimms, hw->num_dimms + 16,
  187. sizeof(struct dimm_info), GFP_KERNEL);
  188. if (!new) {
  189. WARN_ON_ONCE(1);
  190. return;
  191. }
  192. hw->dimms = new;
  193. }
  194. d = &hw->dimms[hw->num_dimms];
  195. d->idx = hw->num_dimms;
  196. assign_dmi_dimm_info(d, entry);
  197. hw->num_dimms++;
  198. }
  199. static void ghes_scan_system(void)
  200. {
  201. if (system_scanned)
  202. return;
  203. dmi_walk(enumerate_dimms, &ghes_hw);
  204. system_scanned = true;
  205. }
  206. static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
  207. const char *location, unsigned int len)
  208. {
  209. u32 n;
  210. if (!msg)
  211. return 0;
  212. n = 0;
  213. len -= 1;
  214. n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
  215. if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
  216. goto out;
  217. n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
  218. n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
  219. out:
  220. msg[n] = '\0';
  221. return n;
  222. }
  223. void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
  224. {
  225. struct cper_mem_err_compact cmem;
  226. struct edac_raw_error_desc *e;
  227. struct mem_ctl_info *mci;
  228. struct ghes_pvt *pvt;
  229. unsigned long flags;
  230. char *p;
  231. /*
  232. * We can do the locking below because GHES defers error processing
  233. * from NMI to IRQ context. Whenever that changes, we'd at least
  234. * know.
  235. */
  236. if (WARN_ON_ONCE(in_nmi()))
  237. return;
  238. spin_lock_irqsave(&ghes_lock, flags);
  239. pvt = ghes_pvt;
  240. if (!pvt)
  241. goto unlock;
  242. mci = pvt->mci;
  243. e = &mci->error_desc;
  244. /* Cleans the error report buffer */
  245. memset(e, 0, sizeof (*e));
  246. e->error_count = 1;
  247. e->grain = 1;
  248. e->msg = pvt->msg;
  249. e->other_detail = pvt->other_detail;
  250. e->top_layer = -1;
  251. e->mid_layer = -1;
  252. e->low_layer = -1;
  253. *pvt->other_detail = '\0';
  254. *pvt->msg = '\0';
  255. switch (sev) {
  256. case GHES_SEV_CORRECTED:
  257. e->type = HW_EVENT_ERR_CORRECTED;
  258. break;
  259. case GHES_SEV_RECOVERABLE:
  260. e->type = HW_EVENT_ERR_UNCORRECTED;
  261. break;
  262. case GHES_SEV_PANIC:
  263. e->type = HW_EVENT_ERR_FATAL;
  264. break;
  265. default:
  266. case GHES_SEV_NO:
  267. e->type = HW_EVENT_ERR_INFO;
  268. }
  269. edac_dbg(1, "error validation_bits: 0x%08llx\n",
  270. (long long)mem_err->validation_bits);
  271. /* Error type, mapped on e->msg */
  272. if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
  273. u8 etype = mem_err->error_type;
  274. p = pvt->msg;
  275. p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
  276. } else {
  277. strcpy(pvt->msg, "unknown error");
  278. }
  279. /* Error address */
  280. if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
  281. e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
  282. e->offset_in_page = offset_in_page(mem_err->physical_addr);
  283. }
  284. /* Error grain */
  285. if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
  286. e->grain = ~mem_err->physical_addr_mask + 1;
  287. /* Memory error location, mapped on e->location */
  288. p = e->location;
  289. cper_mem_err_pack(mem_err, &cmem);
  290. p += cper_mem_err_location(&cmem, p);
  291. if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
  292. struct dimm_info *dimm;
  293. p += cper_dimm_err_location(&cmem, p);
  294. dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
  295. if (dimm) {
  296. e->top_layer = dimm->idx;
  297. strcpy(e->label, dimm->label);
  298. }
  299. }
  300. if (p > e->location)
  301. *(p - 1) = '\0';
  302. if (!*e->label)
  303. strcpy(e->label, "unknown memory");
  304. /* All other fields are mapped on e->other_detail */
  305. p = pvt->other_detail;
  306. p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
  307. if (p > pvt->other_detail)
  308. *(p - 1) = '\0';
  309. edac_raw_mc_handle_error(e);
  310. unlock:
  311. spin_unlock_irqrestore(&ghes_lock, flags);
  312. }
  313. /*
  314. * Known systems that are safe to enable this module.
  315. */
  316. static struct acpi_platform_list plat_list[] = {
  317. {"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
  318. { } /* End */
  319. };
  320. int ghes_edac_register(struct ghes *ghes, struct device *dev)
  321. {
  322. bool fake = false;
  323. struct mem_ctl_info *mci;
  324. struct ghes_pvt *pvt;
  325. struct edac_mc_layer layers[1];
  326. unsigned long flags;
  327. int idx = -1;
  328. int rc = 0;
  329. if (IS_ENABLED(CONFIG_X86)) {
  330. /* Check if safe to enable on this system */
  331. idx = acpi_match_platform_list(plat_list);
  332. if (!force_load && idx < 0)
  333. return -ENODEV;
  334. } else {
  335. force_load = true;
  336. idx = 0;
  337. }
  338. /* finish another registration/unregistration instance first */
  339. mutex_lock(&ghes_reg_mutex);
  340. /*
  341. * We have only one logical memory controller to which all DIMMs belong.
  342. */
  343. if (refcount_inc_not_zero(&ghes_refcount))
  344. goto unlock;
  345. ghes_scan_system();
  346. /* Check if we've got a bogus BIOS */
  347. if (!ghes_hw.num_dimms) {
  348. fake = true;
  349. ghes_hw.num_dimms = 1;
  350. }
  351. layers[0].type = EDAC_MC_LAYER_ALL_MEM;
  352. layers[0].size = ghes_hw.num_dimms;
  353. layers[0].is_virt_csrow = true;
  354. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
  355. if (!mci) {
  356. pr_info("Can't allocate memory for EDAC data\n");
  357. rc = -ENOMEM;
  358. goto unlock;
  359. }
  360. pvt = mci->pvt_info;
  361. pvt->mci = mci;
  362. mci->pdev = dev;
  363. mci->mtype_cap = MEM_FLAG_EMPTY;
  364. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  365. mci->edac_cap = EDAC_FLAG_NONE;
  366. mci->mod_name = "ghes_edac.c";
  367. mci->ctl_name = "ghes_edac";
  368. mci->dev_name = "ghes";
  369. if (fake) {
  370. pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
  371. pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
  372. pr_info("work on such system. Use this driver with caution\n");
  373. } else if (idx < 0) {
  374. pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
  375. pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
  376. pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
  377. pr_info("If you find incorrect reports, please contact your hardware vendor\n");
  378. pr_info("to correct its BIOS.\n");
  379. pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
  380. }
  381. if (!fake) {
  382. struct dimm_info *src, *dst;
  383. int i = 0;
  384. mci_for_each_dimm(mci, dst) {
  385. src = &ghes_hw.dimms[i];
  386. dst->idx = src->idx;
  387. dst->smbios_handle = src->smbios_handle;
  388. dst->nr_pages = src->nr_pages;
  389. dst->mtype = src->mtype;
  390. dst->edac_mode = src->edac_mode;
  391. dst->dtype = src->dtype;
  392. dst->grain = src->grain;
  393. /*
  394. * If no src->label, preserve default label assigned
  395. * from EDAC core.
  396. */
  397. if (strlen(src->label))
  398. memcpy(dst->label, src->label, sizeof(src->label));
  399. i++;
  400. }
  401. } else {
  402. struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
  403. dimm->nr_pages = 1;
  404. dimm->grain = 128;
  405. dimm->mtype = MEM_UNKNOWN;
  406. dimm->dtype = DEV_UNKNOWN;
  407. dimm->edac_mode = EDAC_SECDED;
  408. }
  409. rc = edac_mc_add_mc(mci);
  410. if (rc < 0) {
  411. pr_info("Can't register with the EDAC core\n");
  412. edac_mc_free(mci);
  413. rc = -ENODEV;
  414. goto unlock;
  415. }
  416. spin_lock_irqsave(&ghes_lock, flags);
  417. ghes_pvt = pvt;
  418. spin_unlock_irqrestore(&ghes_lock, flags);
  419. /* only set on success */
  420. refcount_set(&ghes_refcount, 1);
  421. unlock:
  422. /* Not needed anymore */
  423. kfree(ghes_hw.dimms);
  424. ghes_hw.dimms = NULL;
  425. mutex_unlock(&ghes_reg_mutex);
  426. return rc;
  427. }
  428. void ghes_edac_unregister(struct ghes *ghes)
  429. {
  430. struct mem_ctl_info *mci;
  431. unsigned long flags;
  432. if (!force_load)
  433. return;
  434. mutex_lock(&ghes_reg_mutex);
  435. system_scanned = false;
  436. memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
  437. if (!refcount_dec_and_test(&ghes_refcount))
  438. goto unlock;
  439. /*
  440. * Wait for the irq handler being finished.
  441. */
  442. spin_lock_irqsave(&ghes_lock, flags);
  443. mci = ghes_pvt ? ghes_pvt->mci : NULL;
  444. ghes_pvt = NULL;
  445. spin_unlock_irqrestore(&ghes_lock, flags);
  446. if (!mci)
  447. goto unlock;
  448. mci = edac_mc_del_mc(mci->pdev);
  449. if (mci)
  450. edac_mc_free(mci);
  451. unlock:
  452. mutex_unlock(&ghes_reg_mutex);
  453. }