amd64_edac.h 15 KB

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  1. /*
  2. * AMD64 class Memory Controller kernel module
  3. *
  4. * Copyright (c) 2009 SoftwareBitMaker.
  5. * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
  6. *
  7. * This file may be distributed under the terms of the
  8. * GNU General Public License.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/ctype.h>
  12. #include <linux/init.h>
  13. #include <linux/pci.h>
  14. #include <linux/pci_ids.h>
  15. #include <linux/slab.h>
  16. #include <linux/mmzone.h>
  17. #include <linux/edac.h>
  18. #include <asm/cpu_device_id.h>
  19. #include <asm/msr.h>
  20. #include "edac_module.h"
  21. #include "mce_amd.h"
  22. #define amd64_info(fmt, arg...) \
  23. edac_printk(KERN_INFO, "amd64", fmt, ##arg)
  24. #define amd64_warn(fmt, arg...) \
  25. edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
  26. #define amd64_err(fmt, arg...) \
  27. edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
  28. #define amd64_mc_warn(mci, fmt, arg...) \
  29. edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
  30. #define amd64_mc_err(mci, fmt, arg...) \
  31. edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
  32. /*
  33. * Throughout the comments in this code, the following terms are used:
  34. *
  35. * SysAddr, DramAddr, and InputAddr
  36. *
  37. * These terms come directly from the amd64 documentation
  38. * (AMD publication #26094). They are defined as follows:
  39. *
  40. * SysAddr:
  41. * This is a physical address generated by a CPU core or a device
  42. * doing DMA. If generated by a CPU core, a SysAddr is the result of
  43. * a virtual to physical address translation by the CPU core's address
  44. * translation mechanism (MMU).
  45. *
  46. * DramAddr:
  47. * A DramAddr is derived from a SysAddr by subtracting an offset that
  48. * depends on which node the SysAddr maps to and whether the SysAddr
  49. * is within a range affected by memory hoisting. The DRAM Base
  50. * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
  51. * determine which node a SysAddr maps to.
  52. *
  53. * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
  54. * is within the range of addresses specified by this register, then
  55. * a value x from the DHAR is subtracted from the SysAddr to produce a
  56. * DramAddr. Here, x represents the base address for the node that
  57. * the SysAddr maps to plus an offset due to memory hoisting. See
  58. * section 3.4.8 and the comments in amd64_get_dram_hole_info() and
  59. * sys_addr_to_dram_addr() below for more information.
  60. *
  61. * If the SysAddr is not affected by the DHAR then a value y is
  62. * subtracted from the SysAddr to produce a DramAddr. Here, y is the
  63. * base address for the node that the SysAddr maps to. See section
  64. * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
  65. * information.
  66. *
  67. * InputAddr:
  68. * A DramAddr is translated to an InputAddr before being passed to the
  69. * memory controller for the node that the DramAddr is associated
  70. * with. The memory controller then maps the InputAddr to a csrow.
  71. * If node interleaving is not in use, then the InputAddr has the same
  72. * value as the DramAddr. Otherwise, the InputAddr is produced by
  73. * discarding the bits used for node interleaving from the DramAddr.
  74. * See section 3.4.4 for more information.
  75. *
  76. * The memory controller for a given node uses its DRAM CS Base and
  77. * DRAM CS Mask registers to map an InputAddr to a csrow. See
  78. * sections 3.5.4 and 3.5.5 for more information.
  79. */
  80. #define EDAC_AMD64_VERSION "3.5.0"
  81. #define EDAC_MOD_STR "amd64_edac"
  82. /* Extended Model from CPUID, for CPU Revision numbers */
  83. #define K8_REV_D 1
  84. #define K8_REV_E 2
  85. #define K8_REV_F 4
  86. /* Hardware limit on ChipSelect rows per MC and processors per system */
  87. #define NUM_CHIPSELECTS 8
  88. #define DRAM_RANGES 8
  89. #define NUM_CONTROLLERS 12
  90. #define ON true
  91. #define OFF false
  92. /*
  93. * PCI-defined configuration space registers
  94. */
  95. #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
  96. #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
  97. #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
  98. #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
  99. #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
  100. #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
  101. #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
  102. #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
  103. #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
  104. #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
  105. #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
  106. #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
  107. #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
  108. #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
  109. #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
  110. #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
  111. #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
  112. #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
  113. #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
  114. #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
  115. #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650
  116. #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656
  117. #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
  118. #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
  119. #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
  120. #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670
  121. /*
  122. * Function 1 - Address Map
  123. */
  124. #define DRAM_BASE_LO 0x40
  125. #define DRAM_LIMIT_LO 0x44
  126. /*
  127. * F15 M30h D18F1x2[1C:00]
  128. */
  129. #define DRAM_CONT_BASE 0x200
  130. #define DRAM_CONT_LIMIT 0x204
  131. /*
  132. * F15 M30h D18F1x2[4C:40]
  133. */
  134. #define DRAM_CONT_HIGH_OFF 0x240
  135. #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
  136. #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
  137. #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
  138. #define DHAR 0xf0
  139. #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
  140. #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
  141. #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
  142. /* NOTE: Extra mask bit vs K8 */
  143. #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
  144. #define DCT_CFG_SEL 0x10C
  145. #define DRAM_LOCAL_NODE_BASE 0x120
  146. #define DRAM_LOCAL_NODE_LIM 0x124
  147. #define DRAM_BASE_HI 0x140
  148. #define DRAM_LIMIT_HI 0x144
  149. /*
  150. * Function 2 - DRAM controller
  151. */
  152. #define DCSB0 0x40
  153. #define DCSB1 0x140
  154. #define DCSB_CS_ENABLE BIT(0)
  155. #define DCSM0 0x60
  156. #define DCSM1 0x160
  157. #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
  158. #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
  159. #define DRAM_CONTROL 0x78
  160. #define DBAM0 0x80
  161. #define DBAM1 0x180
  162. /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
  163. #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
  164. #define DBAM_MAX_VALUE 11
  165. #define DCLR0 0x90
  166. #define DCLR1 0x190
  167. #define REVE_WIDTH_128 BIT(16)
  168. #define WIDTH_128 BIT(11)
  169. #define DCHR0 0x94
  170. #define DCHR1 0x194
  171. #define DDR3_MODE BIT(8)
  172. #define DCT_SEL_LO 0x110
  173. #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
  174. #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
  175. #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
  176. #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
  177. #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
  178. #define SWAP_INTLV_REG 0x10c
  179. #define DCT_SEL_HI 0x114
  180. #define F15H_M60H_SCRCTRL 0x1C8
  181. #define F17H_SCR_BASE_ADDR 0x48
  182. #define F17H_SCR_LIMIT_ADDR 0x4C
  183. /*
  184. * Function 3 - Misc Control
  185. */
  186. #define NBCTL 0x40
  187. #define NBCFG 0x44
  188. #define NBCFG_CHIPKILL BIT(23)
  189. #define NBCFG_ECC_ENABLE BIT(22)
  190. /* F3x48: NBSL */
  191. #define F10_NBSL_EXT_ERR_ECC 0x8
  192. #define NBSL_PP_OBS 0x2
  193. #define SCRCTRL 0x58
  194. #define F10_ONLINE_SPARE 0xB0
  195. #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
  196. #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
  197. #define F10_NB_ARRAY_ADDR 0xB8
  198. #define F10_NB_ARRAY_DRAM BIT(31)
  199. /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
  200. #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
  201. #define F10_NB_ARRAY_DATA 0xBC
  202. #define F10_NB_ARR_ECC_WR_REQ BIT(17)
  203. #define SET_NB_DRAM_INJECTION_WRITE(inj) \
  204. (BIT(((inj.word) & 0xF) + 20) | \
  205. F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
  206. #define SET_NB_DRAM_INJECTION_READ(inj) \
  207. (BIT(((inj.word) & 0xF) + 20) | \
  208. BIT(16) | inj.bit_map)
  209. #define NBCAP 0xE8
  210. #define NBCAP_CHIPKILL BIT(4)
  211. #define NBCAP_SECDED BIT(3)
  212. #define NBCAP_DCT_DUAL BIT(0)
  213. #define EXT_NB_MCA_CFG 0x180
  214. /* MSRs */
  215. #define MSR_MCGCTL_NBE BIT(4)
  216. /* F17h */
  217. /* F0: */
  218. #define DF_DHAR 0x104
  219. /* UMC CH register offsets */
  220. #define UMCCH_BASE_ADDR 0x0
  221. #define UMCCH_BASE_ADDR_SEC 0x10
  222. #define UMCCH_ADDR_MASK 0x20
  223. #define UMCCH_ADDR_MASK_SEC 0x28
  224. #define UMCCH_ADDR_MASK_SEC_DDR5 0x30
  225. #define UMCCH_ADDR_CFG 0x30
  226. #define UMCCH_ADDR_CFG_DDR5 0x40
  227. #define UMCCH_DIMM_CFG 0x80
  228. #define UMCCH_DIMM_CFG_DDR5 0x90
  229. #define UMCCH_UMC_CFG 0x100
  230. #define UMCCH_SDP_CTRL 0x104
  231. #define UMCCH_ECC_CTRL 0x14C
  232. #define UMCCH_ECC_BAD_SYMBOL 0xD90
  233. #define UMCCH_UMC_CAP 0xDF0
  234. #define UMCCH_UMC_CAP_HI 0xDF4
  235. /* UMC CH bitfields */
  236. #define UMC_ECC_CHIPKILL_CAP BIT(31)
  237. #define UMC_ECC_ENABLED BIT(30)
  238. #define UMC_SDP_INIT BIT(31)
  239. enum amd_families {
  240. K8_CPUS = 0,
  241. F10_CPUS,
  242. F15_CPUS,
  243. F15_M30H_CPUS,
  244. F15_M60H_CPUS,
  245. F16_CPUS,
  246. F16_M30H_CPUS,
  247. F17_CPUS,
  248. F17_M10H_CPUS,
  249. F17_M30H_CPUS,
  250. F17_M60H_CPUS,
  251. F17_M70H_CPUS,
  252. F19_CPUS,
  253. F19_M10H_CPUS,
  254. F19_M50H_CPUS,
  255. NUM_FAMILIES,
  256. };
  257. /* Error injection control structure */
  258. struct error_injection {
  259. u32 section;
  260. u32 word;
  261. u32 bit_map;
  262. };
  263. /* low and high part of PCI config space regs */
  264. struct reg_pair {
  265. u32 lo, hi;
  266. };
  267. /*
  268. * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
  269. */
  270. struct dram_range {
  271. struct reg_pair base;
  272. struct reg_pair lim;
  273. };
  274. /* A DCT chip selects collection */
  275. struct chip_select {
  276. u32 csbases[NUM_CHIPSELECTS];
  277. u32 csbases_sec[NUM_CHIPSELECTS];
  278. u8 b_cnt;
  279. u32 csmasks[NUM_CHIPSELECTS];
  280. u32 csmasks_sec[NUM_CHIPSELECTS];
  281. u8 m_cnt;
  282. };
  283. struct amd64_umc {
  284. u32 dimm_cfg; /* DIMM Configuration reg */
  285. u32 umc_cfg; /* Configuration reg */
  286. u32 sdp_ctrl; /* SDP Control reg */
  287. u32 ecc_ctrl; /* DRAM ECC Control reg */
  288. u32 umc_cap_hi; /* Capabilities High reg */
  289. /* cache the dram_type */
  290. enum mem_type dram_type;
  291. };
  292. struct amd64_pvt {
  293. struct low_ops *ops;
  294. /* pci_device handles which we utilize */
  295. struct pci_dev *F0, *F1, *F2, *F3, *F6;
  296. u16 mc_node_id; /* MC index of this MC node */
  297. u8 fam; /* CPU family */
  298. u8 model; /* ... model */
  299. u8 stepping; /* ... stepping */
  300. int ext_model; /* extended model value of this node */
  301. int channel_count;
  302. /* Raw registers */
  303. u32 dclr0; /* DRAM Configuration Low DCT0 reg */
  304. u32 dclr1; /* DRAM Configuration Low DCT1 reg */
  305. u32 dchr0; /* DRAM Configuration High DCT0 reg */
  306. u32 dchr1; /* DRAM Configuration High DCT1 reg */
  307. u32 nbcap; /* North Bridge Capabilities */
  308. u32 nbcfg; /* F10 North Bridge Configuration */
  309. u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
  310. u32 dhar; /* DRAM Hoist reg */
  311. u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
  312. u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
  313. /* one for each DCT/UMC */
  314. struct chip_select csels[NUM_CONTROLLERS];
  315. /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
  316. struct dram_range ranges[DRAM_RANGES];
  317. u64 top_mem; /* top of memory below 4GB */
  318. u64 top_mem2; /* top of memory above 4GB */
  319. u32 dct_sel_lo; /* DRAM Controller Select Low */
  320. u32 dct_sel_hi; /* DRAM Controller Select High */
  321. u32 online_spare; /* On-Line spare Reg */
  322. /* x4, x8, or x16 syndromes in use */
  323. u8 ecc_sym_sz;
  324. /* place to store error injection parameters prior to issue */
  325. struct error_injection injection;
  326. /*
  327. * cache the dram_type
  328. *
  329. * NOTE: Don't use this for Family 17h and later.
  330. * Use dram_type in struct amd64_umc instead.
  331. */
  332. enum mem_type dram_type;
  333. struct amd64_umc *umc; /* UMC registers */
  334. };
  335. enum err_codes {
  336. DECODE_OK = 0,
  337. ERR_NODE = -1,
  338. ERR_CSROW = -2,
  339. ERR_CHANNEL = -3,
  340. ERR_SYND = -4,
  341. ERR_NORM_ADDR = -5,
  342. };
  343. struct err_info {
  344. int err_code;
  345. struct mem_ctl_info *src_mci;
  346. int csrow;
  347. int channel;
  348. u16 syndrome;
  349. u32 page;
  350. u32 offset;
  351. };
  352. static inline u32 get_umc_base(u8 channel)
  353. {
  354. /* chY: 0xY50000 */
  355. return 0x50000 + (channel << 20);
  356. }
  357. static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
  358. {
  359. u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
  360. if (boot_cpu_data.x86 == 0xf)
  361. return addr;
  362. return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
  363. }
  364. static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
  365. {
  366. u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
  367. if (boot_cpu_data.x86 == 0xf)
  368. return lim;
  369. return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
  370. }
  371. static inline u16 extract_syndrome(u64 status)
  372. {
  373. return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
  374. }
  375. static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
  376. {
  377. if (pvt->fam == 0x15 && pvt->model >= 0x30)
  378. return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
  379. ((pvt->dct_sel_lo >> 6) & 0x3);
  380. return ((pvt)->dct_sel_lo >> 6) & 0x3;
  381. }
  382. /*
  383. * per-node ECC settings descriptor
  384. */
  385. struct ecc_settings {
  386. u32 old_nbctl;
  387. bool nbctl_valid;
  388. struct flags {
  389. unsigned long nb_mce_enable:1;
  390. unsigned long nb_ecc_prev:1;
  391. } flags;
  392. };
  393. /*
  394. * Each of the PCI Device IDs types have their own set of hardware accessor
  395. * functions and per device encoding/decoding logic.
  396. */
  397. struct low_ops {
  398. int (*early_channel_count) (struct amd64_pvt *pvt);
  399. void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
  400. struct err_info *);
  401. int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
  402. unsigned cs_mode, int cs_mask_nr);
  403. };
  404. struct amd64_family_flags {
  405. /*
  406. * Indicates that the system supports the new register offsets, etc.
  407. * first introduced with Family 19h Model 10h.
  408. */
  409. __u64 zn_regs_v2 : 1,
  410. __reserved : 63;
  411. };
  412. struct amd64_family_type {
  413. const char *ctl_name;
  414. u16 f0_id, f1_id, f2_id, f6_id;
  415. /* Maximum number of memory controllers per die/node. */
  416. u8 max_mcs;
  417. struct amd64_family_flags flags;
  418. struct low_ops ops;
  419. };
  420. int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
  421. u32 *val, const char *func);
  422. int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
  423. u32 val, const char *func);
  424. #define amd64_read_pci_cfg(pdev, offset, val) \
  425. __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
  426. #define amd64_write_pci_cfg(pdev, offset, val) \
  427. __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
  428. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  429. /* Injection helpers */
  430. static inline void disable_caches(void *dummy)
  431. {
  432. write_cr0(read_cr0() | X86_CR0_CD);
  433. wbinvd();
  434. }
  435. static inline void enable_caches(void *dummy)
  436. {
  437. write_cr0(read_cr0() & ~X86_CR0_CD);
  438. }
  439. static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
  440. {
  441. if (pvt->fam == 0x15 && pvt->model >= 0x30) {
  442. u32 tmp;
  443. amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
  444. return (u8) tmp & 0xF;
  445. }
  446. return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
  447. }
  448. static inline u8 dhar_valid(struct amd64_pvt *pvt)
  449. {
  450. if (pvt->fam == 0x15 && pvt->model >= 0x30) {
  451. u32 tmp;
  452. amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
  453. return (tmp >> 1) & BIT(0);
  454. }
  455. return (pvt)->dhar & BIT(0);
  456. }
  457. static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
  458. {
  459. if (pvt->fam == 0x15 && pvt->model >= 0x30) {
  460. u32 tmp;
  461. amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
  462. return (tmp >> 11) & 0x1FFF;
  463. }
  464. return (pvt)->dct_sel_lo & 0xFFFFF800;
  465. }