amd64_edac.c 112 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include "amd64_edac.h"
  3. #include <asm/amd_nb.h>
  4. static struct edac_pci_ctl_info *pci_ctl;
  5. /*
  6. * Set by command line parameter. If BIOS has enabled the ECC, this override is
  7. * cleared to prevent re-enabling the hardware by this driver.
  8. */
  9. static int ecc_enable_override;
  10. module_param(ecc_enable_override, int, 0644);
  11. static struct msr __percpu *msrs;
  12. static struct amd64_family_type *fam_type;
  13. static inline u32 get_umc_reg(u32 reg)
  14. {
  15. if (!fam_type->flags.zn_regs_v2)
  16. return reg;
  17. switch (reg) {
  18. case UMCCH_ADDR_CFG: return UMCCH_ADDR_CFG_DDR5;
  19. case UMCCH_ADDR_MASK_SEC: return UMCCH_ADDR_MASK_SEC_DDR5;
  20. case UMCCH_DIMM_CFG: return UMCCH_DIMM_CFG_DDR5;
  21. }
  22. WARN_ONCE(1, "%s: unknown register 0x%x", __func__, reg);
  23. return 0;
  24. }
  25. /* Per-node stuff */
  26. static struct ecc_settings **ecc_stngs;
  27. /* Device for the PCI component */
  28. static struct device *pci_ctl_dev;
  29. /*
  30. * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
  31. * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
  32. * or higher value'.
  33. *
  34. *FIXME: Produce a better mapping/linearisation.
  35. */
  36. static const struct scrubrate {
  37. u32 scrubval; /* bit pattern for scrub rate */
  38. u32 bandwidth; /* bandwidth consumed (bytes/sec) */
  39. } scrubrates[] = {
  40. { 0x01, 1600000000UL},
  41. { 0x02, 800000000UL},
  42. { 0x03, 400000000UL},
  43. { 0x04, 200000000UL},
  44. { 0x05, 100000000UL},
  45. { 0x06, 50000000UL},
  46. { 0x07, 25000000UL},
  47. { 0x08, 12284069UL},
  48. { 0x09, 6274509UL},
  49. { 0x0A, 3121951UL},
  50. { 0x0B, 1560975UL},
  51. { 0x0C, 781440UL},
  52. { 0x0D, 390720UL},
  53. { 0x0E, 195300UL},
  54. { 0x0F, 97650UL},
  55. { 0x10, 48854UL},
  56. { 0x11, 24427UL},
  57. { 0x12, 12213UL},
  58. { 0x13, 6101UL},
  59. { 0x14, 3051UL},
  60. { 0x15, 1523UL},
  61. { 0x16, 761UL},
  62. { 0x00, 0UL}, /* scrubbing off */
  63. };
  64. int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
  65. u32 *val, const char *func)
  66. {
  67. int err = 0;
  68. err = pci_read_config_dword(pdev, offset, val);
  69. if (err)
  70. amd64_warn("%s: error reading F%dx%03x.\n",
  71. func, PCI_FUNC(pdev->devfn), offset);
  72. return err;
  73. }
  74. int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
  75. u32 val, const char *func)
  76. {
  77. int err = 0;
  78. err = pci_write_config_dword(pdev, offset, val);
  79. if (err)
  80. amd64_warn("%s: error writing to F%dx%03x.\n",
  81. func, PCI_FUNC(pdev->devfn), offset);
  82. return err;
  83. }
  84. /*
  85. * Select DCT to which PCI cfg accesses are routed
  86. */
  87. static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
  88. {
  89. u32 reg = 0;
  90. amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
  91. reg &= (pvt->model == 0x30) ? ~3 : ~1;
  92. reg |= dct;
  93. amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
  94. }
  95. /*
  96. *
  97. * Depending on the family, F2 DCT reads need special handling:
  98. *
  99. * K8: has a single DCT only and no address offsets >= 0x100
  100. *
  101. * F10h: each DCT has its own set of regs
  102. * DCT0 -> F2x040..
  103. * DCT1 -> F2x140..
  104. *
  105. * F16h: has only 1 DCT
  106. *
  107. * F15h: we select which DCT we access using F1x10C[DctCfgSel]
  108. */
  109. static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
  110. int offset, u32 *val)
  111. {
  112. switch (pvt->fam) {
  113. case 0xf:
  114. if (dct || offset >= 0x100)
  115. return -EINVAL;
  116. break;
  117. case 0x10:
  118. if (dct) {
  119. /*
  120. * Note: If ganging is enabled, barring the regs
  121. * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx
  122. * return 0. (cf. Section 2.8.1 F10h BKDG)
  123. */
  124. if (dct_ganging_enabled(pvt))
  125. return 0;
  126. offset += 0x100;
  127. }
  128. break;
  129. case 0x15:
  130. /*
  131. * F15h: F2x1xx addresses do not map explicitly to DCT1.
  132. * We should select which DCT we access using F1x10C[DctCfgSel]
  133. */
  134. dct = (dct && pvt->model == 0x30) ? 3 : dct;
  135. f15h_select_dct(pvt, dct);
  136. break;
  137. case 0x16:
  138. if (dct)
  139. return -EINVAL;
  140. break;
  141. default:
  142. break;
  143. }
  144. return amd64_read_pci_cfg(pvt->F2, offset, val);
  145. }
  146. /*
  147. * Memory scrubber control interface. For K8, memory scrubbing is handled by
  148. * hardware and can involve L2 cache, dcache as well as the main memory. With
  149. * F10, this is extended to L3 cache scrubbing on CPU models sporting that
  150. * functionality.
  151. *
  152. * This causes the "units" for the scrubbing speed to vary from 64 byte blocks
  153. * (dram) over to cache lines. This is nasty, so we will use bandwidth in
  154. * bytes/sec for the setting.
  155. *
  156. * Currently, we only do dram scrubbing. If the scrubbing is done in software on
  157. * other archs, we might not have access to the caches directly.
  158. */
  159. static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
  160. {
  161. /*
  162. * Fam17h supports scrub values between 0x5 and 0x14. Also, the values
  163. * are shifted down by 0x5, so scrubval 0x5 is written to the register
  164. * as 0x0, scrubval 0x6 as 0x1, etc.
  165. */
  166. if (scrubval >= 0x5 && scrubval <= 0x14) {
  167. scrubval -= 0x5;
  168. pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);
  169. pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);
  170. } else {
  171. pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);
  172. }
  173. }
  174. /*
  175. * Scan the scrub rate mapping table for a close or matching bandwidth value to
  176. * issue. If requested is too big, then use last maximum value found.
  177. */
  178. static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
  179. {
  180. u32 scrubval;
  181. int i;
  182. /*
  183. * map the configured rate (new_bw) to a value specific to the AMD64
  184. * memory controller and apply to register. Search for the first
  185. * bandwidth entry that is greater or equal than the setting requested
  186. * and program that. If at last entry, turn off DRAM scrubbing.
  187. *
  188. * If no suitable bandwidth is found, turn off DRAM scrubbing entirely
  189. * by falling back to the last element in scrubrates[].
  190. */
  191. for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) {
  192. /*
  193. * skip scrub rates which aren't recommended
  194. * (see F10 BKDG, F3x58)
  195. */
  196. if (scrubrates[i].scrubval < min_rate)
  197. continue;
  198. if (scrubrates[i].bandwidth <= new_bw)
  199. break;
  200. }
  201. scrubval = scrubrates[i].scrubval;
  202. if (pvt->umc) {
  203. __f17h_set_scrubval(pvt, scrubval);
  204. } else if (pvt->fam == 0x15 && pvt->model == 0x60) {
  205. f15h_select_dct(pvt, 0);
  206. pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
  207. f15h_select_dct(pvt, 1);
  208. pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
  209. } else {
  210. pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
  211. }
  212. if (scrubval)
  213. return scrubrates[i].bandwidth;
  214. return 0;
  215. }
  216. static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
  217. {
  218. struct amd64_pvt *pvt = mci->pvt_info;
  219. u32 min_scrubrate = 0x5;
  220. if (pvt->fam == 0xf)
  221. min_scrubrate = 0x0;
  222. if (pvt->fam == 0x15) {
  223. /* Erratum #505 */
  224. if (pvt->model < 0x10)
  225. f15h_select_dct(pvt, 0);
  226. if (pvt->model == 0x60)
  227. min_scrubrate = 0x6;
  228. }
  229. return __set_scrub_rate(pvt, bw, min_scrubrate);
  230. }
  231. static int get_scrub_rate(struct mem_ctl_info *mci)
  232. {
  233. struct amd64_pvt *pvt = mci->pvt_info;
  234. int i, retval = -EINVAL;
  235. u32 scrubval = 0;
  236. if (pvt->umc) {
  237. amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
  238. if (scrubval & BIT(0)) {
  239. amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
  240. scrubval &= 0xF;
  241. scrubval += 0x5;
  242. } else {
  243. scrubval = 0;
  244. }
  245. } else if (pvt->fam == 0x15) {
  246. /* Erratum #505 */
  247. if (pvt->model < 0x10)
  248. f15h_select_dct(pvt, 0);
  249. if (pvt->model == 0x60)
  250. amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
  251. else
  252. amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
  253. } else {
  254. amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
  255. }
  256. scrubval = scrubval & 0x001F;
  257. for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
  258. if (scrubrates[i].scrubval == scrubval) {
  259. retval = scrubrates[i].bandwidth;
  260. break;
  261. }
  262. }
  263. return retval;
  264. }
  265. /*
  266. * returns true if the SysAddr given by sys_addr matches the
  267. * DRAM base/limit associated with node_id
  268. */
  269. static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
  270. {
  271. u64 addr;
  272. /* The K8 treats this as a 40-bit value. However, bits 63-40 will be
  273. * all ones if the most significant implemented address bit is 1.
  274. * Here we discard bits 63-40. See section 3.4.2 of AMD publication
  275. * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1
  276. * Application Programming.
  277. */
  278. addr = sys_addr & 0x000000ffffffffffull;
  279. return ((addr >= get_dram_base(pvt, nid)) &&
  280. (addr <= get_dram_limit(pvt, nid)));
  281. }
  282. /*
  283. * Attempt to map a SysAddr to a node. On success, return a pointer to the
  284. * mem_ctl_info structure for the node that the SysAddr maps to.
  285. *
  286. * On failure, return NULL.
  287. */
  288. static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
  289. u64 sys_addr)
  290. {
  291. struct amd64_pvt *pvt;
  292. u8 node_id;
  293. u32 intlv_en, bits;
  294. /*
  295. * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section
  296. * 3.4.4.2) registers to map the SysAddr to a node ID.
  297. */
  298. pvt = mci->pvt_info;
  299. /*
  300. * The value of this field should be the same for all DRAM Base
  301. * registers. Therefore we arbitrarily choose to read it from the
  302. * register for node 0.
  303. */
  304. intlv_en = dram_intlv_en(pvt, 0);
  305. if (intlv_en == 0) {
  306. for (node_id = 0; node_id < DRAM_RANGES; node_id++) {
  307. if (base_limit_match(pvt, sys_addr, node_id))
  308. goto found;
  309. }
  310. goto err_no_match;
  311. }
  312. if (unlikely((intlv_en != 0x01) &&
  313. (intlv_en != 0x03) &&
  314. (intlv_en != 0x07))) {
  315. amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en);
  316. return NULL;
  317. }
  318. bits = (((u32) sys_addr) >> 12) & intlv_en;
  319. for (node_id = 0; ; ) {
  320. if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
  321. break; /* intlv_sel field matches */
  322. if (++node_id >= DRAM_RANGES)
  323. goto err_no_match;
  324. }
  325. /* sanity test for sys_addr */
  326. if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
  327. amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address"
  328. "range for node %d with node interleaving enabled.\n",
  329. __func__, sys_addr, node_id);
  330. return NULL;
  331. }
  332. found:
  333. return edac_mc_find((int)node_id);
  334. err_no_match:
  335. edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
  336. (unsigned long)sys_addr);
  337. return NULL;
  338. }
  339. /*
  340. * compute the CS base address of the @csrow on the DRAM controller @dct.
  341. * For details see F2x[5C:40] in the processor's BKDG
  342. */
  343. static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
  344. u64 *base, u64 *mask)
  345. {
  346. u64 csbase, csmask, base_bits, mask_bits;
  347. u8 addr_shift;
  348. if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
  349. csbase = pvt->csels[dct].csbases[csrow];
  350. csmask = pvt->csels[dct].csmasks[csrow];
  351. base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9);
  352. mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9);
  353. addr_shift = 4;
  354. /*
  355. * F16h and F15h, models 30h and later need two addr_shift values:
  356. * 8 for high and 6 for low (cf. F16h BKDG).
  357. */
  358. } else if (pvt->fam == 0x16 ||
  359. (pvt->fam == 0x15 && pvt->model >= 0x30)) {
  360. csbase = pvt->csels[dct].csbases[csrow];
  361. csmask = pvt->csels[dct].csmasks[csrow >> 1];
  362. *base = (csbase & GENMASK_ULL(15, 5)) << 6;
  363. *base |= (csbase & GENMASK_ULL(30, 19)) << 8;
  364. *mask = ~0ULL;
  365. /* poke holes for the csmask */
  366. *mask &= ~((GENMASK_ULL(15, 5) << 6) |
  367. (GENMASK_ULL(30, 19) << 8));
  368. *mask |= (csmask & GENMASK_ULL(15, 5)) << 6;
  369. *mask |= (csmask & GENMASK_ULL(30, 19)) << 8;
  370. return;
  371. } else {
  372. csbase = pvt->csels[dct].csbases[csrow];
  373. csmask = pvt->csels[dct].csmasks[csrow >> 1];
  374. addr_shift = 8;
  375. if (pvt->fam == 0x15)
  376. base_bits = mask_bits =
  377. GENMASK_ULL(30,19) | GENMASK_ULL(13,5);
  378. else
  379. base_bits = mask_bits =
  380. GENMASK_ULL(28,19) | GENMASK_ULL(13,5);
  381. }
  382. *base = (csbase & base_bits) << addr_shift;
  383. *mask = ~0ULL;
  384. /* poke holes for the csmask */
  385. *mask &= ~(mask_bits << addr_shift);
  386. /* OR them in */
  387. *mask |= (csmask & mask_bits) << addr_shift;
  388. }
  389. #define for_each_chip_select(i, dct, pvt) \
  390. for (i = 0; i < pvt->csels[dct].b_cnt; i++)
  391. #define chip_select_base(i, dct, pvt) \
  392. pvt->csels[dct].csbases[i]
  393. #define for_each_chip_select_mask(i, dct, pvt) \
  394. for (i = 0; i < pvt->csels[dct].m_cnt; i++)
  395. #define for_each_umc(i) \
  396. for (i = 0; i < fam_type->max_mcs; i++)
  397. /*
  398. * @input_addr is an InputAddr associated with the node given by mci. Return the
  399. * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
  400. */
  401. static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
  402. {
  403. struct amd64_pvt *pvt;
  404. int csrow;
  405. u64 base, mask;
  406. pvt = mci->pvt_info;
  407. for_each_chip_select(csrow, 0, pvt) {
  408. if (!csrow_enabled(csrow, 0, pvt))
  409. continue;
  410. get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
  411. mask = ~mask;
  412. if ((input_addr & mask) == (base & mask)) {
  413. edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
  414. (unsigned long)input_addr, csrow,
  415. pvt->mc_node_id);
  416. return csrow;
  417. }
  418. }
  419. edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
  420. (unsigned long)input_addr, pvt->mc_node_id);
  421. return -1;
  422. }
  423. /*
  424. * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094)
  425. * for the node represented by mci. Info is passed back in *hole_base,
  426. * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if
  427. * info is invalid. Info may be invalid for either of the following reasons:
  428. *
  429. * - The revision of the node is not E or greater. In this case, the DRAM Hole
  430. * Address Register does not exist.
  431. *
  432. * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
  433. * indicating that its contents are not valid.
  434. *
  435. * The values passed back in *hole_base, *hole_offset, and *hole_size are
  436. * complete 32-bit values despite the fact that the bitfields in the DHAR
  437. * only represent bits 31-24 of the base and offset values.
  438. */
  439. static int get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
  440. u64 *hole_offset, u64 *hole_size)
  441. {
  442. struct amd64_pvt *pvt = mci->pvt_info;
  443. /* only revE and later have the DRAM Hole Address Register */
  444. if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
  445. edac_dbg(1, " revision %d for node %d does not support DHAR\n",
  446. pvt->ext_model, pvt->mc_node_id);
  447. return 1;
  448. }
  449. /* valid for Fam10h and above */
  450. if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
  451. edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
  452. return 1;
  453. }
  454. if (!dhar_valid(pvt)) {
  455. edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
  456. pvt->mc_node_id);
  457. return 1;
  458. }
  459. /* This node has Memory Hoisting */
  460. /* +------------------+--------------------+--------------------+-----
  461. * | memory | DRAM hole | relocated |
  462. * | [0, (x - 1)] | [x, 0xffffffff] | addresses from |
  463. * | | | DRAM hole |
  464. * | | | [0x100000000, |
  465. * | | | (0x100000000+ |
  466. * | | | (0xffffffff-x))] |
  467. * +------------------+--------------------+--------------------+-----
  468. *
  469. * Above is a diagram of physical memory showing the DRAM hole and the
  470. * relocated addresses from the DRAM hole. As shown, the DRAM hole
  471. * starts at address x (the base address) and extends through address
  472. * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the
  473. * addresses in the hole so that they start at 0x100000000.
  474. */
  475. *hole_base = dhar_base(pvt);
  476. *hole_size = (1ULL << 32) - *hole_base;
  477. *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
  478. : k8_dhar_offset(pvt);
  479. edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
  480. pvt->mc_node_id, (unsigned long)*hole_base,
  481. (unsigned long)*hole_offset, (unsigned long)*hole_size);
  482. return 0;
  483. }
  484. #ifdef CONFIG_EDAC_DEBUG
  485. #define EDAC_DCT_ATTR_SHOW(reg) \
  486. static ssize_t reg##_show(struct device *dev, \
  487. struct device_attribute *mattr, char *data) \
  488. { \
  489. struct mem_ctl_info *mci = to_mci(dev); \
  490. struct amd64_pvt *pvt = mci->pvt_info; \
  491. \
  492. return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
  493. }
  494. EDAC_DCT_ATTR_SHOW(dhar);
  495. EDAC_DCT_ATTR_SHOW(dbam0);
  496. EDAC_DCT_ATTR_SHOW(top_mem);
  497. EDAC_DCT_ATTR_SHOW(top_mem2);
  498. static ssize_t dram_hole_show(struct device *dev, struct device_attribute *mattr,
  499. char *data)
  500. {
  501. struct mem_ctl_info *mci = to_mci(dev);
  502. u64 hole_base = 0;
  503. u64 hole_offset = 0;
  504. u64 hole_size = 0;
  505. get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
  506. return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset,
  507. hole_size);
  508. }
  509. /*
  510. * update NUM_DBG_ATTRS in case you add new members
  511. */
  512. static DEVICE_ATTR(dhar, S_IRUGO, dhar_show, NULL);
  513. static DEVICE_ATTR(dbam, S_IRUGO, dbam0_show, NULL);
  514. static DEVICE_ATTR(topmem, S_IRUGO, top_mem_show, NULL);
  515. static DEVICE_ATTR(topmem2, S_IRUGO, top_mem2_show, NULL);
  516. static DEVICE_ATTR_RO(dram_hole);
  517. static struct attribute *dbg_attrs[] = {
  518. &dev_attr_dhar.attr,
  519. &dev_attr_dbam.attr,
  520. &dev_attr_topmem.attr,
  521. &dev_attr_topmem2.attr,
  522. &dev_attr_dram_hole.attr,
  523. NULL
  524. };
  525. static const struct attribute_group dbg_group = {
  526. .attrs = dbg_attrs,
  527. };
  528. static ssize_t inject_section_show(struct device *dev,
  529. struct device_attribute *mattr, char *buf)
  530. {
  531. struct mem_ctl_info *mci = to_mci(dev);
  532. struct amd64_pvt *pvt = mci->pvt_info;
  533. return sprintf(buf, "0x%x\n", pvt->injection.section);
  534. }
  535. /*
  536. * store error injection section value which refers to one of 4 16-byte sections
  537. * within a 64-byte cacheline
  538. *
  539. * range: 0..3
  540. */
  541. static ssize_t inject_section_store(struct device *dev,
  542. struct device_attribute *mattr,
  543. const char *data, size_t count)
  544. {
  545. struct mem_ctl_info *mci = to_mci(dev);
  546. struct amd64_pvt *pvt = mci->pvt_info;
  547. unsigned long value;
  548. int ret;
  549. ret = kstrtoul(data, 10, &value);
  550. if (ret < 0)
  551. return ret;
  552. if (value > 3) {
  553. amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
  554. return -EINVAL;
  555. }
  556. pvt->injection.section = (u32) value;
  557. return count;
  558. }
  559. static ssize_t inject_word_show(struct device *dev,
  560. struct device_attribute *mattr, char *buf)
  561. {
  562. struct mem_ctl_info *mci = to_mci(dev);
  563. struct amd64_pvt *pvt = mci->pvt_info;
  564. return sprintf(buf, "0x%x\n", pvt->injection.word);
  565. }
  566. /*
  567. * store error injection word value which refers to one of 9 16-bit word of the
  568. * 16-byte (128-bit + ECC bits) section
  569. *
  570. * range: 0..8
  571. */
  572. static ssize_t inject_word_store(struct device *dev,
  573. struct device_attribute *mattr,
  574. const char *data, size_t count)
  575. {
  576. struct mem_ctl_info *mci = to_mci(dev);
  577. struct amd64_pvt *pvt = mci->pvt_info;
  578. unsigned long value;
  579. int ret;
  580. ret = kstrtoul(data, 10, &value);
  581. if (ret < 0)
  582. return ret;
  583. if (value > 8) {
  584. amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
  585. return -EINVAL;
  586. }
  587. pvt->injection.word = (u32) value;
  588. return count;
  589. }
  590. static ssize_t inject_ecc_vector_show(struct device *dev,
  591. struct device_attribute *mattr,
  592. char *buf)
  593. {
  594. struct mem_ctl_info *mci = to_mci(dev);
  595. struct amd64_pvt *pvt = mci->pvt_info;
  596. return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
  597. }
  598. /*
  599. * store 16 bit error injection vector which enables injecting errors to the
  600. * corresponding bit within the error injection word above. When used during a
  601. * DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
  602. */
  603. static ssize_t inject_ecc_vector_store(struct device *dev,
  604. struct device_attribute *mattr,
  605. const char *data, size_t count)
  606. {
  607. struct mem_ctl_info *mci = to_mci(dev);
  608. struct amd64_pvt *pvt = mci->pvt_info;
  609. unsigned long value;
  610. int ret;
  611. ret = kstrtoul(data, 16, &value);
  612. if (ret < 0)
  613. return ret;
  614. if (value & 0xFFFF0000) {
  615. amd64_warn("%s: invalid EccVector: 0x%lx\n", __func__, value);
  616. return -EINVAL;
  617. }
  618. pvt->injection.bit_map = (u32) value;
  619. return count;
  620. }
  621. /*
  622. * Do a DRAM ECC read. Assemble staged values in the pvt area, format into
  623. * fields needed by the injection registers and read the NB Array Data Port.
  624. */
  625. static ssize_t inject_read_store(struct device *dev,
  626. struct device_attribute *mattr,
  627. const char *data, size_t count)
  628. {
  629. struct mem_ctl_info *mci = to_mci(dev);
  630. struct amd64_pvt *pvt = mci->pvt_info;
  631. unsigned long value;
  632. u32 section, word_bits;
  633. int ret;
  634. ret = kstrtoul(data, 10, &value);
  635. if (ret < 0)
  636. return ret;
  637. /* Form value to choose 16-byte section of cacheline */
  638. section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
  639. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
  640. word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
  641. /* Issue 'word' and 'bit' along with the READ request */
  642. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
  643. edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
  644. return count;
  645. }
  646. /*
  647. * Do a DRAM ECC write. Assemble staged values in the pvt area and format into
  648. * fields needed by the injection registers.
  649. */
  650. static ssize_t inject_write_store(struct device *dev,
  651. struct device_attribute *mattr,
  652. const char *data, size_t count)
  653. {
  654. struct mem_ctl_info *mci = to_mci(dev);
  655. struct amd64_pvt *pvt = mci->pvt_info;
  656. u32 section, word_bits, tmp;
  657. unsigned long value;
  658. int ret;
  659. ret = kstrtoul(data, 10, &value);
  660. if (ret < 0)
  661. return ret;
  662. /* Form value to choose 16-byte section of cacheline */
  663. section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
  664. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
  665. word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
  666. pr_notice_once("Don't forget to decrease MCE polling interval in\n"
  667. "/sys/bus/machinecheck/devices/machinecheck<CPUNUM>/check_interval\n"
  668. "so that you can get the error report faster.\n");
  669. on_each_cpu(disable_caches, NULL, 1);
  670. /* Issue 'word' and 'bit' along with the READ request */
  671. amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
  672. retry:
  673. /* wait until injection happens */
  674. amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
  675. if (tmp & F10_NB_ARR_ECC_WR_REQ) {
  676. cpu_relax();
  677. goto retry;
  678. }
  679. on_each_cpu(enable_caches, NULL, 1);
  680. edac_dbg(0, "section=0x%x word_bits=0x%x\n", section, word_bits);
  681. return count;
  682. }
  683. /*
  684. * update NUM_INJ_ATTRS in case you add new members
  685. */
  686. static DEVICE_ATTR_RW(inject_section);
  687. static DEVICE_ATTR_RW(inject_word);
  688. static DEVICE_ATTR_RW(inject_ecc_vector);
  689. static DEVICE_ATTR_WO(inject_write);
  690. static DEVICE_ATTR_WO(inject_read);
  691. static struct attribute *inj_attrs[] = {
  692. &dev_attr_inject_section.attr,
  693. &dev_attr_inject_word.attr,
  694. &dev_attr_inject_ecc_vector.attr,
  695. &dev_attr_inject_write.attr,
  696. &dev_attr_inject_read.attr,
  697. NULL
  698. };
  699. static umode_t inj_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
  700. {
  701. struct device *dev = kobj_to_dev(kobj);
  702. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  703. struct amd64_pvt *pvt = mci->pvt_info;
  704. /* Families which have that injection hw */
  705. if (pvt->fam >= 0x10 && pvt->fam <= 0x16)
  706. return attr->mode;
  707. return 0;
  708. }
  709. static const struct attribute_group inj_group = {
  710. .attrs = inj_attrs,
  711. .is_visible = inj_is_visible,
  712. };
  713. #endif /* CONFIG_EDAC_DEBUG */
  714. /*
  715. * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is
  716. * assumed that sys_addr maps to the node given by mci.
  717. *
  718. * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section
  719. * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a
  720. * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled,
  721. * then it is also involved in translating a SysAddr to a DramAddr. Sections
  722. * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting.
  723. * These parts of the documentation are unclear. I interpret them as follows:
  724. *
  725. * When node n receives a SysAddr, it processes the SysAddr as follows:
  726. *
  727. * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM
  728. * Limit registers for node n. If the SysAddr is not within the range
  729. * specified by the base and limit values, then node n ignores the Sysaddr
  730. * (since it does not map to node n). Otherwise continue to step 2 below.
  731. *
  732. * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is
  733. * disabled so skip to step 3 below. Otherwise see if the SysAddr is within
  734. * the range of relocated addresses (starting at 0x100000000) from the DRAM
  735. * hole. If not, skip to step 3 below. Else get the value of the
  736. * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the
  737. * offset defined by this value from the SysAddr.
  738. *
  739. * 3. Obtain the base address for node n from the DRAMBase field of the DRAM
  740. * Base register for node n. To obtain the DramAddr, subtract the base
  741. * address from the SysAddr, as shown near the start of section 3.4.4 (p.70).
  742. */
  743. static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
  744. {
  745. struct amd64_pvt *pvt = mci->pvt_info;
  746. u64 dram_base, hole_base, hole_offset, hole_size, dram_addr;
  747. int ret;
  748. dram_base = get_dram_base(pvt, pvt->mc_node_id);
  749. ret = get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size);
  750. if (!ret) {
  751. if ((sys_addr >= (1ULL << 32)) &&
  752. (sys_addr < ((1ULL << 32) + hole_size))) {
  753. /* use DHAR to translate SysAddr to DramAddr */
  754. dram_addr = sys_addr - hole_offset;
  755. edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
  756. (unsigned long)sys_addr,
  757. (unsigned long)dram_addr);
  758. return dram_addr;
  759. }
  760. }
  761. /*
  762. * Translate the SysAddr to a DramAddr as shown near the start of
  763. * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8
  764. * only deals with 40-bit values. Therefore we discard bits 63-40 of
  765. * sys_addr below. If bit 39 of sys_addr is 1 then the bits we
  766. * discard are all 1s. Otherwise the bits we discard are all 0s. See
  767. * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture
  768. * Programmer's Manual Volume 1 Application Programming.
  769. */
  770. dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base;
  771. edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
  772. (unsigned long)sys_addr, (unsigned long)dram_addr);
  773. return dram_addr;
  774. }
  775. /*
  776. * @intlv_en is the value of the IntlvEn field from a DRAM Base register
  777. * (section 3.4.4.1). Return the number of bits from a SysAddr that are used
  778. * for node interleaving.
  779. */
  780. static int num_node_interleave_bits(unsigned intlv_en)
  781. {
  782. static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 };
  783. int n;
  784. BUG_ON(intlv_en > 7);
  785. n = intlv_shift_table[intlv_en];
  786. return n;
  787. }
  788. /* Translate the DramAddr given by @dram_addr to an InputAddr. */
  789. static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
  790. {
  791. struct amd64_pvt *pvt;
  792. int intlv_shift;
  793. u64 input_addr;
  794. pvt = mci->pvt_info;
  795. /*
  796. * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E)
  797. * concerning translating a DramAddr to an InputAddr.
  798. */
  799. intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
  800. input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) +
  801. (dram_addr & 0xfff);
  802. edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
  803. intlv_shift, (unsigned long)dram_addr,
  804. (unsigned long)input_addr);
  805. return input_addr;
  806. }
  807. /*
  808. * Translate the SysAddr represented by @sys_addr to an InputAddr. It is
  809. * assumed that @sys_addr maps to the node given by mci.
  810. */
  811. static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
  812. {
  813. u64 input_addr;
  814. input_addr =
  815. dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
  816. edac_dbg(2, "SysAddr 0x%lx translates to InputAddr 0x%lx\n",
  817. (unsigned long)sys_addr, (unsigned long)input_addr);
  818. return input_addr;
  819. }
  820. /* Map the Error address to a PAGE and PAGE OFFSET. */
  821. static inline void error_address_to_page_and_offset(u64 error_address,
  822. struct err_info *err)
  823. {
  824. err->page = (u32) (error_address >> PAGE_SHIFT);
  825. err->offset = ((u32) error_address) & ~PAGE_MASK;
  826. }
  827. /*
  828. * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address
  829. * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers
  830. * of a node that detected an ECC memory error. mci represents the node that
  831. * the error address maps to (possibly different from the node that detected
  832. * the error). Return the number of the csrow that sys_addr maps to, or -1 on
  833. * error.
  834. */
  835. static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
  836. {
  837. int csrow;
  838. csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr));
  839. if (csrow == -1)
  840. amd64_mc_err(mci, "Failed to translate InputAddr to csrow for "
  841. "address 0x%lx\n", (unsigned long)sys_addr);
  842. return csrow;
  843. }
  844. /* Protect the PCI config register pairs used for DF indirect access. */
  845. static DEFINE_MUTEX(df_indirect_mutex);
  846. /*
  847. * Data Fabric Indirect Access uses FICAA/FICAD.
  848. *
  849. * Fabric Indirect Configuration Access Address (FICAA): Constructed based
  850. * on the device's Instance Id and the PCI function and register offset of
  851. * the desired register.
  852. *
  853. * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
  854. * and FICAD HI registers but so far we only need the LO register.
  855. *
  856. * Use Instance Id 0xFF to indicate a broadcast read.
  857. */
  858. #define DF_BROADCAST 0xFF
  859. static int __df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
  860. {
  861. struct pci_dev *F4;
  862. u32 ficaa;
  863. int err = -ENODEV;
  864. if (node >= amd_nb_num())
  865. goto out;
  866. F4 = node_to_amd_nb(node)->link;
  867. if (!F4)
  868. goto out;
  869. ficaa = (instance_id == DF_BROADCAST) ? 0 : 1;
  870. ficaa |= reg & 0x3FC;
  871. ficaa |= (func & 0x7) << 11;
  872. ficaa |= instance_id << 16;
  873. mutex_lock(&df_indirect_mutex);
  874. err = pci_write_config_dword(F4, 0x5C, ficaa);
  875. if (err) {
  876. pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
  877. goto out_unlock;
  878. }
  879. err = pci_read_config_dword(F4, 0x98, lo);
  880. if (err)
  881. pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
  882. out_unlock:
  883. mutex_unlock(&df_indirect_mutex);
  884. out:
  885. return err;
  886. }
  887. static int df_indirect_read_instance(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
  888. {
  889. return __df_indirect_read(node, func, reg, instance_id, lo);
  890. }
  891. static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo)
  892. {
  893. return __df_indirect_read(node, func, reg, DF_BROADCAST, lo);
  894. }
  895. struct addr_ctx {
  896. u64 ret_addr;
  897. u32 tmp;
  898. u16 nid;
  899. u8 inst_id;
  900. };
  901. static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
  902. {
  903. u64 dram_base_addr, dram_limit_addr, dram_hole_base;
  904. u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
  905. u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
  906. u8 intlv_addr_sel, intlv_addr_bit;
  907. u8 num_intlv_bits, hashed_bit;
  908. u8 lgcy_mmio_hole_en, base = 0;
  909. u8 cs_mask, cs_id = 0;
  910. bool hash_enabled = false;
  911. struct addr_ctx ctx;
  912. memset(&ctx, 0, sizeof(ctx));
  913. /* Start from the normalized address */
  914. ctx.ret_addr = norm_addr;
  915. ctx.nid = nid;
  916. ctx.inst_id = umc;
  917. /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
  918. if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))
  919. goto out_err;
  920. /* Remove HiAddrOffset from normalized address, if enabled: */
  921. if (ctx.tmp & BIT(0)) {
  922. u64 hi_addr_offset = (ctx.tmp & GENMASK_ULL(31, 20)) << 8;
  923. if (norm_addr >= hi_addr_offset) {
  924. ctx.ret_addr -= hi_addr_offset;
  925. base = 1;
  926. }
  927. }
  928. /* Read D18F0x110 (DramBaseAddress). */
  929. if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp))
  930. goto out_err;
  931. /* Check if address range is valid. */
  932. if (!(ctx.tmp & BIT(0))) {
  933. pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
  934. __func__, ctx.tmp);
  935. goto out_err;
  936. }
  937. lgcy_mmio_hole_en = ctx.tmp & BIT(1);
  938. intlv_num_chan = (ctx.tmp >> 4) & 0xF;
  939. intlv_addr_sel = (ctx.tmp >> 8) & 0x7;
  940. dram_base_addr = (ctx.tmp & GENMASK_ULL(31, 12)) << 16;
  941. /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
  942. if (intlv_addr_sel > 3) {
  943. pr_err("%s: Invalid interleave address select %d.\n",
  944. __func__, intlv_addr_sel);
  945. goto out_err;
  946. }
  947. /* Read D18F0x114 (DramLimitAddress). */
  948. if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))
  949. goto out_err;
  950. intlv_num_sockets = (ctx.tmp >> 8) & 0x1;
  951. intlv_num_dies = (ctx.tmp >> 10) & 0x3;
  952. dram_limit_addr = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
  953. intlv_addr_bit = intlv_addr_sel + 8;
  954. /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
  955. switch (intlv_num_chan) {
  956. case 0: intlv_num_chan = 0; break;
  957. case 1: intlv_num_chan = 1; break;
  958. case 3: intlv_num_chan = 2; break;
  959. case 5: intlv_num_chan = 3; break;
  960. case 7: intlv_num_chan = 4; break;
  961. case 8: intlv_num_chan = 1;
  962. hash_enabled = true;
  963. break;
  964. default:
  965. pr_err("%s: Invalid number of interleaved channels %d.\n",
  966. __func__, intlv_num_chan);
  967. goto out_err;
  968. }
  969. num_intlv_bits = intlv_num_chan;
  970. if (intlv_num_dies > 2) {
  971. pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
  972. __func__, intlv_num_dies);
  973. goto out_err;
  974. }
  975. num_intlv_bits += intlv_num_dies;
  976. /* Add a bit if sockets are interleaved. */
  977. num_intlv_bits += intlv_num_sockets;
  978. /* Assert num_intlv_bits <= 4 */
  979. if (num_intlv_bits > 4) {
  980. pr_err("%s: Invalid interleave bits %d.\n",
  981. __func__, num_intlv_bits);
  982. goto out_err;
  983. }
  984. if (num_intlv_bits > 0) {
  985. u64 temp_addr_x, temp_addr_i, temp_addr_y;
  986. u8 die_id_bit, sock_id_bit, cs_fabric_id;
  987. /*
  988. * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
  989. * This is the fabric id for this coherent slave. Use
  990. * umc/channel# as instance id of the coherent slave
  991. * for FICAA.
  992. */
  993. if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))
  994. goto out_err;
  995. cs_fabric_id = (ctx.tmp >> 8) & 0xFF;
  996. die_id_bit = 0;
  997. /* If interleaved over more than 1 channel: */
  998. if (intlv_num_chan) {
  999. die_id_bit = intlv_num_chan;
  1000. cs_mask = (1 << die_id_bit) - 1;
  1001. cs_id = cs_fabric_id & cs_mask;
  1002. }
  1003. sock_id_bit = die_id_bit;
  1004. /* Read D18F1x208 (SystemFabricIdMask). */
  1005. if (intlv_num_dies || intlv_num_sockets)
  1006. if (df_indirect_read_broadcast(nid, 1, 0x208, &ctx.tmp))
  1007. goto out_err;
  1008. /* If interleaved over more than 1 die. */
  1009. if (intlv_num_dies) {
  1010. sock_id_bit = die_id_bit + intlv_num_dies;
  1011. die_id_shift = (ctx.tmp >> 24) & 0xF;
  1012. die_id_mask = (ctx.tmp >> 8) & 0xFF;
  1013. cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
  1014. }
  1015. /* If interleaved over more than 1 socket. */
  1016. if (intlv_num_sockets) {
  1017. socket_id_shift = (ctx.tmp >> 28) & 0xF;
  1018. socket_id_mask = (ctx.tmp >> 16) & 0xFF;
  1019. cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
  1020. }
  1021. /*
  1022. * The pre-interleaved address consists of XXXXXXIIIYYYYY
  1023. * where III is the ID for this CS, and XXXXXXYYYYY are the
  1024. * address bits from the post-interleaved address.
  1025. * "num_intlv_bits" has been calculated to tell us how many "I"
  1026. * bits there are. "intlv_addr_bit" tells us how many "Y" bits
  1027. * there are (where "I" starts).
  1028. */
  1029. temp_addr_y = ctx.ret_addr & GENMASK_ULL(intlv_addr_bit - 1, 0);
  1030. temp_addr_i = (cs_id << intlv_addr_bit);
  1031. temp_addr_x = (ctx.ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
  1032. ctx.ret_addr = temp_addr_x | temp_addr_i | temp_addr_y;
  1033. }
  1034. /* Add dram base address */
  1035. ctx.ret_addr += dram_base_addr;
  1036. /* If legacy MMIO hole enabled */
  1037. if (lgcy_mmio_hole_en) {
  1038. if (df_indirect_read_broadcast(nid, 0, 0x104, &ctx.tmp))
  1039. goto out_err;
  1040. dram_hole_base = ctx.tmp & GENMASK(31, 24);
  1041. if (ctx.ret_addr >= dram_hole_base)
  1042. ctx.ret_addr += (BIT_ULL(32) - dram_hole_base);
  1043. }
  1044. if (hash_enabled) {
  1045. /* Save some parentheses and grab ls-bit at the end. */
  1046. hashed_bit = (ctx.ret_addr >> 12) ^
  1047. (ctx.ret_addr >> 18) ^
  1048. (ctx.ret_addr >> 21) ^
  1049. (ctx.ret_addr >> 30) ^
  1050. cs_id;
  1051. hashed_bit &= BIT(0);
  1052. if (hashed_bit != ((ctx.ret_addr >> intlv_addr_bit) & BIT(0)))
  1053. ctx.ret_addr ^= BIT(intlv_addr_bit);
  1054. }
  1055. /* Is calculated system address is above DRAM limit address? */
  1056. if (ctx.ret_addr > dram_limit_addr)
  1057. goto out_err;
  1058. *sys_addr = ctx.ret_addr;
  1059. return 0;
  1060. out_err:
  1061. return -EINVAL;
  1062. }
  1063. static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
  1064. /*
  1065. * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
  1066. * are ECC capable.
  1067. */
  1068. static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
  1069. {
  1070. unsigned long edac_cap = EDAC_FLAG_NONE;
  1071. u8 bit;
  1072. if (pvt->umc) {
  1073. u8 i, umc_en_mask = 0, dimm_ecc_en_mask = 0;
  1074. for_each_umc(i) {
  1075. if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
  1076. continue;
  1077. umc_en_mask |= BIT(i);
  1078. /* UMC Configuration bit 12 (DimmEccEn) */
  1079. if (pvt->umc[i].umc_cfg & BIT(12))
  1080. dimm_ecc_en_mask |= BIT(i);
  1081. }
  1082. if (umc_en_mask == dimm_ecc_en_mask)
  1083. edac_cap = EDAC_FLAG_SECDED;
  1084. } else {
  1085. bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
  1086. ? 19
  1087. : 17;
  1088. if (pvt->dclr0 & BIT(bit))
  1089. edac_cap = EDAC_FLAG_SECDED;
  1090. }
  1091. return edac_cap;
  1092. }
  1093. static void debug_display_dimm_sizes(struct amd64_pvt *, u8);
  1094. static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
  1095. {
  1096. edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
  1097. if (pvt->dram_type == MEM_LRDDR3) {
  1098. u32 dcsm = pvt->csels[chan].csmasks[0];
  1099. /*
  1100. * It's assumed all LRDIMMs in a DCT are going to be of
  1101. * same 'type' until proven otherwise. So, use a cs
  1102. * value of '0' here to get dcsm value.
  1103. */
  1104. edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));
  1105. }
  1106. edac_dbg(1, "All DIMMs support ECC:%s\n",
  1107. (dclr & BIT(19)) ? "yes" : "no");
  1108. edac_dbg(1, " PAR/ERR parity: %s\n",
  1109. (dclr & BIT(8)) ? "enabled" : "disabled");
  1110. if (pvt->fam == 0x10)
  1111. edac_dbg(1, " DCT 128bit mode width: %s\n",
  1112. (dclr & BIT(11)) ? "128b" : "64b");
  1113. edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
  1114. (dclr & BIT(12)) ? "yes" : "no",
  1115. (dclr & BIT(13)) ? "yes" : "no",
  1116. (dclr & BIT(14)) ? "yes" : "no",
  1117. (dclr & BIT(15)) ? "yes" : "no");
  1118. }
  1119. #define CS_EVEN_PRIMARY BIT(0)
  1120. #define CS_ODD_PRIMARY BIT(1)
  1121. #define CS_EVEN_SECONDARY BIT(2)
  1122. #define CS_ODD_SECONDARY BIT(3)
  1123. #define CS_3R_INTERLEAVE BIT(4)
  1124. #define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY)
  1125. #define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY)
  1126. static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
  1127. {
  1128. u8 base, count = 0;
  1129. int cs_mode = 0;
  1130. if (csrow_enabled(2 * dimm, ctrl, pvt))
  1131. cs_mode |= CS_EVEN_PRIMARY;
  1132. if (csrow_enabled(2 * dimm + 1, ctrl, pvt))
  1133. cs_mode |= CS_ODD_PRIMARY;
  1134. /* Asymmetric dual-rank DIMM support. */
  1135. if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
  1136. cs_mode |= CS_ODD_SECONDARY;
  1137. /*
  1138. * 3 Rank inteleaving support.
  1139. * There should be only three bases enabled and their two masks should
  1140. * be equal.
  1141. */
  1142. for_each_chip_select(base, ctrl, pvt)
  1143. count += csrow_enabled(base, ctrl, pvt);
  1144. if (count == 3 &&
  1145. pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) {
  1146. edac_dbg(1, "3R interleaving in use.\n");
  1147. cs_mode |= CS_3R_INTERLEAVE;
  1148. }
  1149. return cs_mode;
  1150. }
  1151. static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
  1152. {
  1153. int dimm, size0, size1, cs0, cs1, cs_mode;
  1154. edac_printk(KERN_DEBUG, EDAC_MC, "UMC%d chip selects:\n", ctrl);
  1155. for (dimm = 0; dimm < 2; dimm++) {
  1156. cs0 = dimm * 2;
  1157. cs1 = dimm * 2 + 1;
  1158. cs_mode = f17_get_cs_mode(dimm, ctrl, pvt);
  1159. size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0);
  1160. size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1);
  1161. amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
  1162. cs0, size0,
  1163. cs1, size1);
  1164. }
  1165. }
  1166. static void __dump_misc_regs_df(struct amd64_pvt *pvt)
  1167. {
  1168. struct amd64_umc *umc;
  1169. u32 i, tmp, umc_base;
  1170. for_each_umc(i) {
  1171. umc_base = get_umc_base(i);
  1172. umc = &pvt->umc[i];
  1173. edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
  1174. edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
  1175. edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
  1176. edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
  1177. amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
  1178. edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);
  1179. amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
  1180. edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
  1181. edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
  1182. edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
  1183. i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no",
  1184. (umc->umc_cap_hi & BIT(31)) ? "yes" : "no");
  1185. edac_dbg(1, "UMC%d All DIMMs support ECC: %s\n",
  1186. i, (umc->umc_cfg & BIT(12)) ? "yes" : "no");
  1187. edac_dbg(1, "UMC%d x4 DIMMs present: %s\n",
  1188. i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no");
  1189. edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
  1190. i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
  1191. if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {
  1192. amd_smn_read(pvt->mc_node_id,
  1193. umc_base + get_umc_reg(UMCCH_ADDR_CFG),
  1194. &tmp);
  1195. edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
  1196. i, 1 << ((tmp >> 4) & 0x3));
  1197. }
  1198. debug_display_dimm_sizes_df(pvt, i);
  1199. }
  1200. edac_dbg(1, "F0x104 (DRAM Hole Address): 0x%08x, base: 0x%08x\n",
  1201. pvt->dhar, dhar_base(pvt));
  1202. }
  1203. /* Display and decode various NB registers for debug purposes. */
  1204. static void __dump_misc_regs(struct amd64_pvt *pvt)
  1205. {
  1206. edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
  1207. edac_dbg(1, " NB two channel DRAM capable: %s\n",
  1208. (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
  1209. edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
  1210. (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
  1211. (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
  1212. debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
  1213. edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
  1214. edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
  1215. pvt->dhar, dhar_base(pvt),
  1216. (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
  1217. : f10_dhar_offset(pvt));
  1218. debug_display_dimm_sizes(pvt, 0);
  1219. /* everything below this point is Fam10h and above */
  1220. if (pvt->fam == 0xf)
  1221. return;
  1222. debug_display_dimm_sizes(pvt, 1);
  1223. /* Only if NOT ganged does dclr1 have valid info */
  1224. if (!dct_ganging_enabled(pvt))
  1225. debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
  1226. }
  1227. /* Display and decode various NB registers for debug purposes. */
  1228. static void dump_misc_regs(struct amd64_pvt *pvt)
  1229. {
  1230. if (pvt->umc)
  1231. __dump_misc_regs_df(pvt);
  1232. else
  1233. __dump_misc_regs(pvt);
  1234. edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
  1235. amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
  1236. }
  1237. /*
  1238. * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60]
  1239. */
  1240. static void prep_chip_selects(struct amd64_pvt *pvt)
  1241. {
  1242. if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
  1243. pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
  1244. pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
  1245. } else if (pvt->fam == 0x15 && pvt->model == 0x30) {
  1246. pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
  1247. pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
  1248. } else if (pvt->fam >= 0x17) {
  1249. int umc;
  1250. for_each_umc(umc) {
  1251. pvt->csels[umc].b_cnt = 4;
  1252. pvt->csels[umc].m_cnt = fam_type->flags.zn_regs_v2 ? 4 : 2;
  1253. }
  1254. } else {
  1255. pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
  1256. pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
  1257. }
  1258. }
  1259. static void read_umc_base_mask(struct amd64_pvt *pvt)
  1260. {
  1261. u32 umc_base_reg, umc_base_reg_sec;
  1262. u32 umc_mask_reg, umc_mask_reg_sec;
  1263. u32 base_reg, base_reg_sec;
  1264. u32 mask_reg, mask_reg_sec;
  1265. u32 *base, *base_sec;
  1266. u32 *mask, *mask_sec;
  1267. int cs, umc;
  1268. for_each_umc(umc) {
  1269. umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
  1270. umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC;
  1271. for_each_chip_select(cs, umc, pvt) {
  1272. base = &pvt->csels[umc].csbases[cs];
  1273. base_sec = &pvt->csels[umc].csbases_sec[cs];
  1274. base_reg = umc_base_reg + (cs * 4);
  1275. base_reg_sec = umc_base_reg_sec + (cs * 4);
  1276. if (!amd_smn_read(pvt->mc_node_id, base_reg, base))
  1277. edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
  1278. umc, cs, *base, base_reg);
  1279. if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec))
  1280. edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",
  1281. umc, cs, *base_sec, base_reg_sec);
  1282. }
  1283. umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
  1284. umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(UMCCH_ADDR_MASK_SEC);
  1285. for_each_chip_select_mask(cs, umc, pvt) {
  1286. mask = &pvt->csels[umc].csmasks[cs];
  1287. mask_sec = &pvt->csels[umc].csmasks_sec[cs];
  1288. mask_reg = umc_mask_reg + (cs * 4);
  1289. mask_reg_sec = umc_mask_reg_sec + (cs * 4);
  1290. if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask))
  1291. edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
  1292. umc, cs, *mask, mask_reg);
  1293. if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec))
  1294. edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",
  1295. umc, cs, *mask_sec, mask_reg_sec);
  1296. }
  1297. }
  1298. }
  1299. /*
  1300. * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
  1301. */
  1302. static void read_dct_base_mask(struct amd64_pvt *pvt)
  1303. {
  1304. int cs;
  1305. prep_chip_selects(pvt);
  1306. if (pvt->umc)
  1307. return read_umc_base_mask(pvt);
  1308. for_each_chip_select(cs, 0, pvt) {
  1309. int reg0 = DCSB0 + (cs * 4);
  1310. int reg1 = DCSB1 + (cs * 4);
  1311. u32 *base0 = &pvt->csels[0].csbases[cs];
  1312. u32 *base1 = &pvt->csels[1].csbases[cs];
  1313. if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
  1314. edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
  1315. cs, *base0, reg0);
  1316. if (pvt->fam == 0xf)
  1317. continue;
  1318. if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
  1319. edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
  1320. cs, *base1, (pvt->fam == 0x10) ? reg1
  1321. : reg0);
  1322. }
  1323. for_each_chip_select_mask(cs, 0, pvt) {
  1324. int reg0 = DCSM0 + (cs * 4);
  1325. int reg1 = DCSM1 + (cs * 4);
  1326. u32 *mask0 = &pvt->csels[0].csmasks[cs];
  1327. u32 *mask1 = &pvt->csels[1].csmasks[cs];
  1328. if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
  1329. edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
  1330. cs, *mask0, reg0);
  1331. if (pvt->fam == 0xf)
  1332. continue;
  1333. if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
  1334. edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
  1335. cs, *mask1, (pvt->fam == 0x10) ? reg1
  1336. : reg0);
  1337. }
  1338. }
  1339. static void determine_memory_type_df(struct amd64_pvt *pvt)
  1340. {
  1341. struct amd64_umc *umc;
  1342. u32 i;
  1343. for_each_umc(i) {
  1344. umc = &pvt->umc[i];
  1345. if (!(umc->sdp_ctrl & UMC_SDP_INIT)) {
  1346. umc->dram_type = MEM_EMPTY;
  1347. continue;
  1348. }
  1349. /*
  1350. * Check if the system supports the "DDR Type" field in UMC Config
  1351. * and has DDR5 DIMMs in use.
  1352. */
  1353. if (fam_type->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
  1354. if (umc->dimm_cfg & BIT(5))
  1355. umc->dram_type = MEM_LRDDR5;
  1356. else if (umc->dimm_cfg & BIT(4))
  1357. umc->dram_type = MEM_RDDR5;
  1358. else
  1359. umc->dram_type = MEM_DDR5;
  1360. } else {
  1361. if (umc->dimm_cfg & BIT(5))
  1362. umc->dram_type = MEM_LRDDR4;
  1363. else if (umc->dimm_cfg & BIT(4))
  1364. umc->dram_type = MEM_RDDR4;
  1365. else
  1366. umc->dram_type = MEM_DDR4;
  1367. }
  1368. edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);
  1369. }
  1370. }
  1371. static void determine_memory_type(struct amd64_pvt *pvt)
  1372. {
  1373. u32 dram_ctrl, dcsm;
  1374. if (pvt->umc)
  1375. return determine_memory_type_df(pvt);
  1376. switch (pvt->fam) {
  1377. case 0xf:
  1378. if (pvt->ext_model >= K8_REV_F)
  1379. goto ddr3;
  1380. pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
  1381. return;
  1382. case 0x10:
  1383. if (pvt->dchr0 & DDR3_MODE)
  1384. goto ddr3;
  1385. pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
  1386. return;
  1387. case 0x15:
  1388. if (pvt->model < 0x60)
  1389. goto ddr3;
  1390. /*
  1391. * Model 0x60h needs special handling:
  1392. *
  1393. * We use a Chip Select value of '0' to obtain dcsm.
  1394. * Theoretically, it is possible to populate LRDIMMs of different
  1395. * 'Rank' value on a DCT. But this is not the common case. So,
  1396. * it's reasonable to assume all DIMMs are going to be of same
  1397. * 'type' until proven otherwise.
  1398. */
  1399. amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
  1400. dcsm = pvt->csels[0].csmasks[0];
  1401. if (((dram_ctrl >> 8) & 0x7) == 0x2)
  1402. pvt->dram_type = MEM_DDR4;
  1403. else if (pvt->dclr0 & BIT(16))
  1404. pvt->dram_type = MEM_DDR3;
  1405. else if (dcsm & 0x3)
  1406. pvt->dram_type = MEM_LRDDR3;
  1407. else
  1408. pvt->dram_type = MEM_RDDR3;
  1409. return;
  1410. case 0x16:
  1411. goto ddr3;
  1412. default:
  1413. WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
  1414. pvt->dram_type = MEM_EMPTY;
  1415. }
  1416. return;
  1417. ddr3:
  1418. pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
  1419. }
  1420. /* Get the number of DCT channels the memory controller is using. */
  1421. static int k8_early_channel_count(struct amd64_pvt *pvt)
  1422. {
  1423. int flag;
  1424. if (pvt->ext_model >= K8_REV_F)
  1425. /* RevF (NPT) and later */
  1426. flag = pvt->dclr0 & WIDTH_128;
  1427. else
  1428. /* RevE and earlier */
  1429. flag = pvt->dclr0 & REVE_WIDTH_128;
  1430. /* not used */
  1431. pvt->dclr1 = 0;
  1432. return (flag) ? 2 : 1;
  1433. }
  1434. /* On F10h and later ErrAddr is MC4_ADDR[47:1] */
  1435. static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
  1436. {
  1437. u16 mce_nid = topology_die_id(m->extcpu);
  1438. struct mem_ctl_info *mci;
  1439. u8 start_bit = 1;
  1440. u8 end_bit = 47;
  1441. u64 addr;
  1442. mci = edac_mc_find(mce_nid);
  1443. if (!mci)
  1444. return 0;
  1445. pvt = mci->pvt_info;
  1446. if (pvt->fam == 0xf) {
  1447. start_bit = 3;
  1448. end_bit = 39;
  1449. }
  1450. addr = m->addr & GENMASK_ULL(end_bit, start_bit);
  1451. /*
  1452. * Erratum 637 workaround
  1453. */
  1454. if (pvt->fam == 0x15) {
  1455. u64 cc6_base, tmp_addr;
  1456. u32 tmp;
  1457. u8 intlv_en;
  1458. if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7)
  1459. return addr;
  1460. amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
  1461. intlv_en = tmp >> 21 & 0x7;
  1462. /* add [47:27] + 3 trailing bits */
  1463. cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3;
  1464. /* reverse and add DramIntlvEn */
  1465. cc6_base |= intlv_en ^ 0x7;
  1466. /* pin at [47:24] */
  1467. cc6_base <<= 24;
  1468. if (!intlv_en)
  1469. return cc6_base | (addr & GENMASK_ULL(23, 0));
  1470. amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
  1471. /* faster log2 */
  1472. tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1);
  1473. /* OR DramIntlvSel into bits [14:12] */
  1474. tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9;
  1475. /* add remaining [11:0] bits from original MC4_ADDR */
  1476. tmp_addr |= addr & GENMASK_ULL(11, 0);
  1477. return cc6_base | tmp_addr;
  1478. }
  1479. return addr;
  1480. }
  1481. static struct pci_dev *pci_get_related_function(unsigned int vendor,
  1482. unsigned int device,
  1483. struct pci_dev *related)
  1484. {
  1485. struct pci_dev *dev = NULL;
  1486. while ((dev = pci_get_device(vendor, device, dev))) {
  1487. if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) &&
  1488. (dev->bus->number == related->bus->number) &&
  1489. (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn)))
  1490. break;
  1491. }
  1492. return dev;
  1493. }
  1494. static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
  1495. {
  1496. struct amd_northbridge *nb;
  1497. struct pci_dev *f1 = NULL;
  1498. unsigned int pci_func;
  1499. int off = range << 3;
  1500. u32 llim;
  1501. amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo);
  1502. amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
  1503. if (pvt->fam == 0xf)
  1504. return;
  1505. if (!dram_rw(pvt, range))
  1506. return;
  1507. amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi);
  1508. amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
  1509. /* F15h: factor in CC6 save area by reading dst node's limit reg */
  1510. if (pvt->fam != 0x15)
  1511. return;
  1512. nb = node_to_amd_nb(dram_dst_node(pvt, range));
  1513. if (WARN_ON(!nb))
  1514. return;
  1515. if (pvt->model == 0x60)
  1516. pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1;
  1517. else if (pvt->model == 0x30)
  1518. pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1;
  1519. else
  1520. pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1;
  1521. f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc);
  1522. if (WARN_ON(!f1))
  1523. return;
  1524. amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim);
  1525. pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
  1526. /* {[39:27],111b} */
  1527. pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
  1528. pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
  1529. /* [47:40] */
  1530. pvt->ranges[range].lim.hi |= llim >> 13;
  1531. pci_dev_put(f1);
  1532. }
  1533. static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
  1534. struct err_info *err)
  1535. {
  1536. struct amd64_pvt *pvt = mci->pvt_info;
  1537. error_address_to_page_and_offset(sys_addr, err);
  1538. /*
  1539. * Find out which node the error address belongs to. This may be
  1540. * different from the node that detected the error.
  1541. */
  1542. err->src_mci = find_mc_by_sys_addr(mci, sys_addr);
  1543. if (!err->src_mci) {
  1544. amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n",
  1545. (unsigned long)sys_addr);
  1546. err->err_code = ERR_NODE;
  1547. return;
  1548. }
  1549. /* Now map the sys_addr to a CSROW */
  1550. err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr);
  1551. if (err->csrow < 0) {
  1552. err->err_code = ERR_CSROW;
  1553. return;
  1554. }
  1555. /* CHIPKILL enabled */
  1556. if (pvt->nbcfg & NBCFG_CHIPKILL) {
  1557. err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
  1558. if (err->channel < 0) {
  1559. /*
  1560. * Syndrome didn't map, so we don't know which of the
  1561. * 2 DIMMs is in error. So we need to ID 'both' of them
  1562. * as suspect.
  1563. */
  1564. amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - "
  1565. "possible error reporting race\n",
  1566. err->syndrome);
  1567. err->err_code = ERR_CHANNEL;
  1568. return;
  1569. }
  1570. } else {
  1571. /*
  1572. * non-chipkill ecc mode
  1573. *
  1574. * The k8 documentation is unclear about how to determine the
  1575. * channel number when using non-chipkill memory. This method
  1576. * was obtained from email communication with someone at AMD.
  1577. * (Wish the email was placed in this comment - norsk)
  1578. */
  1579. err->channel = ((sys_addr & BIT(3)) != 0);
  1580. }
  1581. }
  1582. static int ddr2_cs_size(unsigned i, bool dct_width)
  1583. {
  1584. unsigned shift = 0;
  1585. if (i <= 2)
  1586. shift = i;
  1587. else if (!(i & 0x1))
  1588. shift = i >> 1;
  1589. else
  1590. shift = (i + 1) >> 1;
  1591. return 128 << (shift + !!dct_width);
  1592. }
  1593. static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
  1594. unsigned cs_mode, int cs_mask_nr)
  1595. {
  1596. u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
  1597. if (pvt->ext_model >= K8_REV_F) {
  1598. WARN_ON(cs_mode > 11);
  1599. return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
  1600. }
  1601. else if (pvt->ext_model >= K8_REV_D) {
  1602. unsigned diff;
  1603. WARN_ON(cs_mode > 10);
  1604. /*
  1605. * the below calculation, besides trying to win an obfuscated C
  1606. * contest, maps cs_mode values to DIMM chip select sizes. The
  1607. * mappings are:
  1608. *
  1609. * cs_mode CS size (mb)
  1610. * ======= ============
  1611. * 0 32
  1612. * 1 64
  1613. * 2 128
  1614. * 3 128
  1615. * 4 256
  1616. * 5 512
  1617. * 6 256
  1618. * 7 512
  1619. * 8 1024
  1620. * 9 1024
  1621. * 10 2048
  1622. *
  1623. * Basically, it calculates a value with which to shift the
  1624. * smallest CS size of 32MB.
  1625. *
  1626. * ddr[23]_cs_size have a similar purpose.
  1627. */
  1628. diff = cs_mode/3 + (unsigned)(cs_mode > 5);
  1629. return 32 << (cs_mode - diff);
  1630. }
  1631. else {
  1632. WARN_ON(cs_mode > 6);
  1633. return 32 << cs_mode;
  1634. }
  1635. }
  1636. /*
  1637. * Get the number of DCT channels in use.
  1638. *
  1639. * Return:
  1640. * number of Memory Channels in operation
  1641. * Pass back:
  1642. * contents of the DCL0_LOW register
  1643. */
  1644. static int f1x_early_channel_count(struct amd64_pvt *pvt)
  1645. {
  1646. int i, j, channels = 0;
  1647. /* On F10h, if we are in 128 bit mode, then we are using 2 channels */
  1648. if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))
  1649. return 2;
  1650. /*
  1651. * Need to check if in unganged mode: In such, there are 2 channels,
  1652. * but they are not in 128 bit mode and thus the above 'dclr0' status
  1653. * bit will be OFF.
  1654. *
  1655. * Need to check DCT0[0] and DCT1[0] to see if only one of them has
  1656. * their CSEnable bit on. If so, then SINGLE DIMM case.
  1657. */
  1658. edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
  1659. /*
  1660. * Check DRAM Bank Address Mapping values for each DIMM to see if there
  1661. * is more than just one DIMM present in unganged mode. Need to check
  1662. * both controllers since DIMMs can be placed in either one.
  1663. */
  1664. for (i = 0; i < 2; i++) {
  1665. u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
  1666. for (j = 0; j < 4; j++) {
  1667. if (DBAM_DIMM(j, dbam) > 0) {
  1668. channels++;
  1669. break;
  1670. }
  1671. }
  1672. }
  1673. if (channels > 2)
  1674. channels = 2;
  1675. amd64_info("MCT channel count: %d\n", channels);
  1676. return channels;
  1677. }
  1678. static int f17_early_channel_count(struct amd64_pvt *pvt)
  1679. {
  1680. int i, channels = 0;
  1681. /* SDP Control bit 31 (SdpInit) is clear for unused UMC channels */
  1682. for_each_umc(i)
  1683. channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);
  1684. amd64_info("MCT channel count: %d\n", channels);
  1685. return channels;
  1686. }
  1687. static int ddr3_cs_size(unsigned i, bool dct_width)
  1688. {
  1689. unsigned shift = 0;
  1690. int cs_size = 0;
  1691. if (i == 0 || i == 3 || i == 4)
  1692. cs_size = -1;
  1693. else if (i <= 2)
  1694. shift = i;
  1695. else if (i == 12)
  1696. shift = 7;
  1697. else if (!(i & 0x1))
  1698. shift = i >> 1;
  1699. else
  1700. shift = (i + 1) >> 1;
  1701. if (cs_size != -1)
  1702. cs_size = (128 * (1 << !!dct_width)) << shift;
  1703. return cs_size;
  1704. }
  1705. static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply)
  1706. {
  1707. unsigned shift = 0;
  1708. int cs_size = 0;
  1709. if (i < 4 || i == 6)
  1710. cs_size = -1;
  1711. else if (i == 12)
  1712. shift = 7;
  1713. else if (!(i & 0x1))
  1714. shift = i >> 1;
  1715. else
  1716. shift = (i + 1) >> 1;
  1717. if (cs_size != -1)
  1718. cs_size = rank_multiply * (128 << shift);
  1719. return cs_size;
  1720. }
  1721. static int ddr4_cs_size(unsigned i)
  1722. {
  1723. int cs_size = 0;
  1724. if (i == 0)
  1725. cs_size = -1;
  1726. else if (i == 1)
  1727. cs_size = 1024;
  1728. else
  1729. /* Min cs_size = 1G */
  1730. cs_size = 1024 * (1 << (i >> 1));
  1731. return cs_size;
  1732. }
  1733. static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
  1734. unsigned cs_mode, int cs_mask_nr)
  1735. {
  1736. u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
  1737. WARN_ON(cs_mode > 11);
  1738. if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
  1739. return ddr3_cs_size(cs_mode, dclr & WIDTH_128);
  1740. else
  1741. return ddr2_cs_size(cs_mode, dclr & WIDTH_128);
  1742. }
  1743. /*
  1744. * F15h supports only 64bit DCT interfaces
  1745. */
  1746. static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
  1747. unsigned cs_mode, int cs_mask_nr)
  1748. {
  1749. WARN_ON(cs_mode > 12);
  1750. return ddr3_cs_size(cs_mode, false);
  1751. }
  1752. /* F15h M60h supports DDR4 mapping as well.. */
  1753. static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
  1754. unsigned cs_mode, int cs_mask_nr)
  1755. {
  1756. int cs_size;
  1757. u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];
  1758. WARN_ON(cs_mode > 12);
  1759. if (pvt->dram_type == MEM_DDR4) {
  1760. if (cs_mode > 9)
  1761. return -1;
  1762. cs_size = ddr4_cs_size(cs_mode);
  1763. } else if (pvt->dram_type == MEM_LRDDR3) {
  1764. unsigned rank_multiply = dcsm & 0xf;
  1765. if (rank_multiply == 3)
  1766. rank_multiply = 4;
  1767. cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply);
  1768. } else {
  1769. /* Minimum cs size is 512mb for F15hM60h*/
  1770. if (cs_mode == 0x1)
  1771. return -1;
  1772. cs_size = ddr3_cs_size(cs_mode, false);
  1773. }
  1774. return cs_size;
  1775. }
  1776. /*
  1777. * F16h and F15h model 30h have only limited cs_modes.
  1778. */
  1779. static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
  1780. unsigned cs_mode, int cs_mask_nr)
  1781. {
  1782. WARN_ON(cs_mode > 12);
  1783. if (cs_mode == 6 || cs_mode == 8 ||
  1784. cs_mode == 9 || cs_mode == 12)
  1785. return -1;
  1786. else
  1787. return ddr3_cs_size(cs_mode, false);
  1788. }
  1789. static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
  1790. unsigned int cs_mode, int csrow_nr)
  1791. {
  1792. u32 addr_mask_orig, addr_mask_deinterleaved;
  1793. u32 msb, weight, num_zero_bits;
  1794. int cs_mask_nr = csrow_nr;
  1795. int dimm, size = 0;
  1796. /* No Chip Selects are enabled. */
  1797. if (!cs_mode)
  1798. return size;
  1799. /* Requested size of an even CS but none are enabled. */
  1800. if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1))
  1801. return size;
  1802. /* Requested size of an odd CS but none are enabled. */
  1803. if (!(cs_mode & CS_ODD) && (csrow_nr & 1))
  1804. return size;
  1805. /*
  1806. * Family 17h introduced systems with one mask per DIMM,
  1807. * and two Chip Selects per DIMM.
  1808. *
  1809. * CS0 and CS1 -> MASK0 / DIMM0
  1810. * CS2 and CS3 -> MASK1 / DIMM1
  1811. *
  1812. * Family 19h Model 10h introduced systems with one mask per Chip Select,
  1813. * and two Chip Selects per DIMM.
  1814. *
  1815. * CS0 -> MASK0 -> DIMM0
  1816. * CS1 -> MASK1 -> DIMM0
  1817. * CS2 -> MASK2 -> DIMM1
  1818. * CS3 -> MASK3 -> DIMM1
  1819. *
  1820. * Keep the mask number equal to the Chip Select number for newer systems,
  1821. * and shift the mask number for older systems.
  1822. */
  1823. dimm = csrow_nr >> 1;
  1824. if (!fam_type->flags.zn_regs_v2)
  1825. cs_mask_nr >>= 1;
  1826. /* Asymmetric dual-rank DIMM support. */
  1827. if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
  1828. addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
  1829. else
  1830. addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
  1831. /*
  1832. * The number of zero bits in the mask is equal to the number of bits
  1833. * in a full mask minus the number of bits in the current mask.
  1834. *
  1835. * The MSB is the number of bits in the full mask because BIT[0] is
  1836. * always 0.
  1837. *
  1838. * In the special 3 Rank interleaving case, a single bit is flipped
  1839. * without swapping with the most significant bit. This can be handled
  1840. * by keeping the MSB where it is and ignoring the single zero bit.
  1841. */
  1842. msb = fls(addr_mask_orig) - 1;
  1843. weight = hweight_long(addr_mask_orig);
  1844. num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE);
  1845. /* Take the number of zero bits off from the top of the mask. */
  1846. addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1);
  1847. edac_dbg(1, "CS%d DIMM%d AddrMasks:\n", csrow_nr, dimm);
  1848. edac_dbg(1, " Original AddrMask: 0x%x\n", addr_mask_orig);
  1849. edac_dbg(1, " Deinterleaved AddrMask: 0x%x\n", addr_mask_deinterleaved);
  1850. /* Register [31:1] = Address [39:9]. Size is in kBs here. */
  1851. size = (addr_mask_deinterleaved >> 2) + 1;
  1852. /* Return size in MBs. */
  1853. return size >> 10;
  1854. }
  1855. static void read_dram_ctl_register(struct amd64_pvt *pvt)
  1856. {
  1857. if (pvt->fam == 0xf)
  1858. return;
  1859. if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
  1860. edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
  1861. pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
  1862. edac_dbg(0, " DCTs operate in %s mode\n",
  1863. (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
  1864. if (!dct_ganging_enabled(pvt))
  1865. edac_dbg(0, " Address range split per DCT: %s\n",
  1866. (dct_high_range_enabled(pvt) ? "yes" : "no"));
  1867. edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
  1868. (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
  1869. (dct_memory_cleared(pvt) ? "yes" : "no"));
  1870. edac_dbg(0, " channel interleave: %s, "
  1871. "interleave bits selector: 0x%x\n",
  1872. (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
  1873. dct_sel_interleave_addr(pvt));
  1874. }
  1875. amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
  1876. }
  1877. /*
  1878. * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG,
  1879. * 2.10.12 Memory Interleaving Modes).
  1880. */
  1881. static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
  1882. u8 intlv_en, int num_dcts_intlv,
  1883. u32 dct_sel)
  1884. {
  1885. u8 channel = 0;
  1886. u8 select;
  1887. if (!(intlv_en))
  1888. return (u8)(dct_sel);
  1889. if (num_dcts_intlv == 2) {
  1890. select = (sys_addr >> 8) & 0x3;
  1891. channel = select ? 0x3 : 0;
  1892. } else if (num_dcts_intlv == 4) {
  1893. u8 intlv_addr = dct_sel_interleave_addr(pvt);
  1894. switch (intlv_addr) {
  1895. case 0x4:
  1896. channel = (sys_addr >> 8) & 0x3;
  1897. break;
  1898. case 0x5:
  1899. channel = (sys_addr >> 9) & 0x3;
  1900. break;
  1901. }
  1902. }
  1903. return channel;
  1904. }
  1905. /*
  1906. * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory
  1907. * Interleaving Modes.
  1908. */
  1909. static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
  1910. bool hi_range_sel, u8 intlv_en)
  1911. {
  1912. u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
  1913. if (dct_ganging_enabled(pvt))
  1914. return 0;
  1915. if (hi_range_sel)
  1916. return dct_sel_high;
  1917. /*
  1918. * see F2x110[DctSelIntLvAddr] - channel interleave mode
  1919. */
  1920. if (dct_interleave_enabled(pvt)) {
  1921. u8 intlv_addr = dct_sel_interleave_addr(pvt);
  1922. /* return DCT select function: 0=DCT0, 1=DCT1 */
  1923. if (!intlv_addr)
  1924. return sys_addr >> 6 & 1;
  1925. if (intlv_addr & 0x2) {
  1926. u8 shift = intlv_addr & 0x1 ? 9 : 6;
  1927. u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) & 1;
  1928. return ((sys_addr >> shift) & 1) ^ temp;
  1929. }
  1930. if (intlv_addr & 0x4) {
  1931. u8 shift = intlv_addr & 0x1 ? 9 : 8;
  1932. return (sys_addr >> shift) & 1;
  1933. }
  1934. return (sys_addr >> (12 + hweight8(intlv_en))) & 1;
  1935. }
  1936. if (dct_high_range_enabled(pvt))
  1937. return ~dct_sel_high & 1;
  1938. return 0;
  1939. }
  1940. /* Convert the sys_addr to the normalized DCT address */
  1941. static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
  1942. u64 sys_addr, bool hi_rng,
  1943. u32 dct_sel_base_addr)
  1944. {
  1945. u64 chan_off;
  1946. u64 dram_base = get_dram_base(pvt, range);
  1947. u64 hole_off = f10_dhar_offset(pvt);
  1948. u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
  1949. if (hi_rng) {
  1950. /*
  1951. * if
  1952. * base address of high range is below 4Gb
  1953. * (bits [47:27] at [31:11])
  1954. * DRAM address space on this DCT is hoisted above 4Gb &&
  1955. * sys_addr > 4Gb
  1956. *
  1957. * remove hole offset from sys_addr
  1958. * else
  1959. * remove high range offset from sys_addr
  1960. */
  1961. if ((!(dct_sel_base_addr >> 16) ||
  1962. dct_sel_base_addr < dhar_base(pvt)) &&
  1963. dhar_valid(pvt) &&
  1964. (sys_addr >= BIT_64(32)))
  1965. chan_off = hole_off;
  1966. else
  1967. chan_off = dct_sel_base_off;
  1968. } else {
  1969. /*
  1970. * if
  1971. * we have a valid hole &&
  1972. * sys_addr > 4Gb
  1973. *
  1974. * remove hole
  1975. * else
  1976. * remove dram base to normalize to DCT address
  1977. */
  1978. if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
  1979. chan_off = hole_off;
  1980. else
  1981. chan_off = dram_base;
  1982. }
  1983. return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23));
  1984. }
  1985. /*
  1986. * checks if the csrow passed in is marked as SPARED, if so returns the new
  1987. * spare row
  1988. */
  1989. static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
  1990. {
  1991. int tmp_cs;
  1992. if (online_spare_swap_done(pvt, dct) &&
  1993. csrow == online_spare_bad_dramcs(pvt, dct)) {
  1994. for_each_chip_select(tmp_cs, dct, pvt) {
  1995. if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
  1996. csrow = tmp_cs;
  1997. break;
  1998. }
  1999. }
  2000. }
  2001. return csrow;
  2002. }
  2003. /*
  2004. * Iterate over the DRAM DCT "base" and "mask" registers looking for a
  2005. * SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
  2006. *
  2007. * Return:
  2008. * -EINVAL: NOT FOUND
  2009. * 0..csrow = Chip-Select Row
  2010. */
  2011. static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct)
  2012. {
  2013. struct mem_ctl_info *mci;
  2014. struct amd64_pvt *pvt;
  2015. u64 cs_base, cs_mask;
  2016. int cs_found = -EINVAL;
  2017. int csrow;
  2018. mci = edac_mc_find(nid);
  2019. if (!mci)
  2020. return cs_found;
  2021. pvt = mci->pvt_info;
  2022. edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
  2023. for_each_chip_select(csrow, dct, pvt) {
  2024. if (!csrow_enabled(csrow, dct, pvt))
  2025. continue;
  2026. get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
  2027. edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
  2028. csrow, cs_base, cs_mask);
  2029. cs_mask = ~cs_mask;
  2030. edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
  2031. (in_addr & cs_mask), (cs_base & cs_mask));
  2032. if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
  2033. if (pvt->fam == 0x15 && pvt->model >= 0x30) {
  2034. cs_found = csrow;
  2035. break;
  2036. }
  2037. cs_found = f10_process_possible_spare(pvt, dct, csrow);
  2038. edac_dbg(1, " MATCH csrow=%d\n", cs_found);
  2039. break;
  2040. }
  2041. }
  2042. return cs_found;
  2043. }
  2044. /*
  2045. * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
  2046. * swapped with a region located at the bottom of memory so that the GPU can use
  2047. * the interleaved region and thus two channels.
  2048. */
  2049. static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
  2050. {
  2051. u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
  2052. if (pvt->fam == 0x10) {
  2053. /* only revC3 and revE have that feature */
  2054. if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
  2055. return sys_addr;
  2056. }
  2057. amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
  2058. if (!(swap_reg & 0x1))
  2059. return sys_addr;
  2060. swap_base = (swap_reg >> 3) & 0x7f;
  2061. swap_limit = (swap_reg >> 11) & 0x7f;
  2062. rgn_size = (swap_reg >> 20) & 0x7f;
  2063. tmp_addr = sys_addr >> 27;
  2064. if (!(sys_addr >> 34) &&
  2065. (((tmp_addr >= swap_base) &&
  2066. (tmp_addr <= swap_limit)) ||
  2067. (tmp_addr < rgn_size)))
  2068. return sys_addr ^ (u64)swap_base << 27;
  2069. return sys_addr;
  2070. }
  2071. /* For a given @dram_range, check if @sys_addr falls within it. */
  2072. static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
  2073. u64 sys_addr, int *chan_sel)
  2074. {
  2075. int cs_found = -EINVAL;
  2076. u64 chan_addr;
  2077. u32 dct_sel_base;
  2078. u8 channel;
  2079. bool high_range = false;
  2080. u8 node_id = dram_dst_node(pvt, range);
  2081. u8 intlv_en = dram_intlv_en(pvt, range);
  2082. u32 intlv_sel = dram_intlv_sel(pvt, range);
  2083. edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
  2084. range, sys_addr, get_dram_limit(pvt, range));
  2085. if (dhar_valid(pvt) &&
  2086. dhar_base(pvt) <= sys_addr &&
  2087. sys_addr < BIT_64(32)) {
  2088. amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
  2089. sys_addr);
  2090. return -EINVAL;
  2091. }
  2092. if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en)))
  2093. return -EINVAL;
  2094. sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
  2095. dct_sel_base = dct_sel_baseaddr(pvt);
  2096. /*
  2097. * check whether addresses >= DctSelBaseAddr[47:27] are to be used to
  2098. * select between DCT0 and DCT1.
  2099. */
  2100. if (dct_high_range_enabled(pvt) &&
  2101. !dct_ganging_enabled(pvt) &&
  2102. ((sys_addr >> 27) >= (dct_sel_base >> 11)))
  2103. high_range = true;
  2104. channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
  2105. chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
  2106. high_range, dct_sel_base);
  2107. /* Remove node interleaving, see F1x120 */
  2108. if (intlv_en)
  2109. chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) |
  2110. (chan_addr & 0xfff);
  2111. /* remove channel interleave */
  2112. if (dct_interleave_enabled(pvt) &&
  2113. !dct_high_range_enabled(pvt) &&
  2114. !dct_ganging_enabled(pvt)) {
  2115. if (dct_sel_interleave_addr(pvt) != 1) {
  2116. if (dct_sel_interleave_addr(pvt) == 0x3)
  2117. /* hash 9 */
  2118. chan_addr = ((chan_addr >> 10) << 9) |
  2119. (chan_addr & 0x1ff);
  2120. else
  2121. /* A[6] or hash 6 */
  2122. chan_addr = ((chan_addr >> 7) << 6) |
  2123. (chan_addr & 0x3f);
  2124. } else
  2125. /* A[12] */
  2126. chan_addr = ((chan_addr >> 13) << 12) |
  2127. (chan_addr & 0xfff);
  2128. }
  2129. edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
  2130. cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
  2131. if (cs_found >= 0)
  2132. *chan_sel = channel;
  2133. return cs_found;
  2134. }
  2135. static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
  2136. u64 sys_addr, int *chan_sel)
  2137. {
  2138. int cs_found = -EINVAL;
  2139. int num_dcts_intlv = 0;
  2140. u64 chan_addr, chan_offset;
  2141. u64 dct_base, dct_limit;
  2142. u32 dct_cont_base_reg, dct_cont_limit_reg, tmp;
  2143. u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en;
  2144. u64 dhar_offset = f10_dhar_offset(pvt);
  2145. u8 intlv_addr = dct_sel_interleave_addr(pvt);
  2146. u8 node_id = dram_dst_node(pvt, range);
  2147. u8 intlv_en = dram_intlv_en(pvt, range);
  2148. amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
  2149. amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);
  2150. dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0));
  2151. dct_sel = (u8) ((dct_cont_base_reg >> 4) & 0x7);
  2152. edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
  2153. range, sys_addr, get_dram_limit(pvt, range));
  2154. if (!(get_dram_base(pvt, range) <= sys_addr) &&
  2155. !(get_dram_limit(pvt, range) >= sys_addr))
  2156. return -EINVAL;
  2157. if (dhar_valid(pvt) &&
  2158. dhar_base(pvt) <= sys_addr &&
  2159. sys_addr < BIT_64(32)) {
  2160. amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n",
  2161. sys_addr);
  2162. return -EINVAL;
  2163. }
  2164. /* Verify sys_addr is within DCT Range. */
  2165. dct_base = (u64) dct_sel_baseaddr(pvt);
  2166. dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
  2167. if (!(dct_cont_base_reg & BIT(0)) &&
  2168. !(dct_base <= (sys_addr >> 27) &&
  2169. dct_limit >= (sys_addr >> 27)))
  2170. return -EINVAL;
  2171. /* Verify number of dct's that participate in channel interleaving. */
  2172. num_dcts_intlv = (int) hweight8(intlv_en);
  2173. if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4))
  2174. return -EINVAL;
  2175. if (pvt->model >= 0x60)
  2176. channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
  2177. else
  2178. channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
  2179. num_dcts_intlv, dct_sel);
  2180. /* Verify we stay within the MAX number of channels allowed */
  2181. if (channel > 3)
  2182. return -EINVAL;
  2183. leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0));
  2184. /* Get normalized DCT addr */
  2185. if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
  2186. chan_offset = dhar_offset;
  2187. else
  2188. chan_offset = dct_base << 27;
  2189. chan_addr = sys_addr - chan_offset;
  2190. /* remove channel interleave */
  2191. if (num_dcts_intlv == 2) {
  2192. if (intlv_addr == 0x4)
  2193. chan_addr = ((chan_addr >> 9) << 8) |
  2194. (chan_addr & 0xff);
  2195. else if (intlv_addr == 0x5)
  2196. chan_addr = ((chan_addr >> 10) << 9) |
  2197. (chan_addr & 0x1ff);
  2198. else
  2199. return -EINVAL;
  2200. } else if (num_dcts_intlv == 4) {
  2201. if (intlv_addr == 0x4)
  2202. chan_addr = ((chan_addr >> 10) << 8) |
  2203. (chan_addr & 0xff);
  2204. else if (intlv_addr == 0x5)
  2205. chan_addr = ((chan_addr >> 11) << 9) |
  2206. (chan_addr & 0x1ff);
  2207. else
  2208. return -EINVAL;
  2209. }
  2210. if (dct_offset_en) {
  2211. amd64_read_pci_cfg(pvt->F1,
  2212. DRAM_CONT_HIGH_OFF + (int) channel * 4,
  2213. &tmp);
  2214. chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27;
  2215. }
  2216. f15h_select_dct(pvt, channel);
  2217. edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
  2218. /*
  2219. * Find Chip select:
  2220. * if channel = 3, then alias it to 1. This is because, in F15 M30h,
  2221. * there is support for 4 DCT's, but only 2 are currently functional.
  2222. * They are DCT0 and DCT3. But we have read all registers of DCT3 into
  2223. * pvt->csels[1]. So we need to use '1' here to get correct info.
  2224. * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications.
  2225. */
  2226. alias_channel = (channel == 3) ? 1 : channel;
  2227. cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel);
  2228. if (cs_found >= 0)
  2229. *chan_sel = alias_channel;
  2230. return cs_found;
  2231. }
  2232. static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
  2233. u64 sys_addr,
  2234. int *chan_sel)
  2235. {
  2236. int cs_found = -EINVAL;
  2237. unsigned range;
  2238. for (range = 0; range < DRAM_RANGES; range++) {
  2239. if (!dram_rw(pvt, range))
  2240. continue;
  2241. if (pvt->fam == 0x15 && pvt->model >= 0x30)
  2242. cs_found = f15_m30h_match_to_this_node(pvt, range,
  2243. sys_addr,
  2244. chan_sel);
  2245. else if ((get_dram_base(pvt, range) <= sys_addr) &&
  2246. (get_dram_limit(pvt, range) >= sys_addr)) {
  2247. cs_found = f1x_match_to_this_node(pvt, range,
  2248. sys_addr, chan_sel);
  2249. if (cs_found >= 0)
  2250. break;
  2251. }
  2252. }
  2253. return cs_found;
  2254. }
  2255. /*
  2256. * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps
  2257. * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW).
  2258. *
  2259. * The @sys_addr is usually an error address received from the hardware
  2260. * (MCX_ADDR).
  2261. */
  2262. static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
  2263. struct err_info *err)
  2264. {
  2265. struct amd64_pvt *pvt = mci->pvt_info;
  2266. error_address_to_page_and_offset(sys_addr, err);
  2267. err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
  2268. if (err->csrow < 0) {
  2269. err->err_code = ERR_CSROW;
  2270. return;
  2271. }
  2272. /*
  2273. * We need the syndromes for channel detection only when we're
  2274. * ganged. Otherwise @chan should already contain the channel at
  2275. * this point.
  2276. */
  2277. if (dct_ganging_enabled(pvt))
  2278. err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome);
  2279. }
  2280. /*
  2281. * debug routine to display the memory sizes of all logical DIMMs and its
  2282. * CSROWs
  2283. */
  2284. static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
  2285. {
  2286. int dimm, size0, size1;
  2287. u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
  2288. u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
  2289. if (pvt->fam == 0xf) {
  2290. /* K8 families < revF not supported yet */
  2291. if (pvt->ext_model < K8_REV_F)
  2292. return;
  2293. else
  2294. WARN_ON(ctrl != 0);
  2295. }
  2296. if (pvt->fam == 0x10) {
  2297. dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
  2298. : pvt->dbam0;
  2299. dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
  2300. pvt->csels[1].csbases :
  2301. pvt->csels[0].csbases;
  2302. } else if (ctrl) {
  2303. dbam = pvt->dbam0;
  2304. dcsb = pvt->csels[1].csbases;
  2305. }
  2306. edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
  2307. ctrl, dbam);
  2308. edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
  2309. /* Dump memory sizes for DIMM and its CSROWs */
  2310. for (dimm = 0; dimm < 4; dimm++) {
  2311. size0 = 0;
  2312. if (dcsb[dimm*2] & DCSB_CS_ENABLE)
  2313. /*
  2314. * For F15m60h, we need multiplier for LRDIMM cs_size
  2315. * calculation. We pass dimm value to the dbam_to_cs
  2316. * mapper so we can find the multiplier from the
  2317. * corresponding DCSM.
  2318. */
  2319. size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
  2320. DBAM_DIMM(dimm, dbam),
  2321. dimm);
  2322. size1 = 0;
  2323. if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE)
  2324. size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
  2325. DBAM_DIMM(dimm, dbam),
  2326. dimm);
  2327. amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n",
  2328. dimm * 2, size0,
  2329. dimm * 2 + 1, size1);
  2330. }
  2331. }
  2332. static struct amd64_family_type family_types[] = {
  2333. [K8_CPUS] = {
  2334. .ctl_name = "K8",
  2335. .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP,
  2336. .f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,
  2337. .max_mcs = 2,
  2338. .ops = {
  2339. .early_channel_count = k8_early_channel_count,
  2340. .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow,
  2341. .dbam_to_cs = k8_dbam_to_chip_select,
  2342. }
  2343. },
  2344. [F10_CPUS] = {
  2345. .ctl_name = "F10h",
  2346. .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
  2347. .f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM,
  2348. .max_mcs = 2,
  2349. .ops = {
  2350. .early_channel_count = f1x_early_channel_count,
  2351. .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
  2352. .dbam_to_cs = f10_dbam_to_chip_select,
  2353. }
  2354. },
  2355. [F15_CPUS] = {
  2356. .ctl_name = "F15h",
  2357. .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1,
  2358. .f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2,
  2359. .max_mcs = 2,
  2360. .ops = {
  2361. .early_channel_count = f1x_early_channel_count,
  2362. .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
  2363. .dbam_to_cs = f15_dbam_to_chip_select,
  2364. }
  2365. },
  2366. [F15_M30H_CPUS] = {
  2367. .ctl_name = "F15h_M30h",
  2368. .f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1,
  2369. .f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2,
  2370. .max_mcs = 2,
  2371. .ops = {
  2372. .early_channel_count = f1x_early_channel_count,
  2373. .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
  2374. .dbam_to_cs = f16_dbam_to_chip_select,
  2375. }
  2376. },
  2377. [F15_M60H_CPUS] = {
  2378. .ctl_name = "F15h_M60h",
  2379. .f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1,
  2380. .f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2,
  2381. .max_mcs = 2,
  2382. .ops = {
  2383. .early_channel_count = f1x_early_channel_count,
  2384. .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
  2385. .dbam_to_cs = f15_m60h_dbam_to_chip_select,
  2386. }
  2387. },
  2388. [F16_CPUS] = {
  2389. .ctl_name = "F16h",
  2390. .f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1,
  2391. .f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2,
  2392. .max_mcs = 2,
  2393. .ops = {
  2394. .early_channel_count = f1x_early_channel_count,
  2395. .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
  2396. .dbam_to_cs = f16_dbam_to_chip_select,
  2397. }
  2398. },
  2399. [F16_M30H_CPUS] = {
  2400. .ctl_name = "F16h_M30h",
  2401. .f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1,
  2402. .f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2,
  2403. .max_mcs = 2,
  2404. .ops = {
  2405. .early_channel_count = f1x_early_channel_count,
  2406. .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow,
  2407. .dbam_to_cs = f16_dbam_to_chip_select,
  2408. }
  2409. },
  2410. [F17_CPUS] = {
  2411. .ctl_name = "F17h",
  2412. .f0_id = PCI_DEVICE_ID_AMD_17H_DF_F0,
  2413. .f6_id = PCI_DEVICE_ID_AMD_17H_DF_F6,
  2414. .max_mcs = 2,
  2415. .ops = {
  2416. .early_channel_count = f17_early_channel_count,
  2417. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2418. }
  2419. },
  2420. [F17_M10H_CPUS] = {
  2421. .ctl_name = "F17h_M10h",
  2422. .f0_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F0,
  2423. .f6_id = PCI_DEVICE_ID_AMD_17H_M10H_DF_F6,
  2424. .max_mcs = 2,
  2425. .ops = {
  2426. .early_channel_count = f17_early_channel_count,
  2427. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2428. }
  2429. },
  2430. [F17_M30H_CPUS] = {
  2431. .ctl_name = "F17h_M30h",
  2432. .f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,
  2433. .f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6,
  2434. .max_mcs = 8,
  2435. .ops = {
  2436. .early_channel_count = f17_early_channel_count,
  2437. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2438. }
  2439. },
  2440. [F17_M60H_CPUS] = {
  2441. .ctl_name = "F17h_M60h",
  2442. .f0_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F0,
  2443. .f6_id = PCI_DEVICE_ID_AMD_17H_M60H_DF_F6,
  2444. .max_mcs = 2,
  2445. .ops = {
  2446. .early_channel_count = f17_early_channel_count,
  2447. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2448. }
  2449. },
  2450. [F17_M70H_CPUS] = {
  2451. .ctl_name = "F17h_M70h",
  2452. .f0_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F0,
  2453. .f6_id = PCI_DEVICE_ID_AMD_17H_M70H_DF_F6,
  2454. .max_mcs = 2,
  2455. .ops = {
  2456. .early_channel_count = f17_early_channel_count,
  2457. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2458. }
  2459. },
  2460. [F19_CPUS] = {
  2461. .ctl_name = "F19h",
  2462. .f0_id = PCI_DEVICE_ID_AMD_19H_DF_F0,
  2463. .f6_id = PCI_DEVICE_ID_AMD_19H_DF_F6,
  2464. .max_mcs = 8,
  2465. .ops = {
  2466. .early_channel_count = f17_early_channel_count,
  2467. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2468. }
  2469. },
  2470. [F19_M10H_CPUS] = {
  2471. .ctl_name = "F19h_M10h",
  2472. .f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,
  2473. .f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6,
  2474. .max_mcs = 12,
  2475. .flags.zn_regs_v2 = 1,
  2476. .ops = {
  2477. .early_channel_count = f17_early_channel_count,
  2478. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2479. }
  2480. },
  2481. [F19_M50H_CPUS] = {
  2482. .ctl_name = "F19h_M50h",
  2483. .f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,
  2484. .f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6,
  2485. .max_mcs = 2,
  2486. .ops = {
  2487. .early_channel_count = f17_early_channel_count,
  2488. .dbam_to_cs = f17_addr_mask_to_cs_size,
  2489. }
  2490. },
  2491. };
  2492. /*
  2493. * These are tables of eigenvectors (one per line) which can be used for the
  2494. * construction of the syndrome tables. The modified syndrome search algorithm
  2495. * uses those to find the symbol in error and thus the DIMM.
  2496. *
  2497. * Algorithm courtesy of Ross LaFetra from AMD.
  2498. */
  2499. static const u16 x4_vectors[] = {
  2500. 0x2f57, 0x1afe, 0x66cc, 0xdd88,
  2501. 0x11eb, 0x3396, 0x7f4c, 0xeac8,
  2502. 0x0001, 0x0002, 0x0004, 0x0008,
  2503. 0x1013, 0x3032, 0x4044, 0x8088,
  2504. 0x106b, 0x30d6, 0x70fc, 0xe0a8,
  2505. 0x4857, 0xc4fe, 0x13cc, 0x3288,
  2506. 0x1ac5, 0x2f4a, 0x5394, 0xa1e8,
  2507. 0x1f39, 0x251e, 0xbd6c, 0x6bd8,
  2508. 0x15c1, 0x2a42, 0x89ac, 0x4758,
  2509. 0x2b03, 0x1602, 0x4f0c, 0xca08,
  2510. 0x1f07, 0x3a0e, 0x6b04, 0xbd08,
  2511. 0x8ba7, 0x465e, 0x244c, 0x1cc8,
  2512. 0x2b87, 0x164e, 0x642c, 0xdc18,
  2513. 0x40b9, 0x80de, 0x1094, 0x20e8,
  2514. 0x27db, 0x1eb6, 0x9dac, 0x7b58,
  2515. 0x11c1, 0x2242, 0x84ac, 0x4c58,
  2516. 0x1be5, 0x2d7a, 0x5e34, 0xa718,
  2517. 0x4b39, 0x8d1e, 0x14b4, 0x28d8,
  2518. 0x4c97, 0xc87e, 0x11fc, 0x33a8,
  2519. 0x8e97, 0x497e, 0x2ffc, 0x1aa8,
  2520. 0x16b3, 0x3d62, 0x4f34, 0x8518,
  2521. 0x1e2f, 0x391a, 0x5cac, 0xf858,
  2522. 0x1d9f, 0x3b7a, 0x572c, 0xfe18,
  2523. 0x15f5, 0x2a5a, 0x5264, 0xa3b8,
  2524. 0x1dbb, 0x3b66, 0x715c, 0xe3f8,
  2525. 0x4397, 0xc27e, 0x17fc, 0x3ea8,
  2526. 0x1617, 0x3d3e, 0x6464, 0xb8b8,
  2527. 0x23ff, 0x12aa, 0xab6c, 0x56d8,
  2528. 0x2dfb, 0x1ba6, 0x913c, 0x7328,
  2529. 0x185d, 0x2ca6, 0x7914, 0x9e28,
  2530. 0x171b, 0x3e36, 0x7d7c, 0xebe8,
  2531. 0x4199, 0x82ee, 0x19f4, 0x2e58,
  2532. 0x4807, 0xc40e, 0x130c, 0x3208,
  2533. 0x1905, 0x2e0a, 0x5804, 0xac08,
  2534. 0x213f, 0x132a, 0xadfc, 0x5ba8,
  2535. 0x19a9, 0x2efe, 0xb5cc, 0x6f88,
  2536. };
  2537. static const u16 x8_vectors[] = {
  2538. 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480,
  2539. 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80,
  2540. 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80,
  2541. 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80,
  2542. 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780,
  2543. 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080,
  2544. 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080,
  2545. 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080,
  2546. 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80,
  2547. 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580,
  2548. 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880,
  2549. 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280,
  2550. 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180,
  2551. 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580,
  2552. 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280,
  2553. 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180,
  2554. 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080,
  2555. 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
  2556. 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000,
  2557. };
  2558. static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs,
  2559. unsigned v_dim)
  2560. {
  2561. unsigned int i, err_sym;
  2562. for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) {
  2563. u16 s = syndrome;
  2564. unsigned v_idx = err_sym * v_dim;
  2565. unsigned v_end = (err_sym + 1) * v_dim;
  2566. /* walk over all 16 bits of the syndrome */
  2567. for (i = 1; i < (1U << 16); i <<= 1) {
  2568. /* if bit is set in that eigenvector... */
  2569. if (v_idx < v_end && vectors[v_idx] & i) {
  2570. u16 ev_comp = vectors[v_idx++];
  2571. /* ... and bit set in the modified syndrome, */
  2572. if (s & i) {
  2573. /* remove it. */
  2574. s ^= ev_comp;
  2575. if (!s)
  2576. return err_sym;
  2577. }
  2578. } else if (s & i)
  2579. /* can't get to zero, move to next symbol */
  2580. break;
  2581. }
  2582. }
  2583. edac_dbg(0, "syndrome(%x) not found\n", syndrome);
  2584. return -1;
  2585. }
  2586. static int map_err_sym_to_channel(int err_sym, int sym_size)
  2587. {
  2588. if (sym_size == 4)
  2589. switch (err_sym) {
  2590. case 0x20:
  2591. case 0x21:
  2592. return 0;
  2593. case 0x22:
  2594. case 0x23:
  2595. return 1;
  2596. default:
  2597. return err_sym >> 4;
  2598. }
  2599. /* x8 symbols */
  2600. else
  2601. switch (err_sym) {
  2602. /* imaginary bits not in a DIMM */
  2603. case 0x10:
  2604. WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n",
  2605. err_sym);
  2606. return -1;
  2607. case 0x11:
  2608. return 0;
  2609. case 0x12:
  2610. return 1;
  2611. default:
  2612. return err_sym >> 3;
  2613. }
  2614. return -1;
  2615. }
  2616. static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
  2617. {
  2618. struct amd64_pvt *pvt = mci->pvt_info;
  2619. int err_sym = -1;
  2620. if (pvt->ecc_sym_sz == 8)
  2621. err_sym = decode_syndrome(syndrome, x8_vectors,
  2622. ARRAY_SIZE(x8_vectors),
  2623. pvt->ecc_sym_sz);
  2624. else if (pvt->ecc_sym_sz == 4)
  2625. err_sym = decode_syndrome(syndrome, x4_vectors,
  2626. ARRAY_SIZE(x4_vectors),
  2627. pvt->ecc_sym_sz);
  2628. else {
  2629. amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
  2630. return err_sym;
  2631. }
  2632. return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
  2633. }
  2634. static void __log_ecc_error(struct mem_ctl_info *mci, struct err_info *err,
  2635. u8 ecc_type)
  2636. {
  2637. enum hw_event_mc_err_type err_type;
  2638. const char *string;
  2639. if (ecc_type == 2)
  2640. err_type = HW_EVENT_ERR_CORRECTED;
  2641. else if (ecc_type == 1)
  2642. err_type = HW_EVENT_ERR_UNCORRECTED;
  2643. else if (ecc_type == 3)
  2644. err_type = HW_EVENT_ERR_DEFERRED;
  2645. else {
  2646. WARN(1, "Something is rotten in the state of Denmark.\n");
  2647. return;
  2648. }
  2649. switch (err->err_code) {
  2650. case DECODE_OK:
  2651. string = "";
  2652. break;
  2653. case ERR_NODE:
  2654. string = "Failed to map error addr to a node";
  2655. break;
  2656. case ERR_CSROW:
  2657. string = "Failed to map error addr to a csrow";
  2658. break;
  2659. case ERR_CHANNEL:
  2660. string = "Unknown syndrome - possible error reporting race";
  2661. break;
  2662. case ERR_SYND:
  2663. string = "MCA_SYND not valid - unknown syndrome and csrow";
  2664. break;
  2665. case ERR_NORM_ADDR:
  2666. string = "Cannot decode normalized address";
  2667. break;
  2668. default:
  2669. string = "WTF error";
  2670. break;
  2671. }
  2672. edac_mc_handle_error(err_type, mci, 1,
  2673. err->page, err->offset, err->syndrome,
  2674. err->csrow, err->channel, -1,
  2675. string, "");
  2676. }
  2677. static inline void decode_bus_error(int node_id, struct mce *m)
  2678. {
  2679. struct mem_ctl_info *mci;
  2680. struct amd64_pvt *pvt;
  2681. u8 ecc_type = (m->status >> 45) & 0x3;
  2682. u8 xec = XEC(m->status, 0x1f);
  2683. u16 ec = EC(m->status);
  2684. u64 sys_addr;
  2685. struct err_info err;
  2686. mci = edac_mc_find(node_id);
  2687. if (!mci)
  2688. return;
  2689. pvt = mci->pvt_info;
  2690. /* Bail out early if this was an 'observed' error */
  2691. if (PP(ec) == NBSL_PP_OBS)
  2692. return;
  2693. /* Do only ECC errors */
  2694. if (xec && xec != F10_NBSL_EXT_ERR_ECC)
  2695. return;
  2696. memset(&err, 0, sizeof(err));
  2697. sys_addr = get_error_address(pvt, m);
  2698. if (ecc_type == 2)
  2699. err.syndrome = extract_syndrome(m->status);
  2700. pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);
  2701. __log_ecc_error(mci, &err, ecc_type);
  2702. }
  2703. /*
  2704. * To find the UMC channel represented by this bank we need to match on its
  2705. * instance_id. The instance_id of a bank is held in the lower 32 bits of its
  2706. * IPID.
  2707. *
  2708. * Currently, we can derive the channel number by looking at the 6th nibble in
  2709. * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
  2710. * number.
  2711. */
  2712. static int find_umc_channel(struct mce *m)
  2713. {
  2714. return (m->ipid & GENMASK(31, 0)) >> 20;
  2715. }
  2716. static void decode_umc_error(int node_id, struct mce *m)
  2717. {
  2718. u8 ecc_type = (m->status >> 45) & 0x3;
  2719. struct mem_ctl_info *mci;
  2720. struct amd64_pvt *pvt;
  2721. struct err_info err;
  2722. u64 sys_addr;
  2723. mci = edac_mc_find(node_id);
  2724. if (!mci)
  2725. return;
  2726. pvt = mci->pvt_info;
  2727. memset(&err, 0, sizeof(err));
  2728. if (m->status & MCI_STATUS_DEFERRED)
  2729. ecc_type = 3;
  2730. err.channel = find_umc_channel(m);
  2731. if (!(m->status & MCI_STATUS_SYNDV)) {
  2732. err.err_code = ERR_SYND;
  2733. goto log_error;
  2734. }
  2735. if (ecc_type == 2) {
  2736. u8 length = (m->synd >> 18) & 0x3f;
  2737. if (length)
  2738. err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0);
  2739. else
  2740. err.err_code = ERR_CHANNEL;
  2741. }
  2742. err.csrow = m->synd & 0x7;
  2743. if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
  2744. err.err_code = ERR_NORM_ADDR;
  2745. goto log_error;
  2746. }
  2747. error_address_to_page_and_offset(sys_addr, &err);
  2748. log_error:
  2749. __log_ecc_error(mci, &err, ecc_type);
  2750. }
  2751. /*
  2752. * Use pvt->F3 which contains the F3 CPU PCI device to get the related
  2753. * F1 (AddrMap) and F2 (Dct) devices. Return negative value on error.
  2754. * Reserve F0 and F6 on systems with a UMC.
  2755. */
  2756. static int
  2757. reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
  2758. {
  2759. if (pvt->umc) {
  2760. pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
  2761. if (!pvt->F0) {
  2762. edac_dbg(1, "F0 not found, device 0x%x\n", pci_id1);
  2763. return -ENODEV;
  2764. }
  2765. pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
  2766. if (!pvt->F6) {
  2767. pci_dev_put(pvt->F0);
  2768. pvt->F0 = NULL;
  2769. edac_dbg(1, "F6 not found: device 0x%x\n", pci_id2);
  2770. return -ENODEV;
  2771. }
  2772. if (!pci_ctl_dev)
  2773. pci_ctl_dev = &pvt->F0->dev;
  2774. edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
  2775. edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
  2776. edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));
  2777. return 0;
  2778. }
  2779. /* Reserve the ADDRESS MAP Device */
  2780. pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
  2781. if (!pvt->F1) {
  2782. edac_dbg(1, "F1 not found: device 0x%x\n", pci_id1);
  2783. return -ENODEV;
  2784. }
  2785. /* Reserve the DCT Device */
  2786. pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
  2787. if (!pvt->F2) {
  2788. pci_dev_put(pvt->F1);
  2789. pvt->F1 = NULL;
  2790. edac_dbg(1, "F2 not found: device 0x%x\n", pci_id2);
  2791. return -ENODEV;
  2792. }
  2793. if (!pci_ctl_dev)
  2794. pci_ctl_dev = &pvt->F2->dev;
  2795. edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
  2796. edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
  2797. edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
  2798. return 0;
  2799. }
  2800. static void free_mc_sibling_devs(struct amd64_pvt *pvt)
  2801. {
  2802. if (pvt->umc) {
  2803. pci_dev_put(pvt->F0);
  2804. pci_dev_put(pvt->F6);
  2805. } else {
  2806. pci_dev_put(pvt->F1);
  2807. pci_dev_put(pvt->F2);
  2808. }
  2809. }
  2810. static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
  2811. {
  2812. pvt->ecc_sym_sz = 4;
  2813. if (pvt->umc) {
  2814. u8 i;
  2815. for_each_umc(i) {
  2816. /* Check enabled channels only: */
  2817. if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
  2818. if (pvt->umc[i].ecc_ctrl & BIT(9)) {
  2819. pvt->ecc_sym_sz = 16;
  2820. return;
  2821. } else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
  2822. pvt->ecc_sym_sz = 8;
  2823. return;
  2824. }
  2825. }
  2826. }
  2827. } else if (pvt->fam >= 0x10) {
  2828. u32 tmp;
  2829. amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
  2830. /* F16h has only DCT0, so no need to read dbam1. */
  2831. if (pvt->fam != 0x16)
  2832. amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);
  2833. /* F10h, revD and later can do x8 ECC too. */
  2834. if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
  2835. pvt->ecc_sym_sz = 8;
  2836. }
  2837. }
  2838. /*
  2839. * Retrieve the hardware registers of the memory controller.
  2840. */
  2841. static void __read_mc_regs_df(struct amd64_pvt *pvt)
  2842. {
  2843. u8 nid = pvt->mc_node_id;
  2844. struct amd64_umc *umc;
  2845. u32 i, umc_base;
  2846. /* Read registers from each UMC */
  2847. for_each_umc(i) {
  2848. umc_base = get_umc_base(i);
  2849. umc = &pvt->umc[i];
  2850. amd_smn_read(nid, umc_base + get_umc_reg(UMCCH_DIMM_CFG), &umc->dimm_cfg);
  2851. amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
  2852. amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
  2853. amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
  2854. amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);
  2855. }
  2856. }
  2857. /*
  2858. * Retrieve the hardware registers of the memory controller (this includes the
  2859. * 'Address Map' and 'Misc' device regs)
  2860. */
  2861. static void read_mc_regs(struct amd64_pvt *pvt)
  2862. {
  2863. unsigned int range;
  2864. u64 msr_val;
  2865. /*
  2866. * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since
  2867. * those are Read-As-Zero.
  2868. */
  2869. rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
  2870. edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
  2871. /* Check first whether TOP_MEM2 is enabled: */
  2872. rdmsrl(MSR_AMD64_SYSCFG, msr_val);
  2873. if (msr_val & BIT(21)) {
  2874. rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
  2875. edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
  2876. } else {
  2877. edac_dbg(0, " TOP_MEM2 disabled\n");
  2878. }
  2879. if (pvt->umc) {
  2880. __read_mc_regs_df(pvt);
  2881. amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);
  2882. goto skip;
  2883. }
  2884. amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
  2885. read_dram_ctl_register(pvt);
  2886. for (range = 0; range < DRAM_RANGES; range++) {
  2887. u8 rw;
  2888. /* read settings for this DRAM range */
  2889. read_dram_base_limit_regs(pvt, range);
  2890. rw = dram_rw(pvt, range);
  2891. if (!rw)
  2892. continue;
  2893. edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
  2894. range,
  2895. get_dram_base(pvt, range),
  2896. get_dram_limit(pvt, range));
  2897. edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
  2898. dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
  2899. (rw & 0x1) ? "R" : "-",
  2900. (rw & 0x2) ? "W" : "-",
  2901. dram_intlv_sel(pvt, range),
  2902. dram_dst_node(pvt, range));
  2903. }
  2904. amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
  2905. amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
  2906. amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
  2907. amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
  2908. amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
  2909. if (!dct_ganging_enabled(pvt)) {
  2910. amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
  2911. amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
  2912. }
  2913. skip:
  2914. read_dct_base_mask(pvt);
  2915. determine_memory_type(pvt);
  2916. if (!pvt->umc)
  2917. edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
  2918. determine_ecc_sym_sz(pvt);
  2919. }
  2920. /*
  2921. * NOTE: CPU Revision Dependent code
  2922. *
  2923. * Input:
  2924. * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
  2925. * k8 private pointer to -->
  2926. * DRAM Bank Address mapping register
  2927. * node_id
  2928. * DCL register where dual_channel_active is
  2929. *
  2930. * The DBAM register consists of 4 sets of 4 bits each definitions:
  2931. *
  2932. * Bits: CSROWs
  2933. * 0-3 CSROWs 0 and 1
  2934. * 4-7 CSROWs 2 and 3
  2935. * 8-11 CSROWs 4 and 5
  2936. * 12-15 CSROWs 6 and 7
  2937. *
  2938. * Values range from: 0 to 15
  2939. * The meaning of the values depends on CPU revision and dual-channel state,
  2940. * see relevant BKDG more info.
  2941. *
  2942. * The memory controller provides for total of only 8 CSROWs in its current
  2943. * architecture. Each "pair" of CSROWs normally represents just one DIMM in
  2944. * single channel or two (2) DIMMs in dual channel mode.
  2945. *
  2946. * The following code logic collapses the various tables for CSROW based on CPU
  2947. * revision.
  2948. *
  2949. * Returns:
  2950. * The number of PAGE_SIZE pages on the specified CSROW number it
  2951. * encompasses
  2952. *
  2953. */
  2954. static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
  2955. {
  2956. u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
  2957. int csrow_nr = csrow_nr_orig;
  2958. u32 cs_mode, nr_pages;
  2959. if (!pvt->umc) {
  2960. csrow_nr >>= 1;
  2961. cs_mode = DBAM_DIMM(csrow_nr, dbam);
  2962. } else {
  2963. cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt);
  2964. }
  2965. nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
  2966. nr_pages <<= 20 - PAGE_SHIFT;
  2967. edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",
  2968. csrow_nr_orig, dct, cs_mode);
  2969. edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);
  2970. return nr_pages;
  2971. }
  2972. static int init_csrows_df(struct mem_ctl_info *mci)
  2973. {
  2974. struct amd64_pvt *pvt = mci->pvt_info;
  2975. enum edac_type edac_mode = EDAC_NONE;
  2976. enum dev_type dev_type = DEV_UNKNOWN;
  2977. struct dimm_info *dimm;
  2978. int empty = 1;
  2979. u8 umc, cs;
  2980. if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) {
  2981. edac_mode = EDAC_S16ECD16ED;
  2982. dev_type = DEV_X16;
  2983. } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) {
  2984. edac_mode = EDAC_S8ECD8ED;
  2985. dev_type = DEV_X8;
  2986. } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) {
  2987. edac_mode = EDAC_S4ECD4ED;
  2988. dev_type = DEV_X4;
  2989. } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) {
  2990. edac_mode = EDAC_SECDED;
  2991. }
  2992. for_each_umc(umc) {
  2993. for_each_chip_select(cs, umc, pvt) {
  2994. if (!csrow_enabled(cs, umc, pvt))
  2995. continue;
  2996. empty = 0;
  2997. dimm = mci->csrows[cs]->channels[umc]->dimm;
  2998. edac_dbg(1, "MC node: %d, csrow: %d\n",
  2999. pvt->mc_node_id, cs);
  3000. dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);
  3001. dimm->mtype = pvt->umc[umc].dram_type;
  3002. dimm->edac_mode = edac_mode;
  3003. dimm->dtype = dev_type;
  3004. dimm->grain = 64;
  3005. }
  3006. }
  3007. return empty;
  3008. }
  3009. /*
  3010. * Initialize the array of csrow attribute instances, based on the values
  3011. * from pci config hardware registers.
  3012. */
  3013. static int init_csrows(struct mem_ctl_info *mci)
  3014. {
  3015. struct amd64_pvt *pvt = mci->pvt_info;
  3016. enum edac_type edac_mode = EDAC_NONE;
  3017. struct csrow_info *csrow;
  3018. struct dimm_info *dimm;
  3019. int i, j, empty = 1;
  3020. int nr_pages = 0;
  3021. u32 val;
  3022. if (pvt->umc)
  3023. return init_csrows_df(mci);
  3024. amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
  3025. pvt->nbcfg = val;
  3026. edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
  3027. pvt->mc_node_id, val,
  3028. !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
  3029. /*
  3030. * We iterate over DCT0 here but we look at DCT1 in parallel, if needed.
  3031. */
  3032. for_each_chip_select(i, 0, pvt) {
  3033. bool row_dct0 = !!csrow_enabled(i, 0, pvt);
  3034. bool row_dct1 = false;
  3035. if (pvt->fam != 0xf)
  3036. row_dct1 = !!csrow_enabled(i, 1, pvt);
  3037. if (!row_dct0 && !row_dct1)
  3038. continue;
  3039. csrow = mci->csrows[i];
  3040. empty = 0;
  3041. edac_dbg(1, "MC node: %d, csrow: %d\n",
  3042. pvt->mc_node_id, i);
  3043. if (row_dct0) {
  3044. nr_pages = get_csrow_nr_pages(pvt, 0, i);
  3045. csrow->channels[0]->dimm->nr_pages = nr_pages;
  3046. }
  3047. /* K8 has only one DCT */
  3048. if (pvt->fam != 0xf && row_dct1) {
  3049. int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i);
  3050. csrow->channels[1]->dimm->nr_pages = row_dct1_pages;
  3051. nr_pages += row_dct1_pages;
  3052. }
  3053. edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);
  3054. /* Determine DIMM ECC mode: */
  3055. if (pvt->nbcfg & NBCFG_ECC_ENABLE) {
  3056. edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL)
  3057. ? EDAC_S4ECD4ED
  3058. : EDAC_SECDED;
  3059. }
  3060. for (j = 0; j < pvt->channel_count; j++) {
  3061. dimm = csrow->channels[j]->dimm;
  3062. dimm->mtype = pvt->dram_type;
  3063. dimm->edac_mode = edac_mode;
  3064. dimm->grain = 64;
  3065. }
  3066. }
  3067. return empty;
  3068. }
  3069. /* get all cores on this DCT */
  3070. static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid)
  3071. {
  3072. int cpu;
  3073. for_each_online_cpu(cpu)
  3074. if (topology_die_id(cpu) == nid)
  3075. cpumask_set_cpu(cpu, mask);
  3076. }
  3077. /* check MCG_CTL on all the cpus on this node */
  3078. static bool nb_mce_bank_enabled_on_node(u16 nid)
  3079. {
  3080. cpumask_var_t mask;
  3081. int cpu, nbe;
  3082. bool ret = false;
  3083. if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) {
  3084. amd64_warn("%s: Error allocating mask\n", __func__);
  3085. return false;
  3086. }
  3087. get_cpus_on_this_dct_cpumask(mask, nid);
  3088. rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs);
  3089. for_each_cpu(cpu, mask) {
  3090. struct msr *reg = per_cpu_ptr(msrs, cpu);
  3091. nbe = reg->l & MSR_MCGCTL_NBE;
  3092. edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
  3093. cpu, reg->q,
  3094. (nbe ? "enabled" : "disabled"));
  3095. if (!nbe)
  3096. goto out;
  3097. }
  3098. ret = true;
  3099. out:
  3100. free_cpumask_var(mask);
  3101. return ret;
  3102. }
  3103. static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on)
  3104. {
  3105. cpumask_var_t cmask;
  3106. int cpu;
  3107. if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
  3108. amd64_warn("%s: error allocating mask\n", __func__);
  3109. return -ENOMEM;
  3110. }
  3111. get_cpus_on_this_dct_cpumask(cmask, nid);
  3112. rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
  3113. for_each_cpu(cpu, cmask) {
  3114. struct msr *reg = per_cpu_ptr(msrs, cpu);
  3115. if (on) {
  3116. if (reg->l & MSR_MCGCTL_NBE)
  3117. s->flags.nb_mce_enable = 1;
  3118. reg->l |= MSR_MCGCTL_NBE;
  3119. } else {
  3120. /*
  3121. * Turn off NB MCE reporting only when it was off before
  3122. */
  3123. if (!s->flags.nb_mce_enable)
  3124. reg->l &= ~MSR_MCGCTL_NBE;
  3125. }
  3126. }
  3127. wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
  3128. free_cpumask_var(cmask);
  3129. return 0;
  3130. }
  3131. static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid,
  3132. struct pci_dev *F3)
  3133. {
  3134. bool ret = true;
  3135. u32 value, mask = 0x3; /* UECC/CECC enable */
  3136. if (toggle_ecc_err_reporting(s, nid, ON)) {
  3137. amd64_warn("Error enabling ECC reporting over MCGCTL!\n");
  3138. return false;
  3139. }
  3140. amd64_read_pci_cfg(F3, NBCTL, &value);
  3141. s->old_nbctl = value & mask;
  3142. s->nbctl_valid = true;
  3143. value |= mask;
  3144. amd64_write_pci_cfg(F3, NBCTL, value);
  3145. amd64_read_pci_cfg(F3, NBCFG, &value);
  3146. edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
  3147. nid, value, !!(value & NBCFG_ECC_ENABLE));
  3148. if (!(value & NBCFG_ECC_ENABLE)) {
  3149. amd64_warn("DRAM ECC disabled on this node, enabling...\n");
  3150. s->flags.nb_ecc_prev = 0;
  3151. /* Attempt to turn on DRAM ECC Enable */
  3152. value |= NBCFG_ECC_ENABLE;
  3153. amd64_write_pci_cfg(F3, NBCFG, value);
  3154. amd64_read_pci_cfg(F3, NBCFG, &value);
  3155. if (!(value & NBCFG_ECC_ENABLE)) {
  3156. amd64_warn("Hardware rejected DRAM ECC enable,"
  3157. "check memory DIMM configuration.\n");
  3158. ret = false;
  3159. } else {
  3160. amd64_info("Hardware accepted DRAM ECC Enable\n");
  3161. }
  3162. } else {
  3163. s->flags.nb_ecc_prev = 1;
  3164. }
  3165. edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
  3166. nid, value, !!(value & NBCFG_ECC_ENABLE));
  3167. return ret;
  3168. }
  3169. static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid,
  3170. struct pci_dev *F3)
  3171. {
  3172. u32 value, mask = 0x3; /* UECC/CECC enable */
  3173. if (!s->nbctl_valid)
  3174. return;
  3175. amd64_read_pci_cfg(F3, NBCTL, &value);
  3176. value &= ~mask;
  3177. value |= s->old_nbctl;
  3178. amd64_write_pci_cfg(F3, NBCTL, value);
  3179. /* restore previous BIOS DRAM ECC "off" setting we force-enabled */
  3180. if (!s->flags.nb_ecc_prev) {
  3181. amd64_read_pci_cfg(F3, NBCFG, &value);
  3182. value &= ~NBCFG_ECC_ENABLE;
  3183. amd64_write_pci_cfg(F3, NBCFG, value);
  3184. }
  3185. /* restore the NB Enable MCGCTL bit */
  3186. if (toggle_ecc_err_reporting(s, nid, OFF))
  3187. amd64_warn("Error restoring NB MCGCTL settings!\n");
  3188. }
  3189. static bool ecc_enabled(struct amd64_pvt *pvt)
  3190. {
  3191. u16 nid = pvt->mc_node_id;
  3192. bool nb_mce_en = false;
  3193. u8 ecc_en = 0, i;
  3194. u32 value;
  3195. if (boot_cpu_data.x86 >= 0x17) {
  3196. u8 umc_en_mask = 0, ecc_en_mask = 0;
  3197. struct amd64_umc *umc;
  3198. for_each_umc(i) {
  3199. umc = &pvt->umc[i];
  3200. /* Only check enabled UMCs. */
  3201. if (!(umc->sdp_ctrl & UMC_SDP_INIT))
  3202. continue;
  3203. umc_en_mask |= BIT(i);
  3204. if (umc->umc_cap_hi & UMC_ECC_ENABLED)
  3205. ecc_en_mask |= BIT(i);
  3206. }
  3207. /* Check whether at least one UMC is enabled: */
  3208. if (umc_en_mask)
  3209. ecc_en = umc_en_mask == ecc_en_mask;
  3210. else
  3211. edac_dbg(0, "Node %d: No enabled UMCs.\n", nid);
  3212. /* Assume UMC MCA banks are enabled. */
  3213. nb_mce_en = true;
  3214. } else {
  3215. amd64_read_pci_cfg(pvt->F3, NBCFG, &value);
  3216. ecc_en = !!(value & NBCFG_ECC_ENABLE);
  3217. nb_mce_en = nb_mce_bank_enabled_on_node(nid);
  3218. if (!nb_mce_en)
  3219. edac_dbg(0, "NB MCE bank disabled, set MSR 0x%08x[4] on node %d to enable.\n",
  3220. MSR_IA32_MCG_CTL, nid);
  3221. }
  3222. edac_dbg(3, "Node %d: DRAM ECC %s.\n", nid, (ecc_en ? "enabled" : "disabled"));
  3223. if (!ecc_en || !nb_mce_en)
  3224. return false;
  3225. else
  3226. return true;
  3227. }
  3228. static inline void
  3229. f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
  3230. {
  3231. u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1;
  3232. for_each_umc(i) {
  3233. if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
  3234. ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
  3235. cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
  3236. dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6));
  3237. dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));
  3238. }
  3239. }
  3240. /* Set chipkill only if ECC is enabled: */
  3241. if (ecc_en) {
  3242. mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
  3243. if (!cpk_en)
  3244. return;
  3245. if (dev_x4)
  3246. mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
  3247. else if (dev_x16)
  3248. mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED;
  3249. else
  3250. mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED;
  3251. }
  3252. }
  3253. static void setup_mci_misc_attrs(struct mem_ctl_info *mci)
  3254. {
  3255. struct amd64_pvt *pvt = mci->pvt_info;
  3256. mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2;
  3257. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  3258. if (pvt->umc) {
  3259. f17h_determine_edac_ctl_cap(mci, pvt);
  3260. } else {
  3261. if (pvt->nbcap & NBCAP_SECDED)
  3262. mci->edac_ctl_cap |= EDAC_FLAG_SECDED;
  3263. if (pvt->nbcap & NBCAP_CHIPKILL)
  3264. mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED;
  3265. }
  3266. mci->edac_cap = determine_edac_cap(pvt);
  3267. mci->mod_name = EDAC_MOD_STR;
  3268. mci->ctl_name = fam_type->ctl_name;
  3269. mci->dev_name = pci_name(pvt->F3);
  3270. mci->ctl_page_to_phys = NULL;
  3271. /* memory scrubber interface */
  3272. mci->set_sdram_scrub_rate = set_scrub_rate;
  3273. mci->get_sdram_scrub_rate = get_scrub_rate;
  3274. }
  3275. /*
  3276. * returns a pointer to the family descriptor on success, NULL otherwise.
  3277. */
  3278. static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
  3279. {
  3280. pvt->ext_model = boot_cpu_data.x86_model >> 4;
  3281. pvt->stepping = boot_cpu_data.x86_stepping;
  3282. pvt->model = boot_cpu_data.x86_model;
  3283. pvt->fam = boot_cpu_data.x86;
  3284. switch (pvt->fam) {
  3285. case 0xf:
  3286. fam_type = &family_types[K8_CPUS];
  3287. pvt->ops = &family_types[K8_CPUS].ops;
  3288. break;
  3289. case 0x10:
  3290. fam_type = &family_types[F10_CPUS];
  3291. pvt->ops = &family_types[F10_CPUS].ops;
  3292. break;
  3293. case 0x15:
  3294. if (pvt->model == 0x30) {
  3295. fam_type = &family_types[F15_M30H_CPUS];
  3296. pvt->ops = &family_types[F15_M30H_CPUS].ops;
  3297. break;
  3298. } else if (pvt->model == 0x60) {
  3299. fam_type = &family_types[F15_M60H_CPUS];
  3300. pvt->ops = &family_types[F15_M60H_CPUS].ops;
  3301. break;
  3302. /* Richland is only client */
  3303. } else if (pvt->model == 0x13) {
  3304. return NULL;
  3305. } else {
  3306. fam_type = &family_types[F15_CPUS];
  3307. pvt->ops = &family_types[F15_CPUS].ops;
  3308. }
  3309. break;
  3310. case 0x16:
  3311. if (pvt->model == 0x30) {
  3312. fam_type = &family_types[F16_M30H_CPUS];
  3313. pvt->ops = &family_types[F16_M30H_CPUS].ops;
  3314. break;
  3315. }
  3316. fam_type = &family_types[F16_CPUS];
  3317. pvt->ops = &family_types[F16_CPUS].ops;
  3318. break;
  3319. case 0x17:
  3320. if (pvt->model >= 0x10 && pvt->model <= 0x2f) {
  3321. fam_type = &family_types[F17_M10H_CPUS];
  3322. pvt->ops = &family_types[F17_M10H_CPUS].ops;
  3323. break;
  3324. } else if (pvt->model >= 0x30 && pvt->model <= 0x3f) {
  3325. fam_type = &family_types[F17_M30H_CPUS];
  3326. pvt->ops = &family_types[F17_M30H_CPUS].ops;
  3327. break;
  3328. } else if (pvt->model >= 0x60 && pvt->model <= 0x6f) {
  3329. fam_type = &family_types[F17_M60H_CPUS];
  3330. pvt->ops = &family_types[F17_M60H_CPUS].ops;
  3331. break;
  3332. } else if (pvt->model >= 0x70 && pvt->model <= 0x7f) {
  3333. fam_type = &family_types[F17_M70H_CPUS];
  3334. pvt->ops = &family_types[F17_M70H_CPUS].ops;
  3335. break;
  3336. }
  3337. fallthrough;
  3338. case 0x18:
  3339. fam_type = &family_types[F17_CPUS];
  3340. pvt->ops = &family_types[F17_CPUS].ops;
  3341. if (pvt->fam == 0x18)
  3342. family_types[F17_CPUS].ctl_name = "F18h";
  3343. break;
  3344. case 0x19:
  3345. if (pvt->model >= 0x10 && pvt->model <= 0x1f) {
  3346. fam_type = &family_types[F19_M10H_CPUS];
  3347. pvt->ops = &family_types[F19_M10H_CPUS].ops;
  3348. break;
  3349. } else if (pvt->model >= 0x20 && pvt->model <= 0x2f) {
  3350. fam_type = &family_types[F17_M70H_CPUS];
  3351. pvt->ops = &family_types[F17_M70H_CPUS].ops;
  3352. fam_type->ctl_name = "F19h_M20h";
  3353. break;
  3354. } else if (pvt->model >= 0x50 && pvt->model <= 0x5f) {
  3355. fam_type = &family_types[F19_M50H_CPUS];
  3356. pvt->ops = &family_types[F19_M50H_CPUS].ops;
  3357. fam_type->ctl_name = "F19h_M50h";
  3358. break;
  3359. } else if (pvt->model >= 0xa0 && pvt->model <= 0xaf) {
  3360. fam_type = &family_types[F19_M10H_CPUS];
  3361. pvt->ops = &family_types[F19_M10H_CPUS].ops;
  3362. fam_type->ctl_name = "F19h_MA0h";
  3363. break;
  3364. }
  3365. fam_type = &family_types[F19_CPUS];
  3366. pvt->ops = &family_types[F19_CPUS].ops;
  3367. family_types[F19_CPUS].ctl_name = "F19h";
  3368. break;
  3369. default:
  3370. amd64_err("Unsupported family!\n");
  3371. return NULL;
  3372. }
  3373. return fam_type;
  3374. }
  3375. static const struct attribute_group *amd64_edac_attr_groups[] = {
  3376. #ifdef CONFIG_EDAC_DEBUG
  3377. &dbg_group,
  3378. &inj_group,
  3379. #endif
  3380. NULL
  3381. };
  3382. static int hw_info_get(struct amd64_pvt *pvt)
  3383. {
  3384. u16 pci_id1, pci_id2;
  3385. int ret;
  3386. if (pvt->fam >= 0x17) {
  3387. pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL);
  3388. if (!pvt->umc)
  3389. return -ENOMEM;
  3390. pci_id1 = fam_type->f0_id;
  3391. pci_id2 = fam_type->f6_id;
  3392. } else {
  3393. pci_id1 = fam_type->f1_id;
  3394. pci_id2 = fam_type->f2_id;
  3395. }
  3396. ret = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2);
  3397. if (ret)
  3398. return ret;
  3399. read_mc_regs(pvt);
  3400. return 0;
  3401. }
  3402. static void hw_info_put(struct amd64_pvt *pvt)
  3403. {
  3404. if (pvt->F0 || pvt->F1)
  3405. free_mc_sibling_devs(pvt);
  3406. kfree(pvt->umc);
  3407. }
  3408. static int init_one_instance(struct amd64_pvt *pvt)
  3409. {
  3410. struct mem_ctl_info *mci = NULL;
  3411. struct edac_mc_layer layers[2];
  3412. int ret = -EINVAL;
  3413. /*
  3414. * We need to determine how many memory channels there are. Then use
  3415. * that information for calculating the size of the dynamic instance
  3416. * tables in the 'mci' structure.
  3417. */
  3418. pvt->channel_count = pvt->ops->early_channel_count(pvt);
  3419. if (pvt->channel_count < 0)
  3420. return ret;
  3421. ret = -ENOMEM;
  3422. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  3423. layers[0].size = pvt->csels[0].b_cnt;
  3424. layers[0].is_virt_csrow = true;
  3425. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  3426. /*
  3427. * Always allocate two channels since we can have setups with DIMMs on
  3428. * only one channel. Also, this simplifies handling later for the price
  3429. * of a couple of KBs tops.
  3430. */
  3431. layers[1].size = fam_type->max_mcs;
  3432. layers[1].is_virt_csrow = false;
  3433. mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0);
  3434. if (!mci)
  3435. return ret;
  3436. mci->pvt_info = pvt;
  3437. mci->pdev = &pvt->F3->dev;
  3438. setup_mci_misc_attrs(mci);
  3439. if (init_csrows(mci))
  3440. mci->edac_cap = EDAC_FLAG_NONE;
  3441. ret = -ENODEV;
  3442. if (edac_mc_add_mc_with_groups(mci, amd64_edac_attr_groups)) {
  3443. edac_dbg(1, "failed edac_mc_add_mc()\n");
  3444. edac_mc_free(mci);
  3445. return ret;
  3446. }
  3447. return 0;
  3448. }
  3449. static bool instance_has_memory(struct amd64_pvt *pvt)
  3450. {
  3451. bool cs_enabled = false;
  3452. int cs = 0, dct = 0;
  3453. for (dct = 0; dct < fam_type->max_mcs; dct++) {
  3454. for_each_chip_select(cs, dct, pvt)
  3455. cs_enabled |= csrow_enabled(cs, dct, pvt);
  3456. }
  3457. return cs_enabled;
  3458. }
  3459. static int probe_one_instance(unsigned int nid)
  3460. {
  3461. struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
  3462. struct amd64_pvt *pvt = NULL;
  3463. struct ecc_settings *s;
  3464. int ret;
  3465. ret = -ENOMEM;
  3466. s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL);
  3467. if (!s)
  3468. goto err_out;
  3469. ecc_stngs[nid] = s;
  3470. pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
  3471. if (!pvt)
  3472. goto err_settings;
  3473. pvt->mc_node_id = nid;
  3474. pvt->F3 = F3;
  3475. ret = -ENODEV;
  3476. fam_type = per_family_init(pvt);
  3477. if (!fam_type)
  3478. goto err_enable;
  3479. ret = hw_info_get(pvt);
  3480. if (ret < 0)
  3481. goto err_enable;
  3482. ret = 0;
  3483. if (!instance_has_memory(pvt)) {
  3484. amd64_info("Node %d: No DIMMs detected.\n", nid);
  3485. goto err_enable;
  3486. }
  3487. if (!ecc_enabled(pvt)) {
  3488. ret = -ENODEV;
  3489. if (!ecc_enable_override)
  3490. goto err_enable;
  3491. if (boot_cpu_data.x86 >= 0x17) {
  3492. amd64_warn("Forcing ECC on is not recommended on newer systems. Please enable ECC in BIOS.");
  3493. goto err_enable;
  3494. } else
  3495. amd64_warn("Forcing ECC on!\n");
  3496. if (!enable_ecc_error_reporting(s, nid, F3))
  3497. goto err_enable;
  3498. }
  3499. ret = init_one_instance(pvt);
  3500. if (ret < 0) {
  3501. amd64_err("Error probing instance: %d\n", nid);
  3502. if (boot_cpu_data.x86 < 0x17)
  3503. restore_ecc_error_reporting(s, nid, F3);
  3504. goto err_enable;
  3505. }
  3506. amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name,
  3507. (pvt->fam == 0xf ?
  3508. (pvt->ext_model >= K8_REV_F ? "revF or later "
  3509. : "revE or earlier ")
  3510. : ""), pvt->mc_node_id);
  3511. dump_misc_regs(pvt);
  3512. return ret;
  3513. err_enable:
  3514. hw_info_put(pvt);
  3515. kfree(pvt);
  3516. err_settings:
  3517. kfree(s);
  3518. ecc_stngs[nid] = NULL;
  3519. err_out:
  3520. return ret;
  3521. }
  3522. static void remove_one_instance(unsigned int nid)
  3523. {
  3524. struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
  3525. struct ecc_settings *s = ecc_stngs[nid];
  3526. struct mem_ctl_info *mci;
  3527. struct amd64_pvt *pvt;
  3528. /* Remove from EDAC CORE tracking list */
  3529. mci = edac_mc_del_mc(&F3->dev);
  3530. if (!mci)
  3531. return;
  3532. pvt = mci->pvt_info;
  3533. restore_ecc_error_reporting(s, nid, F3);
  3534. kfree(ecc_stngs[nid]);
  3535. ecc_stngs[nid] = NULL;
  3536. /* Free the EDAC CORE resources */
  3537. mci->pvt_info = NULL;
  3538. hw_info_put(pvt);
  3539. kfree(pvt);
  3540. edac_mc_free(mci);
  3541. }
  3542. static void setup_pci_device(void)
  3543. {
  3544. if (pci_ctl)
  3545. return;
  3546. pci_ctl = edac_pci_create_generic_ctl(pci_ctl_dev, EDAC_MOD_STR);
  3547. if (!pci_ctl) {
  3548. pr_warn("%s(): Unable to create PCI control\n", __func__);
  3549. pr_warn("%s(): PCI error report via EDAC not set\n", __func__);
  3550. }
  3551. }
  3552. static const struct x86_cpu_id amd64_cpuids[] = {
  3553. X86_MATCH_VENDOR_FAM(AMD, 0x0F, NULL),
  3554. X86_MATCH_VENDOR_FAM(AMD, 0x10, NULL),
  3555. X86_MATCH_VENDOR_FAM(AMD, 0x15, NULL),
  3556. X86_MATCH_VENDOR_FAM(AMD, 0x16, NULL),
  3557. X86_MATCH_VENDOR_FAM(AMD, 0x17, NULL),
  3558. X86_MATCH_VENDOR_FAM(HYGON, 0x18, NULL),
  3559. X86_MATCH_VENDOR_FAM(AMD, 0x19, NULL),
  3560. { }
  3561. };
  3562. MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);
  3563. static int __init amd64_edac_init(void)
  3564. {
  3565. const char *owner;
  3566. int err = -ENODEV;
  3567. int i;
  3568. owner = edac_get_owner();
  3569. if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
  3570. return -EBUSY;
  3571. if (!x86_match_cpu(amd64_cpuids))
  3572. return -ENODEV;
  3573. if (!amd_nb_num())
  3574. return -ENODEV;
  3575. opstate_init();
  3576. err = -ENOMEM;
  3577. ecc_stngs = kcalloc(amd_nb_num(), sizeof(ecc_stngs[0]), GFP_KERNEL);
  3578. if (!ecc_stngs)
  3579. goto err_free;
  3580. msrs = msrs_alloc();
  3581. if (!msrs)
  3582. goto err_free;
  3583. for (i = 0; i < amd_nb_num(); i++) {
  3584. err = probe_one_instance(i);
  3585. if (err) {
  3586. /* unwind properly */
  3587. while (--i >= 0)
  3588. remove_one_instance(i);
  3589. goto err_pci;
  3590. }
  3591. }
  3592. if (!edac_has_mcs()) {
  3593. err = -ENODEV;
  3594. goto err_pci;
  3595. }
  3596. /* register stuff with EDAC MCE */
  3597. if (boot_cpu_data.x86 >= 0x17)
  3598. amd_register_ecc_decoder(decode_umc_error);
  3599. else
  3600. amd_register_ecc_decoder(decode_bus_error);
  3601. setup_pci_device();
  3602. #ifdef CONFIG_X86_32
  3603. amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR);
  3604. #endif
  3605. printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);
  3606. return 0;
  3607. err_pci:
  3608. pci_ctl_dev = NULL;
  3609. msrs_free(msrs);
  3610. msrs = NULL;
  3611. err_free:
  3612. kfree(ecc_stngs);
  3613. ecc_stngs = NULL;
  3614. return err;
  3615. }
  3616. static void __exit amd64_edac_exit(void)
  3617. {
  3618. int i;
  3619. if (pci_ctl)
  3620. edac_pci_release_generic_ctl(pci_ctl);
  3621. /* unregister from EDAC MCE */
  3622. if (boot_cpu_data.x86 >= 0x17)
  3623. amd_unregister_ecc_decoder(decode_umc_error);
  3624. else
  3625. amd_unregister_ecc_decoder(decode_bus_error);
  3626. for (i = 0; i < amd_nb_num(); i++)
  3627. remove_one_instance(i);
  3628. kfree(ecc_stngs);
  3629. ecc_stngs = NULL;
  3630. pci_ctl_dev = NULL;
  3631. msrs_free(msrs);
  3632. msrs = NULL;
  3633. }
  3634. module_init(amd64_edac_init);
  3635. module_exit(amd64_edac_exit);
  3636. MODULE_LICENSE("GPL");
  3637. MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, "
  3638. "Dave Peterson, Thayne Harbaugh");
  3639. MODULE_DESCRIPTION("MC support for AMD64 memory controllers - "
  3640. EDAC_AMD64_VERSION);
  3641. module_param(edac_op_state, int, 0444);
  3642. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");