Kconfig 4.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menuconfig CXL_BUS
  3. tristate "CXL (Compute Express Link) Devices Support"
  4. depends on PCI
  5. select PCI_DOE
  6. help
  7. CXL is a bus that is electrically compatible with PCI Express, but
  8. layers three protocols on that signalling (CXL.io, CXL.cache, and
  9. CXL.mem). The CXL.cache protocol allows devices to hold cachelines
  10. locally, the CXL.mem protocol allows devices to be fully coherent
  11. memory targets, the CXL.io protocol is equivalent to PCI Express.
  12. Say 'y' to enable support for the configuration and management of
  13. devices supporting these protocols.
  14. if CXL_BUS
  15. config CXL_PCI
  16. tristate "PCI manageability"
  17. default CXL_BUS
  18. help
  19. The CXL specification defines a "CXL memory device" sub-class in the
  20. PCI "memory controller" base class of devices. Device's identified by
  21. this class code provide support for volatile and / or persistent
  22. memory to be mapped into the system address map (Host-managed Device
  23. Memory (HDM)).
  24. Say 'y/m' to enable a driver that will attach to CXL memory expander
  25. devices enumerated by the memory device class code for configuration
  26. and management primarily via the mailbox interface. See Chapter 2.3
  27. Type 3 CXL Device in the CXL 2.0 specification for more details.
  28. If unsure say 'm'.
  29. config CXL_MEM_RAW_COMMANDS
  30. bool "RAW Command Interface for Memory Devices"
  31. depends on CXL_PCI
  32. help
  33. Enable CXL RAW command interface.
  34. The CXL driver ioctl interface may assign a kernel ioctl command
  35. number for each specification defined opcode. At any given point in
  36. time the number of opcodes that the specification defines and a device
  37. may implement may exceed the kernel's set of associated ioctl function
  38. numbers. The mismatch is either by omission, specification is too new,
  39. or by design. When prototyping new hardware, or developing / debugging
  40. the driver it is useful to be able to submit any possible command to
  41. the hardware, even commands that may crash the kernel due to their
  42. potential impact to memory currently in use by the kernel.
  43. If developing CXL hardware or the driver say Y, otherwise say N.
  44. config CXL_ACPI
  45. tristate "CXL ACPI: Platform Support"
  46. depends on ACPI
  47. default CXL_BUS
  48. select ACPI_TABLE_LIB
  49. help
  50. Enable support for host managed device memory (HDM) resources
  51. published by a platform's ACPI CXL memory layout description. See
  52. Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
  53. specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
  54. (https://www.computeexpresslink.org/spec-landing). The CXL core
  55. consumes these resource to publish the root of a cxl_port decode
  56. hierarchy to map regions that represent System RAM, or Persistent
  57. Memory regions to be managed by LIBNVDIMM.
  58. If unsure say 'm'.
  59. config CXL_PMEM
  60. tristate "CXL PMEM: Persistent Memory Support"
  61. depends on LIBNVDIMM
  62. default CXL_BUS
  63. help
  64. In addition to typical memory resources a platform may also advertise
  65. support for persistent memory attached via CXL. This support is
  66. managed via a bridge driver from CXL to the LIBNVDIMM system
  67. subsystem. Say 'y/m' to enable support for enumerating and
  68. provisioning the persistent memory capacity of CXL memory expanders.
  69. If unsure say 'm'.
  70. config CXL_MEM
  71. tristate "CXL: Memory Expansion"
  72. depends on CXL_PCI
  73. default CXL_BUS
  74. help
  75. The CXL.mem protocol allows a device to act as a provider of "System
  76. RAM" and/or "Persistent Memory" that is fully coherent as if the
  77. memory were attached to the typical CPU memory controller. This is
  78. known as HDM "Host-managed Device Memory".
  79. Say 'y/m' to enable a driver that will attach to CXL.mem devices for
  80. memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
  81. specification for a detailed description of HDM.
  82. If unsure say 'm'.
  83. config CXL_PORT
  84. default CXL_BUS
  85. tristate
  86. config CXL_SUSPEND
  87. def_bool y
  88. depends on SUSPEND && CXL_MEM
  89. config CXL_REGION
  90. bool
  91. default CXL_BUS
  92. # For MAX_PHYSMEM_BITS
  93. depends on SPARSEMEM
  94. select MEMREGION
  95. select GET_FREE_REGION
  96. endif