timer-gx6605s.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
  3. #include <linux/init.h>
  4. #include <linux/interrupt.h>
  5. #include <linux/sched_clock.h>
  6. #include "timer-of.h"
  7. #define CLKSRC_OFFSET 0x40
  8. #define TIMER_STATUS 0x00
  9. #define TIMER_VALUE 0x04
  10. #define TIMER_CONTRL 0x10
  11. #define TIMER_CONFIG 0x20
  12. #define TIMER_DIV 0x24
  13. #define TIMER_INI 0x28
  14. #define GX6605S_STATUS_CLR BIT(0)
  15. #define GX6605S_CONTRL_RST BIT(0)
  16. #define GX6605S_CONTRL_START BIT(1)
  17. #define GX6605S_CONFIG_EN BIT(0)
  18. #define GX6605S_CONFIG_IRQ_EN BIT(1)
  19. static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
  20. {
  21. struct clock_event_device *ce = dev;
  22. void __iomem *base = timer_of_base(to_timer_of(ce));
  23. writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
  24. writel_relaxed(0, base + TIMER_INI);
  25. ce->event_handler(ce);
  26. return IRQ_HANDLED;
  27. }
  28. static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
  29. {
  30. void __iomem *base = timer_of_base(to_timer_of(ce));
  31. /* reset and stop counter */
  32. writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
  33. /* enable with irq and start */
  34. writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN,
  35. base + TIMER_CONFIG);
  36. return 0;
  37. }
  38. static int gx6605s_timer_set_next_event(unsigned long delta,
  39. struct clock_event_device *ce)
  40. {
  41. void __iomem *base = timer_of_base(to_timer_of(ce));
  42. /* use reset to pause timer */
  43. writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
  44. /* config next timeout value */
  45. writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
  46. writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
  47. return 0;
  48. }
  49. static int gx6605s_timer_shutdown(struct clock_event_device *ce)
  50. {
  51. void __iomem *base = timer_of_base(to_timer_of(ce));
  52. writel_relaxed(0, base + TIMER_CONTRL);
  53. writel_relaxed(0, base + TIMER_CONFIG);
  54. return 0;
  55. }
  56. static struct timer_of to = {
  57. .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
  58. .clkevt = {
  59. .rating = 300,
  60. .features = CLOCK_EVT_FEAT_DYNIRQ |
  61. CLOCK_EVT_FEAT_ONESHOT,
  62. .set_state_shutdown = gx6605s_timer_shutdown,
  63. .set_state_oneshot = gx6605s_timer_set_oneshot,
  64. .set_next_event = gx6605s_timer_set_next_event,
  65. .cpumask = cpu_possible_mask,
  66. },
  67. .of_irq = {
  68. .handler = gx6605s_timer_interrupt,
  69. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  70. },
  71. };
  72. static u64 notrace gx6605s_sched_clock_read(void)
  73. {
  74. void __iomem *base;
  75. base = timer_of_base(&to) + CLKSRC_OFFSET;
  76. return (u64)readl_relaxed(base + TIMER_VALUE);
  77. }
  78. static void gx6605s_clkevt_init(void __iomem *base)
  79. {
  80. writel_relaxed(0, base + TIMER_DIV);
  81. writel_relaxed(0, base + TIMER_CONFIG);
  82. clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2,
  83. ULONG_MAX);
  84. }
  85. static int gx6605s_clksrc_init(void __iomem *base)
  86. {
  87. writel_relaxed(0, base + TIMER_DIV);
  88. writel_relaxed(0, base + TIMER_INI);
  89. writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
  90. writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
  91. writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
  92. sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to));
  93. return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s",
  94. timer_of_rate(&to), 200, 32, clocksource_mmio_readl_up);
  95. }
  96. static int __init gx6605s_timer_init(struct device_node *np)
  97. {
  98. int ret;
  99. /*
  100. * The timer driver is for nationalchip gx6605s SOC and there are two
  101. * same timer in gx6605s. We use one for clkevt and another for clksrc.
  102. *
  103. * The timer is mmio map to access, so we need give mmio address in dts.
  104. *
  105. * It provides a 32bit countup timer and interrupt will be caused by
  106. * count-overflow.
  107. * So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
  108. *
  109. * The counter at 0x0 offset is clock event.
  110. * The counter at 0x40 offset is clock source.
  111. * They are the same in hardware, just different used by driver.
  112. */
  113. ret = timer_of_init(np, &to);
  114. if (ret)
  115. return ret;
  116. gx6605s_clkevt_init(timer_of_base(&to));
  117. return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);
  118. }
  119. TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init);