dpll3xxx.c 29 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP3/4 - specific DPLL control functions
  4. *
  5. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  6. * Copyright (C) 2009-2010 Nokia Corporation
  7. *
  8. * Written by Paul Walmsley
  9. * Testing and integration fixes by Jouni Högander
  10. *
  11. * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
  12. * Menon
  13. *
  14. * Parts of this code are based on code written by
  15. * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/device.h>
  19. #include <linux/list.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/io.h>
  24. #include <linux/bitops.h>
  25. #include <linux/clkdev.h>
  26. #include <linux/clk/ti.h>
  27. #include "clock.h"
  28. /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
  29. #define DPLL_AUTOIDLE_DISABLE 0x0
  30. #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
  31. #define MAX_DPLL_WAIT_TRIES 1000000
  32. #define OMAP3XXX_EN_DPLL_LOCKED 0x7
  33. /* Forward declarations */
  34. static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
  35. static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
  36. static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
  37. /* Private functions */
  38. /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
  39. static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
  40. {
  41. const struct dpll_data *dd;
  42. u32 v;
  43. dd = clk->dpll_data;
  44. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  45. v &= ~dd->enable_mask;
  46. v |= clken_bits << __ffs(dd->enable_mask);
  47. ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
  48. }
  49. /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
  50. static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
  51. {
  52. const struct dpll_data *dd;
  53. int i = 0;
  54. int ret = -EINVAL;
  55. const char *clk_name;
  56. dd = clk->dpll_data;
  57. clk_name = clk_hw_get_name(&clk->hw);
  58. state <<= __ffs(dd->idlest_mask);
  59. while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
  60. != state) && i < MAX_DPLL_WAIT_TRIES) {
  61. i++;
  62. udelay(1);
  63. }
  64. if (i == MAX_DPLL_WAIT_TRIES) {
  65. pr_err("clock: %s failed transition to '%s'\n",
  66. clk_name, (state) ? "locked" : "bypassed");
  67. } else {
  68. pr_debug("clock: %s transition to '%s' in %d loops\n",
  69. clk_name, (state) ? "locked" : "bypassed", i);
  70. ret = 0;
  71. }
  72. return ret;
  73. }
  74. /* From 3430 TRM ES2 4.7.6.2 */
  75. static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
  76. {
  77. unsigned long fint;
  78. u16 f = 0;
  79. fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n;
  80. pr_debug("clock: fint is %lu\n", fint);
  81. if (fint >= 750000 && fint <= 1000000)
  82. f = 0x3;
  83. else if (fint > 1000000 && fint <= 1250000)
  84. f = 0x4;
  85. else if (fint > 1250000 && fint <= 1500000)
  86. f = 0x5;
  87. else if (fint > 1500000 && fint <= 1750000)
  88. f = 0x6;
  89. else if (fint > 1750000 && fint <= 2100000)
  90. f = 0x7;
  91. else if (fint > 7500000 && fint <= 10000000)
  92. f = 0xB;
  93. else if (fint > 10000000 && fint <= 12500000)
  94. f = 0xC;
  95. else if (fint > 12500000 && fint <= 15000000)
  96. f = 0xD;
  97. else if (fint > 15000000 && fint <= 17500000)
  98. f = 0xE;
  99. else if (fint > 17500000 && fint <= 21000000)
  100. f = 0xF;
  101. else
  102. pr_debug("clock: unknown freqsel setting for %d\n", n);
  103. return f;
  104. }
  105. /**
  106. * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
  107. * @clk: pointer to a DPLL struct clk
  108. *
  109. * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
  110. * readiness before returning. Will save and restore the DPLL's
  111. * autoidle state across the enable, per the CDP code. If the DPLL
  112. * locked successfully, return 0; if the DPLL did not lock in the time
  113. * allotted, or DPLL3 was passed in, return -EINVAL.
  114. */
  115. static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
  116. {
  117. const struct dpll_data *dd;
  118. u8 ai;
  119. u8 state = 1;
  120. int r = 0;
  121. pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
  122. dd = clk->dpll_data;
  123. state <<= __ffs(dd->idlest_mask);
  124. /* Check if already locked */
  125. if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
  126. state)
  127. goto done;
  128. ai = omap3_dpll_autoidle_read(clk);
  129. if (ai)
  130. omap3_dpll_deny_idle(clk);
  131. _omap3_dpll_write_clken(clk, DPLL_LOCKED);
  132. r = _omap3_wait_dpll_status(clk, 1);
  133. if (ai)
  134. omap3_dpll_allow_idle(clk);
  135. done:
  136. return r;
  137. }
  138. /**
  139. * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
  140. * @clk: pointer to a DPLL struct clk
  141. *
  142. * Instructs a non-CORE DPLL to enter low-power bypass mode. In
  143. * bypass mode, the DPLL's rate is set equal to its parent clock's
  144. * rate. Waits for the DPLL to report readiness before returning.
  145. * Will save and restore the DPLL's autoidle state across the enable,
  146. * per the CDP code. If the DPLL entered bypass mode successfully,
  147. * return 0; if the DPLL did not enter bypass in the time allotted, or
  148. * DPLL3 was passed in, or the DPLL does not support low-power bypass,
  149. * return -EINVAL.
  150. */
  151. static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
  152. {
  153. int r;
  154. u8 ai;
  155. if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
  156. return -EINVAL;
  157. pr_debug("clock: configuring DPLL %s for low-power bypass\n",
  158. clk_hw_get_name(&clk->hw));
  159. ai = omap3_dpll_autoidle_read(clk);
  160. _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
  161. r = _omap3_wait_dpll_status(clk, 0);
  162. if (ai)
  163. omap3_dpll_allow_idle(clk);
  164. return r;
  165. }
  166. /**
  167. * _omap3_noncore_dpll_stop - instruct a DPLL to stop
  168. * @clk: pointer to a DPLL struct clk
  169. *
  170. * Instructs a non-CORE DPLL to enter low-power stop. Will save and
  171. * restore the DPLL's autoidle state across the stop, per the CDP
  172. * code. If DPLL3 was passed in, or the DPLL does not support
  173. * low-power stop, return -EINVAL; otherwise, return 0.
  174. */
  175. static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
  176. {
  177. u8 ai;
  178. if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
  179. return -EINVAL;
  180. pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
  181. ai = omap3_dpll_autoidle_read(clk);
  182. _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
  183. if (ai)
  184. omap3_dpll_allow_idle(clk);
  185. return 0;
  186. }
  187. /**
  188. * _lookup_dco - Lookup DCO used by j-type DPLL
  189. * @clk: pointer to a DPLL struct clk
  190. * @dco: digital control oscillator selector
  191. * @m: DPLL multiplier to set
  192. * @n: DPLL divider to set
  193. *
  194. * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
  195. *
  196. * XXX This code is not needed for 3430/AM35xx; can it be optimized
  197. * out in non-multi-OMAP builds for those chips?
  198. */
  199. static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
  200. {
  201. unsigned long fint, clkinp; /* watch out for overflow */
  202. clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
  203. fint = (clkinp / n) * m;
  204. if (fint < 1000000000)
  205. *dco = 2;
  206. else
  207. *dco = 4;
  208. }
  209. /**
  210. * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
  211. * @clk: pointer to a DPLL struct clk
  212. * @sd_div: target sigma-delta divider
  213. * @m: DPLL multiplier to set
  214. * @n: DPLL divider to set
  215. *
  216. * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
  217. *
  218. * XXX This code is not needed for 3430/AM35xx; can it be optimized
  219. * out in non-multi-OMAP builds for those chips?
  220. */
  221. static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
  222. {
  223. unsigned long clkinp, sd; /* watch out for overflow */
  224. int mod1, mod2;
  225. clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
  226. /*
  227. * target sigma-delta to near 250MHz
  228. * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
  229. */
  230. clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
  231. mod1 = (clkinp * m) % (250 * n);
  232. sd = (clkinp * m) / (250 * n);
  233. mod2 = sd % 10;
  234. sd /= 10;
  235. if (mod1 || mod2)
  236. sd++;
  237. *sd_div = sd;
  238. }
  239. /**
  240. * omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers
  241. * @clk: struct clk * of DPLL to set
  242. *
  243. * Enable the DPLL spread spectrum clocking if frequency modulation and
  244. * frequency spreading have been set, otherwise disable it.
  245. */
  246. static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)
  247. {
  248. struct dpll_data *dd = clk->dpll_data;
  249. unsigned long ref_rate;
  250. u32 v, ctrl, mod_freq_divider, exponent, mantissa;
  251. u32 deltam_step, deltam_ceil;
  252. ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  253. if (dd->ssc_modfreq && dd->ssc_deltam) {
  254. ctrl |= dd->ssc_enable_mask;
  255. if (dd->ssc_downspread)
  256. ctrl |= dd->ssc_downspread_mask;
  257. else
  258. ctrl &= ~dd->ssc_downspread_mask;
  259. ref_rate = clk_hw_get_rate(dd->clk_ref);
  260. mod_freq_divider =
  261. (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq);
  262. if (dd->ssc_modfreq > (ref_rate / 70))
  263. pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n",
  264. __clk_get_name(clk->hw.clk), ref_rate / 70);
  265. exponent = 0;
  266. mantissa = mod_freq_divider;
  267. while ((mantissa > 127) && (exponent < 7)) {
  268. exponent++;
  269. mantissa /= 2;
  270. }
  271. if (mantissa > 127)
  272. mantissa = 127;
  273. v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
  274. v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask);
  275. v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask);
  276. v |= exponent << __ffs(dd->ssc_modfreq_exp_mask);
  277. ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
  278. deltam_step = dd->last_rounded_m * dd->ssc_deltam;
  279. deltam_step /= 10;
  280. if (dd->ssc_downspread)
  281. deltam_step /= 2;
  282. deltam_step <<= __ffs(dd->ssc_deltam_int_mask);
  283. deltam_step /= 100;
  284. deltam_step /= mod_freq_divider;
  285. if (deltam_step > 0xFFFFF)
  286. deltam_step = 0xFFFFF;
  287. deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >>
  288. __ffs(dd->ssc_deltam_int_mask);
  289. if (deltam_step & dd->ssc_deltam_frac_mask)
  290. deltam_ceil++;
  291. if ((dd->ssc_downspread &&
  292. ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 ||
  293. dd->last_rounded_m > 2045)) ||
  294. ((dd->last_rounded_m - deltam_ceil) < 20 ||
  295. (dd->last_rounded_m + deltam_ceil) > 2045))
  296. pr_warn("clock: SSC multiplier of DPLL %s is out of range\n",
  297. __clk_get_name(clk->hw.clk));
  298. v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
  299. v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask);
  300. v |= deltam_step << __ffs(dd->ssc_deltam_int_mask |
  301. dd->ssc_deltam_frac_mask);
  302. ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
  303. } else {
  304. ctrl &= ~dd->ssc_enable_mask;
  305. }
  306. ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
  307. }
  308. /**
  309. * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
  310. * @clk: struct clk * of DPLL to set
  311. * @freqsel: FREQSEL value to set
  312. *
  313. * Program the DPLL with the last M, N values calculated, and wait for
  314. * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
  315. */
  316. static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
  317. {
  318. struct dpll_data *dd = clk->dpll_data;
  319. u8 dco, sd_div, ai = 0;
  320. u32 v;
  321. bool errata_i810;
  322. /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
  323. _omap3_noncore_dpll_bypass(clk);
  324. /*
  325. * Set jitter correction. Jitter correction applicable for OMAP343X
  326. * only since freqsel field is no longer present on other devices.
  327. */
  328. if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
  329. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  330. v &= ~dd->freqsel_mask;
  331. v |= freqsel << __ffs(dd->freqsel_mask);
  332. ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
  333. }
  334. /* Set DPLL multiplier, divider */
  335. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  336. /* Handle Duty Cycle Correction */
  337. if (dd->dcc_mask) {
  338. if (dd->last_rounded_rate >= dd->dcc_rate)
  339. v |= dd->dcc_mask; /* Enable DCC */
  340. else
  341. v &= ~dd->dcc_mask; /* Disable DCC */
  342. }
  343. v &= ~(dd->mult_mask | dd->div1_mask);
  344. v |= dd->last_rounded_m << __ffs(dd->mult_mask);
  345. v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
  346. /* Configure dco and sd_div for dplls that have these fields */
  347. if (dd->dco_mask) {
  348. _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
  349. v &= ~(dd->dco_mask);
  350. v |= dco << __ffs(dd->dco_mask);
  351. }
  352. if (dd->sddiv_mask) {
  353. _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
  354. dd->last_rounded_n);
  355. v &= ~(dd->sddiv_mask);
  356. v |= sd_div << __ffs(dd->sddiv_mask);
  357. }
  358. /*
  359. * Errata i810 - DPLL controller can get stuck while transitioning
  360. * to a power saving state. Software must ensure the DPLL can not
  361. * transition to a low power state while changing M/N values.
  362. * Easiest way to accomplish this is to prevent DPLL autoidle
  363. * before doing the M/N re-program.
  364. */
  365. errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
  366. if (errata_i810) {
  367. ai = omap3_dpll_autoidle_read(clk);
  368. if (ai) {
  369. omap3_dpll_deny_idle(clk);
  370. /* OCP barrier */
  371. omap3_dpll_autoidle_read(clk);
  372. }
  373. }
  374. ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
  375. /* Set 4X multiplier and low-power mode */
  376. if (dd->m4xen_mask || dd->lpmode_mask) {
  377. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  378. if (dd->m4xen_mask) {
  379. if (dd->last_rounded_m4xen)
  380. v |= dd->m4xen_mask;
  381. else
  382. v &= ~dd->m4xen_mask;
  383. }
  384. if (dd->lpmode_mask) {
  385. if (dd->last_rounded_lpmode)
  386. v |= dd->lpmode_mask;
  387. else
  388. v &= ~dd->lpmode_mask;
  389. }
  390. ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
  391. }
  392. if (dd->ssc_enable_mask)
  393. omap3_noncore_dpll_ssc_program(clk);
  394. /* We let the clock framework set the other output dividers later */
  395. /* REVISIT: Set ramp-up delay? */
  396. _omap3_noncore_dpll_lock(clk);
  397. if (errata_i810 && ai)
  398. omap3_dpll_allow_idle(clk);
  399. return 0;
  400. }
  401. /* Public functions */
  402. /**
  403. * omap3_dpll_recalc - recalculate DPLL rate
  404. * @hw: struct clk_hw containing the DPLL struct clk
  405. * @parent_rate: clock rate of the DPLL parent
  406. *
  407. * Recalculate and propagate the DPLL rate.
  408. */
  409. unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
  410. {
  411. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  412. return omap2_get_dpll_rate(clk);
  413. }
  414. /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
  415. /**
  416. * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
  417. * @hw: struct clk_hw containing then pointer to a DPLL struct clk
  418. *
  419. * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
  420. * The choice of modes depends on the DPLL's programmed rate: if it is
  421. * the same as the DPLL's parent clock, it will enter bypass;
  422. * otherwise, it will enter lock. This code will wait for the DPLL to
  423. * indicate readiness before returning, unless the DPLL takes too long
  424. * to enter the target state. Intended to be used as the struct clk's
  425. * enable function. If DPLL3 was passed in, or the DPLL does not
  426. * support low-power stop, or if the DPLL took too long to enter
  427. * bypass or lock, return -EINVAL; otherwise, return 0.
  428. */
  429. int omap3_noncore_dpll_enable(struct clk_hw *hw)
  430. {
  431. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  432. int r;
  433. struct dpll_data *dd;
  434. struct clk_hw *parent;
  435. dd = clk->dpll_data;
  436. if (!dd)
  437. return -EINVAL;
  438. if (clk->clkdm) {
  439. r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
  440. if (r) {
  441. WARN(1,
  442. "%s: could not enable %s's clockdomain %s: %d\n",
  443. __func__, clk_hw_get_name(hw),
  444. clk->clkdm_name, r);
  445. return r;
  446. }
  447. }
  448. parent = clk_hw_get_parent(hw);
  449. if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {
  450. WARN_ON(parent != dd->clk_bypass);
  451. r = _omap3_noncore_dpll_bypass(clk);
  452. } else {
  453. WARN_ON(parent != dd->clk_ref);
  454. r = _omap3_noncore_dpll_lock(clk);
  455. }
  456. return r;
  457. }
  458. /**
  459. * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
  460. * @hw: struct clk_hw containing then pointer to a DPLL struct clk
  461. *
  462. * Instructs a non-CORE DPLL to enter low-power stop. This function is
  463. * intended for use in struct clkops. No return value.
  464. */
  465. void omap3_noncore_dpll_disable(struct clk_hw *hw)
  466. {
  467. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  468. _omap3_noncore_dpll_stop(clk);
  469. if (clk->clkdm)
  470. ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
  471. }
  472. /* Non-CORE DPLL rate set code */
  473. /**
  474. * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
  475. * @hw: pointer to the clock to determine rate for
  476. * @req: target rate request
  477. *
  478. * Determines which DPLL mode to use for reaching a desired target rate.
  479. * Checks whether the DPLL shall be in bypass or locked mode, and if
  480. * locked, calculates the M,N values for the DPLL via round-rate.
  481. * Returns a 0 on success, negative error value in failure.
  482. */
  483. int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
  484. struct clk_rate_request *req)
  485. {
  486. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  487. struct dpll_data *dd;
  488. if (!req->rate)
  489. return -EINVAL;
  490. dd = clk->dpll_data;
  491. if (!dd)
  492. return -EINVAL;
  493. if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
  494. (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
  495. req->best_parent_hw = dd->clk_bypass;
  496. } else {
  497. req->rate = omap2_dpll_round_rate(hw, req->rate,
  498. &req->best_parent_rate);
  499. req->best_parent_hw = dd->clk_ref;
  500. }
  501. req->best_parent_rate = req->rate;
  502. return 0;
  503. }
  504. /**
  505. * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
  506. * @hw: pointer to the clock to set parent for
  507. * @index: parent index to select
  508. *
  509. * Sets parent for a DPLL clock. This sets the DPLL into bypass or
  510. * locked mode. Returns 0 with success, negative error value otherwise.
  511. */
  512. int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
  513. {
  514. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  515. int ret;
  516. if (!hw)
  517. return -EINVAL;
  518. if (index)
  519. ret = _omap3_noncore_dpll_bypass(clk);
  520. else
  521. ret = _omap3_noncore_dpll_lock(clk);
  522. return ret;
  523. }
  524. /**
  525. * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
  526. * @hw: pointer to the clock to set parent for
  527. * @rate: target rate for the clock
  528. * @parent_rate: rate of the parent clock
  529. *
  530. * Sets rate for a DPLL clock. First checks if the clock parent is
  531. * reference clock (in bypass mode, the rate of the clock can't be
  532. * changed) and proceeds with the rate change operation. Returns 0
  533. * with success, negative error value otherwise.
  534. */
  535. int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
  536. unsigned long parent_rate)
  537. {
  538. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  539. struct dpll_data *dd;
  540. u16 freqsel = 0;
  541. int ret;
  542. if (!hw || !rate)
  543. return -EINVAL;
  544. dd = clk->dpll_data;
  545. if (!dd)
  546. return -EINVAL;
  547. if (clk_hw_get_parent(hw) != dd->clk_ref)
  548. return -EINVAL;
  549. if (dd->last_rounded_rate == 0)
  550. return -EINVAL;
  551. /* Freqsel is available only on OMAP343X devices */
  552. if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
  553. freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
  554. WARN_ON(!freqsel);
  555. }
  556. pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
  557. clk_hw_get_name(hw), rate);
  558. ret = omap3_noncore_dpll_program(clk, freqsel);
  559. return ret;
  560. }
  561. /**
  562. * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
  563. * @hw: pointer to the clock to set rate and parent for
  564. * @rate: target rate for the DPLL
  565. * @parent_rate: clock rate of the DPLL parent
  566. * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
  567. *
  568. * Sets rate and parent for a DPLL clock. If new parent is the bypass
  569. * clock, only selects the parent. Otherwise proceeds with a rate
  570. * change, as this will effectively also change the parent as the
  571. * DPLL is put into locked mode. Returns 0 with success, negative error
  572. * value otherwise.
  573. */
  574. int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
  575. unsigned long rate,
  576. unsigned long parent_rate,
  577. u8 index)
  578. {
  579. int ret;
  580. if (!hw || !rate)
  581. return -EINVAL;
  582. /*
  583. * clk-ref at index[0], in which case we only need to set rate,
  584. * the parent will be changed automatically with the lock sequence.
  585. * With clk-bypass case we only need to change parent.
  586. */
  587. if (index)
  588. ret = omap3_noncore_dpll_set_parent(hw, index);
  589. else
  590. ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
  591. return ret;
  592. }
  593. /* DPLL autoidle read/set code */
  594. /**
  595. * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
  596. * @clk: struct clk * of the DPLL to read
  597. *
  598. * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
  599. * -EINVAL if passed a null pointer or if the struct clk does not
  600. * appear to refer to a DPLL.
  601. */
  602. static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
  603. {
  604. const struct dpll_data *dd;
  605. u32 v;
  606. if (!clk || !clk->dpll_data)
  607. return -EINVAL;
  608. dd = clk->dpll_data;
  609. if (!dd->autoidle_mask)
  610. return -EINVAL;
  611. v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
  612. v &= dd->autoidle_mask;
  613. v >>= __ffs(dd->autoidle_mask);
  614. return v;
  615. }
  616. /**
  617. * omap3_dpll_allow_idle - enable DPLL autoidle bits
  618. * @clk: struct clk * of the DPLL to operate on
  619. *
  620. * Enable DPLL automatic idle control. This automatic idle mode
  621. * switching takes effect only when the DPLL is locked, at least on
  622. * OMAP3430. The DPLL will enter low-power stop when its downstream
  623. * clocks are gated. No return value.
  624. */
  625. static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
  626. {
  627. const struct dpll_data *dd;
  628. u32 v;
  629. if (!clk || !clk->dpll_data)
  630. return;
  631. dd = clk->dpll_data;
  632. if (!dd->autoidle_mask)
  633. return;
  634. /*
  635. * REVISIT: CORE DPLL can optionally enter low-power bypass
  636. * by writing 0x5 instead of 0x1. Add some mechanism to
  637. * optionally enter this mode.
  638. */
  639. v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
  640. v &= ~dd->autoidle_mask;
  641. v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
  642. ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
  643. }
  644. /**
  645. * omap3_dpll_deny_idle - prevent DPLL from automatically idling
  646. * @clk: struct clk * of the DPLL to operate on
  647. *
  648. * Disable DPLL automatic idle control. No return value.
  649. */
  650. static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
  651. {
  652. const struct dpll_data *dd;
  653. u32 v;
  654. if (!clk || !clk->dpll_data)
  655. return;
  656. dd = clk->dpll_data;
  657. if (!dd->autoidle_mask)
  658. return;
  659. v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
  660. v &= ~dd->autoidle_mask;
  661. v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
  662. ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
  663. }
  664. /* Clock control for DPLL outputs */
  665. /* Find the parent DPLL for the given clkoutx2 clock */
  666. static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
  667. {
  668. struct clk_hw_omap *pclk = NULL;
  669. /* Walk up the parents of clk, looking for a DPLL */
  670. do {
  671. do {
  672. hw = clk_hw_get_parent(hw);
  673. } while (hw && (!omap2_clk_is_hw_omap(hw)));
  674. if (!hw)
  675. break;
  676. pclk = to_clk_hw_omap(hw);
  677. } while (pclk && !pclk->dpll_data);
  678. /* clk does not have a DPLL as a parent? error in the clock data */
  679. if (!pclk) {
  680. WARN_ON(1);
  681. return NULL;
  682. }
  683. return pclk;
  684. }
  685. /**
  686. * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
  687. * @hw: pointer struct clk_hw
  688. * @parent_rate: clock rate of the DPLL parent
  689. *
  690. * Using parent clock DPLL data, look up DPLL state. If locked, set our
  691. * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
  692. */
  693. unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
  694. unsigned long parent_rate)
  695. {
  696. const struct dpll_data *dd;
  697. unsigned long rate;
  698. u32 v;
  699. struct clk_hw_omap *pclk = NULL;
  700. if (!parent_rate)
  701. return 0;
  702. pclk = omap3_find_clkoutx2_dpll(hw);
  703. if (!pclk)
  704. return 0;
  705. dd = pclk->dpll_data;
  706. WARN_ON(!dd->enable_mask);
  707. v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
  708. v >>= __ffs(dd->enable_mask);
  709. if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
  710. rate = parent_rate;
  711. else
  712. rate = parent_rate * 2;
  713. return rate;
  714. }
  715. /**
  716. * omap3_core_dpll_save_context - Save the m and n values of the divider
  717. * @hw: pointer struct clk_hw
  718. *
  719. * Before the dpll registers are lost save the last rounded rate m and n
  720. * and the enable mask.
  721. */
  722. int omap3_core_dpll_save_context(struct clk_hw *hw)
  723. {
  724. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  725. struct dpll_data *dd;
  726. u32 v;
  727. dd = clk->dpll_data;
  728. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  729. clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
  730. if (clk->context == DPLL_LOCKED) {
  731. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  732. dd->last_rounded_m = (v & dd->mult_mask) >>
  733. __ffs(dd->mult_mask);
  734. dd->last_rounded_n = ((v & dd->div1_mask) >>
  735. __ffs(dd->div1_mask)) + 1;
  736. }
  737. return 0;
  738. }
  739. /**
  740. * omap3_core_dpll_restore_context - restore the m and n values of the divider
  741. * @hw: pointer struct clk_hw
  742. *
  743. * Restore the last rounded rate m and n
  744. * and the enable mask.
  745. */
  746. void omap3_core_dpll_restore_context(struct clk_hw *hw)
  747. {
  748. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  749. const struct dpll_data *dd;
  750. u32 v;
  751. dd = clk->dpll_data;
  752. if (clk->context == DPLL_LOCKED) {
  753. _omap3_dpll_write_clken(clk, 0x4);
  754. _omap3_wait_dpll_status(clk, 0);
  755. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  756. v &= ~(dd->mult_mask | dd->div1_mask);
  757. v |= dd->last_rounded_m << __ffs(dd->mult_mask);
  758. v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
  759. ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
  760. _omap3_dpll_write_clken(clk, DPLL_LOCKED);
  761. _omap3_wait_dpll_status(clk, 1);
  762. } else {
  763. _omap3_dpll_write_clken(clk, clk->context);
  764. }
  765. }
  766. /**
  767. * omap3_non_core_dpll_save_context - Save the m and n values of the divider
  768. * @hw: pointer struct clk_hw
  769. *
  770. * Before the dpll registers are lost save the last rounded rate m and n
  771. * and the enable mask.
  772. */
  773. int omap3_noncore_dpll_save_context(struct clk_hw *hw)
  774. {
  775. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  776. struct dpll_data *dd;
  777. u32 v;
  778. dd = clk->dpll_data;
  779. v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  780. clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
  781. if (clk->context == DPLL_LOCKED) {
  782. v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  783. dd->last_rounded_m = (v & dd->mult_mask) >>
  784. __ffs(dd->mult_mask);
  785. dd->last_rounded_n = ((v & dd->div1_mask) >>
  786. __ffs(dd->div1_mask)) + 1;
  787. }
  788. return 0;
  789. }
  790. /**
  791. * omap3_core_dpll_restore_context - restore the m and n values of the divider
  792. * @hw: pointer struct clk_hw
  793. *
  794. * Restore the last rounded rate m and n
  795. * and the enable mask.
  796. */
  797. void omap3_noncore_dpll_restore_context(struct clk_hw *hw)
  798. {
  799. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  800. const struct dpll_data *dd;
  801. u32 ctrl, mult_div1;
  802. dd = clk->dpll_data;
  803. ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
  804. mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
  805. if (clk->context == ((ctrl & dd->enable_mask) >>
  806. __ffs(dd->enable_mask)) &&
  807. dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >>
  808. __ffs(dd->mult_mask)) &&
  809. dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >>
  810. __ffs(dd->div1_mask)) + 1) {
  811. /* nothing to be done */
  812. return;
  813. }
  814. if (clk->context == DPLL_LOCKED)
  815. omap3_noncore_dpll_program(clk, 0);
  816. else
  817. _omap3_dpll_write_clken(clk, clk->context);
  818. }
  819. /* OMAP3/4 non-CORE DPLL clkops */
  820. const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
  821. .allow_idle = omap3_dpll_allow_idle,
  822. .deny_idle = omap3_dpll_deny_idle,
  823. };
  824. /**
  825. * omap3_dpll4_set_rate - set rate for omap3 per-dpll
  826. * @hw: clock to change
  827. * @rate: target rate for clock
  828. * @parent_rate: clock rate of the DPLL parent
  829. *
  830. * Check if the current SoC supports the per-dpll reprogram operation
  831. * or not, and then do the rate change if supported. Returns -EINVAL
  832. * if not supported, 0 for success, and potential error codes from the
  833. * clock rate change.
  834. */
  835. int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
  836. unsigned long parent_rate)
  837. {
  838. /*
  839. * According to the 12-5 CDP code from TI, "Limitation 2.5"
  840. * on 3430ES1 prevents us from changing DPLL multipliers or dividers
  841. * on DPLL4.
  842. */
  843. if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
  844. pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
  845. return -EINVAL;
  846. }
  847. return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
  848. }
  849. /**
  850. * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
  851. * @hw: clock to change
  852. * @rate: target rate for clock
  853. * @parent_rate: rate of the parent clock
  854. * @index: parent index, 0 - reference clock, 1 - bypass clock
  855. *
  856. * Check if the current SoC support the per-dpll reprogram operation
  857. * or not, and then do the rate + parent change if supported. Returns
  858. * -EINVAL if not supported, 0 for success, and potential error codes
  859. * from the clock rate change.
  860. */
  861. int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
  862. unsigned long parent_rate, u8 index)
  863. {
  864. if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
  865. pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
  866. return -EINVAL;
  867. }
  868. return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
  869. index);
  870. }
  871. /* Apply DM3730 errata sprz319 advisory 2.1. */
  872. static bool omap3_dpll5_apply_errata(struct clk_hw *hw,
  873. unsigned long parent_rate)
  874. {
  875. struct omap3_dpll5_settings {
  876. unsigned int rate, m, n;
  877. };
  878. static const struct omap3_dpll5_settings precomputed[] = {
  879. /*
  880. * From DM3730 errata advisory 2.1, table 35 and 36.
  881. * The N value is increased by 1 compared to the tables as the
  882. * errata lists register values while last_rounded_field is the
  883. * real divider value.
  884. */
  885. { 12000000, 80, 0 + 1 },
  886. { 13000000, 443, 5 + 1 },
  887. { 19200000, 50, 0 + 1 },
  888. { 26000000, 443, 11 + 1 },
  889. { 38400000, 25, 0 + 1 }
  890. };
  891. const struct omap3_dpll5_settings *d;
  892. struct clk_hw_omap *clk = to_clk_hw_omap(hw);
  893. struct dpll_data *dd;
  894. unsigned int i;
  895. for (i = 0; i < ARRAY_SIZE(precomputed); ++i) {
  896. if (parent_rate == precomputed[i].rate)
  897. break;
  898. }
  899. if (i == ARRAY_SIZE(precomputed))
  900. return false;
  901. d = &precomputed[i];
  902. /* Update the M, N and rounded rate values and program the DPLL. */
  903. dd = clk->dpll_data;
  904. dd->last_rounded_m = d->m;
  905. dd->last_rounded_n = d->n;
  906. dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);
  907. omap3_noncore_dpll_program(clk, 0);
  908. return true;
  909. }
  910. /**
  911. * omap3_dpll5_set_rate - set rate for omap3 dpll5
  912. * @hw: clock to change
  913. * @rate: target rate for clock
  914. * @parent_rate: rate of the parent clock
  915. *
  916. * Set rate for the DPLL5 clock. Apply the sprz319 advisory 2.1 on OMAP36xx if
  917. * the DPLL is used for USB host (detected through the requested rate).
  918. */
  919. int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
  920. unsigned long parent_rate)
  921. {
  922. if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {
  923. if (omap3_dpll5_apply_errata(hw, parent_rate))
  924. return 0;
  925. }
  926. return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
  927. }