clk-sun8i-bus-gates.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2015 Jens Kuske <[email protected]>
  4. *
  5. * Based on clk-simple-gates.c, which is:
  6. * Copyright 2015 Maxime Ripard
  7. *
  8. * Maxime Ripard <[email protected]>
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. static DEFINE_SPINLOCK(gates_lock);
  17. static void __init sun8i_h3_bus_gates_init(struct device_node *node)
  18. {
  19. static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
  20. enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
  21. const char *parents[PARENT_MAX];
  22. struct clk_onecell_data *clk_data;
  23. const char *clk_name;
  24. struct property *prop;
  25. struct resource res;
  26. void __iomem *clk_reg;
  27. void __iomem *reg;
  28. const __be32 *p;
  29. int number, i;
  30. u8 clk_bit;
  31. int index;
  32. reg = of_io_request_and_map(node, 0, of_node_full_name(node));
  33. if (IS_ERR(reg))
  34. return;
  35. for (i = 0; i < ARRAY_SIZE(names); i++) {
  36. int idx = of_property_match_string(node, "clock-names",
  37. names[i]);
  38. if (idx < 0)
  39. return;
  40. parents[i] = of_clk_get_parent_name(node, idx);
  41. }
  42. clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
  43. if (!clk_data)
  44. goto err_unmap;
  45. number = of_property_count_u32_elems(node, "clock-indices");
  46. of_property_read_u32_index(node, "clock-indices", number - 1, &number);
  47. clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
  48. if (!clk_data->clks)
  49. goto err_free_data;
  50. i = 0;
  51. of_property_for_each_u32(node, "clock-indices", prop, p, index) {
  52. of_property_read_string_index(node, "clock-output-names",
  53. i, &clk_name);
  54. if (index == 17 || (index >= 29 && index <= 31))
  55. clk_parent = AHB2;
  56. else if (index <= 63 || index >= 128)
  57. clk_parent = AHB1;
  58. else if (index >= 64 && index <= 95)
  59. clk_parent = APB1;
  60. else if (index >= 96 && index <= 127)
  61. clk_parent = APB2;
  62. else {
  63. WARN_ON(true);
  64. continue;
  65. }
  66. clk_reg = reg + 4 * (index / 32);
  67. clk_bit = index % 32;
  68. clk_data->clks[index] = clk_register_gate(NULL, clk_name,
  69. parents[clk_parent],
  70. 0, clk_reg, clk_bit,
  71. 0, &gates_lock);
  72. i++;
  73. if (IS_ERR(clk_data->clks[index])) {
  74. WARN_ON(true);
  75. continue;
  76. }
  77. }
  78. clk_data->clk_num = number + 1;
  79. of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  80. return;
  81. err_free_data:
  82. kfree(clk_data);
  83. err_unmap:
  84. iounmap(reg);
  85. of_address_to_resource(node, 0, &res);
  86. release_mem_region(res.start, resource_size(&res));
  87. }
  88. CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
  89. sun8i_h3_bus_gates_init);
  90. CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
  91. sun8i_h3_bus_gates_init);