clk-sun6i-apb0-gates.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014 Free Electrons
  4. *
  5. * Author: Boris BREZILLON <[email protected]>
  6. *
  7. * Allwinner A31 APB0 clock gates driver
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/init.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/platform_device.h>
  14. #define SUN6I_APB0_GATES_MAX_SIZE 32
  15. struct gates_data {
  16. DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
  17. };
  18. static const struct gates_data sun6i_a31_apb0_gates __initconst = {
  19. .mask = {0x7F},
  20. };
  21. static const struct gates_data sun8i_a23_apb0_gates __initconst = {
  22. .mask = {0x5D},
  23. };
  24. static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
  25. { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
  26. { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
  27. { /* sentinel */ }
  28. };
  29. static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
  30. {
  31. struct device_node *np = pdev->dev.of_node;
  32. struct clk_onecell_data *clk_data;
  33. const struct gates_data *data;
  34. const char *clk_parent;
  35. const char *clk_name;
  36. void __iomem *reg;
  37. int ngates;
  38. int i;
  39. int j = 0;
  40. if (!np)
  41. return -ENODEV;
  42. data = of_device_get_match_data(&pdev->dev);
  43. if (!data)
  44. return -ENODEV;
  45. reg = devm_platform_ioremap_resource(pdev, 0);
  46. if (IS_ERR(reg))
  47. return PTR_ERR(reg);
  48. clk_parent = of_clk_get_parent_name(np, 0);
  49. if (!clk_parent)
  50. return -EINVAL;
  51. clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
  52. GFP_KERNEL);
  53. if (!clk_data)
  54. return -ENOMEM;
  55. /* Worst-case size approximation and memory allocation */
  56. ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
  57. clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
  58. sizeof(struct clk *), GFP_KERNEL);
  59. if (!clk_data->clks)
  60. return -ENOMEM;
  61. for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
  62. of_property_read_string_index(np, "clock-output-names",
  63. j, &clk_name);
  64. clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
  65. clk_parent, 0, reg, i,
  66. 0, NULL);
  67. WARN_ON(IS_ERR(clk_data->clks[i]));
  68. j++;
  69. }
  70. clk_data->clk_num = ngates + 1;
  71. return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
  72. }
  73. static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
  74. .driver = {
  75. .name = "sun6i-a31-apb0-gates-clk",
  76. .of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
  77. },
  78. .probe = sun6i_a31_apb0_gates_clk_probe,
  79. };
  80. builtin_platform_driver(sun6i_a31_apb0_gates_clk_driver);