clk-a10-mod1.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2013 Emilio López
  4. *
  5. * Emilio López <[email protected]>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/io.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/slab.h>
  12. static DEFINE_SPINLOCK(mod1_lock);
  13. #define SUN4I_MOD1_ENABLE 31
  14. #define SUN4I_MOD1_MUX 16
  15. #define SUN4I_MOD1_MUX_WIDTH 2
  16. #define SUN4I_MOD1_MAX_PARENTS 4
  17. static void __init sun4i_mod1_clk_setup(struct device_node *node)
  18. {
  19. struct clk *clk;
  20. struct clk_mux *mux;
  21. struct clk_gate *gate;
  22. const char *parents[4];
  23. const char *clk_name = node->name;
  24. void __iomem *reg;
  25. int i;
  26. reg = of_io_request_and_map(node, 0, of_node_full_name(node));
  27. if (IS_ERR(reg))
  28. return;
  29. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  30. if (!mux)
  31. goto err_unmap;
  32. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  33. if (!gate)
  34. goto err_free_mux;
  35. of_property_read_string(node, "clock-output-names", &clk_name);
  36. i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
  37. gate->reg = reg;
  38. gate->bit_idx = SUN4I_MOD1_ENABLE;
  39. gate->lock = &mod1_lock;
  40. mux->reg = reg;
  41. mux->shift = SUN4I_MOD1_MUX;
  42. mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
  43. mux->lock = &mod1_lock;
  44. clk = clk_register_composite(NULL, clk_name, parents, i,
  45. &mux->hw, &clk_mux_ops,
  46. NULL, NULL,
  47. &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
  48. if (IS_ERR(clk))
  49. goto err_free_gate;
  50. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  51. return;
  52. err_free_gate:
  53. kfree(gate);
  54. err_free_mux:
  55. kfree(mux);
  56. err_unmap:
  57. iounmap(reg);
  58. }
  59. CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",
  60. sun4i_mod1_clk_setup);