ccu-sun8i-h3.h 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2016 Maxime Ripard
  4. *
  5. * Maxime Ripard <[email protected]>
  6. */
  7. #ifndef _CCU_SUN8I_H3_H_
  8. #define _CCU_SUN8I_H3_H_
  9. #include <dt-bindings/clock/sun8i-h3-ccu.h>
  10. #include <dt-bindings/reset/sun8i-h3-ccu.h>
  11. #define CLK_PLL_CPUX 0
  12. #define CLK_PLL_AUDIO_BASE 1
  13. #define CLK_PLL_AUDIO 2
  14. #define CLK_PLL_AUDIO_2X 3
  15. #define CLK_PLL_AUDIO_4X 4
  16. #define CLK_PLL_AUDIO_8X 5
  17. /* PLL_VIDEO is exported */
  18. #define CLK_PLL_VE 7
  19. #define CLK_PLL_DDR 8
  20. /* PLL_PERIPH0 exported for PRCM */
  21. #define CLK_PLL_PERIPH0_2X 10
  22. #define CLK_PLL_GPU 11
  23. #define CLK_PLL_PERIPH1 12
  24. #define CLK_PLL_DE 13
  25. /* The CPUX clock is exported */
  26. #define CLK_AXI 15
  27. #define CLK_AHB1 16
  28. #define CLK_APB1 17
  29. #define CLK_APB2 18
  30. #define CLK_AHB2 19
  31. /* All the bus gates are exported */
  32. /* The first bunch of module clocks are exported */
  33. /* All the DRAM gates are exported */
  34. /* Some more module clocks are exported */
  35. #define CLK_NUMBER_H3 (CLK_GPU + 1)
  36. #define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1)
  37. #endif /* _CCU_SUN8I_H3_H_ */