clk-pll.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. *
  6. * This file contains the utility functions to register the pll clocks.
  7. */
  8. #include <linux/errno.h>
  9. #include <linux/hrtimer.h>
  10. #include <linux/iopoll.h>
  11. #include <linux/delay.h>
  12. #include <linux/slab.h>
  13. #include <linux/timekeeping.h>
  14. #include <linux/clk-provider.h>
  15. #include <linux/io.h>
  16. #include "clk.h"
  17. #include "clk-pll.h"
  18. #define PLL_TIMEOUT_US 20000U
  19. #define PLL_TIMEOUT_LOOPS 1000000U
  20. struct samsung_clk_pll {
  21. struct clk_hw hw;
  22. void __iomem *lock_reg;
  23. void __iomem *con_reg;
  24. /* PLL enable control bit offset in @con_reg register */
  25. unsigned short enable_offs;
  26. /* PLL lock status bit offset in @con_reg register */
  27. unsigned short lock_offs;
  28. enum samsung_pll_type type;
  29. unsigned int rate_count;
  30. const struct samsung_pll_rate_table *rate_table;
  31. };
  32. #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
  33. static const struct samsung_pll_rate_table *samsung_get_pll_settings(
  34. struct samsung_clk_pll *pll, unsigned long rate)
  35. {
  36. const struct samsung_pll_rate_table *rate_table = pll->rate_table;
  37. int i;
  38. for (i = 0; i < pll->rate_count; i++) {
  39. if (rate == rate_table[i].rate)
  40. return &rate_table[i];
  41. }
  42. return NULL;
  43. }
  44. static long samsung_pll_round_rate(struct clk_hw *hw,
  45. unsigned long drate, unsigned long *prate)
  46. {
  47. struct samsung_clk_pll *pll = to_clk_pll(hw);
  48. const struct samsung_pll_rate_table *rate_table = pll->rate_table;
  49. int i;
  50. /* Assumming rate_table is in descending order */
  51. for (i = 0; i < pll->rate_count; i++) {
  52. if (drate >= rate_table[i].rate)
  53. return rate_table[i].rate;
  54. }
  55. /* return minimum supported value */
  56. return rate_table[i - 1].rate;
  57. }
  58. static bool pll_early_timeout = true;
  59. static int __init samsung_pll_disable_early_timeout(void)
  60. {
  61. pll_early_timeout = false;
  62. return 0;
  63. }
  64. arch_initcall(samsung_pll_disable_early_timeout);
  65. /* Wait until the PLL is locked */
  66. static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,
  67. unsigned int reg_mask)
  68. {
  69. int i, ret;
  70. u32 val;
  71. /*
  72. * This function might be called when the timekeeping API can't be used
  73. * to detect timeouts. One situation is when the clocksource is not yet
  74. * initialized, another when the timekeeping is suspended. udelay() also
  75. * cannot be used when the clocksource is not running on arm64, since
  76. * the current timer is used as cycle counter. So a simple busy loop
  77. * is used here in that special cases. The limit of iterations has been
  78. * derived from experimental measurements of various PLLs on multiple
  79. * Exynos SoC variants. Single register read time was usually in range
  80. * 0.4...1.5 us, never less than 0.4 us.
  81. */
  82. if (pll_early_timeout || timekeeping_suspended) {
  83. i = PLL_TIMEOUT_LOOPS;
  84. while (i-- > 0) {
  85. if (readl_relaxed(pll->con_reg) & reg_mask)
  86. return 0;
  87. cpu_relax();
  88. }
  89. ret = -ETIMEDOUT;
  90. } else {
  91. ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,
  92. val & reg_mask, 0, PLL_TIMEOUT_US);
  93. }
  94. if (ret < 0)
  95. pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));
  96. return ret;
  97. }
  98. static int samsung_pll3xxx_enable(struct clk_hw *hw)
  99. {
  100. struct samsung_clk_pll *pll = to_clk_pll(hw);
  101. u32 tmp;
  102. tmp = readl_relaxed(pll->con_reg);
  103. tmp |= BIT(pll->enable_offs);
  104. writel_relaxed(tmp, pll->con_reg);
  105. return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
  106. }
  107. static void samsung_pll3xxx_disable(struct clk_hw *hw)
  108. {
  109. struct samsung_clk_pll *pll = to_clk_pll(hw);
  110. u32 tmp;
  111. tmp = readl_relaxed(pll->con_reg);
  112. tmp &= ~BIT(pll->enable_offs);
  113. writel_relaxed(tmp, pll->con_reg);
  114. }
  115. /*
  116. * PLL2126 Clock Type
  117. */
  118. #define PLL2126_MDIV_MASK (0xff)
  119. #define PLL2126_PDIV_MASK (0x3f)
  120. #define PLL2126_SDIV_MASK (0x3)
  121. #define PLL2126_MDIV_SHIFT (16)
  122. #define PLL2126_PDIV_SHIFT (8)
  123. #define PLL2126_SDIV_SHIFT (0)
  124. static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
  125. unsigned long parent_rate)
  126. {
  127. struct samsung_clk_pll *pll = to_clk_pll(hw);
  128. u32 pll_con, mdiv, pdiv, sdiv;
  129. u64 fvco = parent_rate;
  130. pll_con = readl_relaxed(pll->con_reg);
  131. mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
  132. pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
  133. sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
  134. fvco *= (mdiv + 8);
  135. do_div(fvco, (pdiv + 2) << sdiv);
  136. return (unsigned long)fvco;
  137. }
  138. static const struct clk_ops samsung_pll2126_clk_ops = {
  139. .recalc_rate = samsung_pll2126_recalc_rate,
  140. };
  141. /*
  142. * PLL3000 Clock Type
  143. */
  144. #define PLL3000_MDIV_MASK (0xff)
  145. #define PLL3000_PDIV_MASK (0x3)
  146. #define PLL3000_SDIV_MASK (0x3)
  147. #define PLL3000_MDIV_SHIFT (16)
  148. #define PLL3000_PDIV_SHIFT (8)
  149. #define PLL3000_SDIV_SHIFT (0)
  150. static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
  151. unsigned long parent_rate)
  152. {
  153. struct samsung_clk_pll *pll = to_clk_pll(hw);
  154. u32 pll_con, mdiv, pdiv, sdiv;
  155. u64 fvco = parent_rate;
  156. pll_con = readl_relaxed(pll->con_reg);
  157. mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
  158. pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
  159. sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
  160. fvco *= (2 * (mdiv + 8));
  161. do_div(fvco, pdiv << sdiv);
  162. return (unsigned long)fvco;
  163. }
  164. static const struct clk_ops samsung_pll3000_clk_ops = {
  165. .recalc_rate = samsung_pll3000_recalc_rate,
  166. };
  167. /*
  168. * PLL35xx Clock Type
  169. */
  170. /* Maximum lock time can be 270 * PDIV cycles */
  171. #define PLL35XX_LOCK_FACTOR (270)
  172. #define PLL35XX_MDIV_MASK (0x3FF)
  173. #define PLL35XX_PDIV_MASK (0x3F)
  174. #define PLL35XX_SDIV_MASK (0x7)
  175. #define PLL35XX_MDIV_SHIFT (16)
  176. #define PLL35XX_PDIV_SHIFT (8)
  177. #define PLL35XX_SDIV_SHIFT (0)
  178. #define PLL35XX_LOCK_STAT_SHIFT (29)
  179. #define PLL35XX_ENABLE_SHIFT (31)
  180. static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
  181. unsigned long parent_rate)
  182. {
  183. struct samsung_clk_pll *pll = to_clk_pll(hw);
  184. u32 mdiv, pdiv, sdiv, pll_con;
  185. u64 fvco = parent_rate;
  186. pll_con = readl_relaxed(pll->con_reg);
  187. mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
  188. pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
  189. sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
  190. fvco *= mdiv;
  191. do_div(fvco, (pdiv << sdiv));
  192. return (unsigned long)fvco;
  193. }
  194. static inline bool samsung_pll35xx_mp_change(
  195. const struct samsung_pll_rate_table *rate, u32 pll_con)
  196. {
  197. u32 old_mdiv, old_pdiv;
  198. old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
  199. old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
  200. return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
  201. }
  202. static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
  203. unsigned long prate)
  204. {
  205. struct samsung_clk_pll *pll = to_clk_pll(hw);
  206. const struct samsung_pll_rate_table *rate;
  207. u32 tmp;
  208. /* Get required rate settings from table */
  209. rate = samsung_get_pll_settings(pll, drate);
  210. if (!rate) {
  211. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  212. drate, clk_hw_get_name(hw));
  213. return -EINVAL;
  214. }
  215. tmp = readl_relaxed(pll->con_reg);
  216. if (!(samsung_pll35xx_mp_change(rate, tmp))) {
  217. /* If only s change, change just s value only*/
  218. tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
  219. tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
  220. writel_relaxed(tmp, pll->con_reg);
  221. return 0;
  222. }
  223. /* Set PLL lock time. */
  224. writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
  225. pll->lock_reg);
  226. /* Change PLL PMS values */
  227. tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
  228. (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
  229. (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
  230. tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
  231. (rate->pdiv << PLL35XX_PDIV_SHIFT) |
  232. (rate->sdiv << PLL35XX_SDIV_SHIFT);
  233. writel_relaxed(tmp, pll->con_reg);
  234. /* Wait for PLL lock if the PLL is enabled */
  235. if (tmp & BIT(pll->enable_offs))
  236. return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
  237. return 0;
  238. }
  239. static const struct clk_ops samsung_pll35xx_clk_ops = {
  240. .recalc_rate = samsung_pll35xx_recalc_rate,
  241. .round_rate = samsung_pll_round_rate,
  242. .set_rate = samsung_pll35xx_set_rate,
  243. .enable = samsung_pll3xxx_enable,
  244. .disable = samsung_pll3xxx_disable,
  245. };
  246. static const struct clk_ops samsung_pll35xx_clk_min_ops = {
  247. .recalc_rate = samsung_pll35xx_recalc_rate,
  248. };
  249. /*
  250. * PLL36xx Clock Type
  251. */
  252. /* Maximum lock time can be 3000 * PDIV cycles */
  253. #define PLL36XX_LOCK_FACTOR (3000)
  254. #define PLL36XX_KDIV_MASK (0xFFFF)
  255. #define PLL36XX_MDIV_MASK (0x1FF)
  256. #define PLL36XX_PDIV_MASK (0x3F)
  257. #define PLL36XX_SDIV_MASK (0x7)
  258. #define PLL36XX_MDIV_SHIFT (16)
  259. #define PLL36XX_PDIV_SHIFT (8)
  260. #define PLL36XX_SDIV_SHIFT (0)
  261. #define PLL36XX_KDIV_SHIFT (0)
  262. #define PLL36XX_LOCK_STAT_SHIFT (29)
  263. #define PLL36XX_ENABLE_SHIFT (31)
  264. static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
  265. unsigned long parent_rate)
  266. {
  267. struct samsung_clk_pll *pll = to_clk_pll(hw);
  268. u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
  269. s16 kdiv;
  270. u64 fvco = parent_rate;
  271. pll_con0 = readl_relaxed(pll->con_reg);
  272. pll_con1 = readl_relaxed(pll->con_reg + 4);
  273. mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
  274. pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
  275. sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
  276. kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
  277. fvco *= (mdiv << 16) + kdiv;
  278. do_div(fvco, (pdiv << sdiv));
  279. fvco >>= 16;
  280. return (unsigned long)fvco;
  281. }
  282. static inline bool samsung_pll36xx_mpk_change(
  283. const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
  284. {
  285. u32 old_mdiv, old_pdiv, old_kdiv;
  286. old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
  287. old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
  288. old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
  289. return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
  290. rate->kdiv != old_kdiv);
  291. }
  292. static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
  293. unsigned long parent_rate)
  294. {
  295. struct samsung_clk_pll *pll = to_clk_pll(hw);
  296. u32 pll_con0, pll_con1;
  297. const struct samsung_pll_rate_table *rate;
  298. rate = samsung_get_pll_settings(pll, drate);
  299. if (!rate) {
  300. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  301. drate, clk_hw_get_name(hw));
  302. return -EINVAL;
  303. }
  304. pll_con0 = readl_relaxed(pll->con_reg);
  305. pll_con1 = readl_relaxed(pll->con_reg + 4);
  306. if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
  307. /* If only s change, change just s value only*/
  308. pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
  309. pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
  310. writel_relaxed(pll_con0, pll->con_reg);
  311. return 0;
  312. }
  313. /* Set PLL lock time. */
  314. writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
  315. /* Change PLL PMS values */
  316. pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
  317. (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
  318. (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
  319. pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
  320. (rate->pdiv << PLL36XX_PDIV_SHIFT) |
  321. (rate->sdiv << PLL36XX_SDIV_SHIFT);
  322. writel_relaxed(pll_con0, pll->con_reg);
  323. pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
  324. pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
  325. writel_relaxed(pll_con1, pll->con_reg + 4);
  326. if (pll_con0 & BIT(pll->enable_offs))
  327. return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
  328. return 0;
  329. }
  330. static const struct clk_ops samsung_pll36xx_clk_ops = {
  331. .recalc_rate = samsung_pll36xx_recalc_rate,
  332. .set_rate = samsung_pll36xx_set_rate,
  333. .round_rate = samsung_pll_round_rate,
  334. .enable = samsung_pll3xxx_enable,
  335. .disable = samsung_pll3xxx_disable,
  336. };
  337. static const struct clk_ops samsung_pll36xx_clk_min_ops = {
  338. .recalc_rate = samsung_pll36xx_recalc_rate,
  339. };
  340. /*
  341. * PLL0822x Clock Type
  342. */
  343. /* Maximum lock time can be 150 * PDIV cycles */
  344. #define PLL0822X_LOCK_FACTOR (150)
  345. #define PLL0822X_MDIV_MASK (0x3FF)
  346. #define PLL0822X_PDIV_MASK (0x3F)
  347. #define PLL0822X_SDIV_MASK (0x7)
  348. #define PLL0822X_MDIV_SHIFT (16)
  349. #define PLL0822X_PDIV_SHIFT (8)
  350. #define PLL0822X_SDIV_SHIFT (0)
  351. #define PLL0822X_LOCK_STAT_SHIFT (29)
  352. #define PLL0822X_ENABLE_SHIFT (31)
  353. static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
  354. unsigned long parent_rate)
  355. {
  356. struct samsung_clk_pll *pll = to_clk_pll(hw);
  357. u32 mdiv, pdiv, sdiv, pll_con3;
  358. u64 fvco = parent_rate;
  359. pll_con3 = readl_relaxed(pll->con_reg);
  360. mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
  361. pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
  362. sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
  363. fvco *= mdiv;
  364. do_div(fvco, (pdiv << sdiv));
  365. return (unsigned long)fvco;
  366. }
  367. static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
  368. unsigned long prate)
  369. {
  370. const struct samsung_pll_rate_table *rate;
  371. struct samsung_clk_pll *pll = to_clk_pll(hw);
  372. u32 pll_con3;
  373. /* Get required rate settings from table */
  374. rate = samsung_get_pll_settings(pll, drate);
  375. if (!rate) {
  376. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  377. drate, clk_hw_get_name(hw));
  378. return -EINVAL;
  379. }
  380. /* Change PLL PMS values */
  381. pll_con3 = readl_relaxed(pll->con_reg);
  382. pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |
  383. (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
  384. (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
  385. pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
  386. (rate->pdiv << PLL0822X_PDIV_SHIFT) |
  387. (rate->sdiv << PLL0822X_SDIV_SHIFT);
  388. /* Set PLL lock time */
  389. writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR,
  390. pll->lock_reg);
  391. /* Write PMS values */
  392. writel_relaxed(pll_con3, pll->con_reg);
  393. /* Wait for PLL lock if the PLL is enabled */
  394. if (pll_con3 & BIT(pll->enable_offs))
  395. return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
  396. return 0;
  397. }
  398. static const struct clk_ops samsung_pll0822x_clk_ops = {
  399. .recalc_rate = samsung_pll0822x_recalc_rate,
  400. .round_rate = samsung_pll_round_rate,
  401. .set_rate = samsung_pll0822x_set_rate,
  402. .enable = samsung_pll3xxx_enable,
  403. .disable = samsung_pll3xxx_disable,
  404. };
  405. static const struct clk_ops samsung_pll0822x_clk_min_ops = {
  406. .recalc_rate = samsung_pll0822x_recalc_rate,
  407. };
  408. /*
  409. * PLL0831x Clock Type
  410. */
  411. /* Maximum lock time can be 500 * PDIV cycles */
  412. #define PLL0831X_LOCK_FACTOR (500)
  413. #define PLL0831X_KDIV_MASK (0xFFFF)
  414. #define PLL0831X_MDIV_MASK (0x1FF)
  415. #define PLL0831X_PDIV_MASK (0x3F)
  416. #define PLL0831X_SDIV_MASK (0x7)
  417. #define PLL0831X_MDIV_SHIFT (16)
  418. #define PLL0831X_PDIV_SHIFT (8)
  419. #define PLL0831X_SDIV_SHIFT (0)
  420. #define PLL0831X_KDIV_SHIFT (0)
  421. #define PLL0831X_LOCK_STAT_SHIFT (29)
  422. #define PLL0831X_ENABLE_SHIFT (31)
  423. static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw,
  424. unsigned long parent_rate)
  425. {
  426. struct samsung_clk_pll *pll = to_clk_pll(hw);
  427. u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
  428. s16 kdiv;
  429. u64 fvco = parent_rate;
  430. pll_con3 = readl_relaxed(pll->con_reg);
  431. pll_con5 = readl_relaxed(pll->con_reg + 8);
  432. mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
  433. pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
  434. sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
  435. kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
  436. fvco *= (mdiv << 16) + kdiv;
  437. do_div(fvco, (pdiv << sdiv));
  438. fvco >>= 16;
  439. return (unsigned long)fvco;
  440. }
  441. static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate,
  442. unsigned long parent_rate)
  443. {
  444. const struct samsung_pll_rate_table *rate;
  445. struct samsung_clk_pll *pll = to_clk_pll(hw);
  446. u32 pll_con3, pll_con5;
  447. /* Get required rate settings from table */
  448. rate = samsung_get_pll_settings(pll, drate);
  449. if (!rate) {
  450. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  451. drate, clk_hw_get_name(hw));
  452. return -EINVAL;
  453. }
  454. pll_con3 = readl_relaxed(pll->con_reg);
  455. pll_con5 = readl_relaxed(pll->con_reg + 8);
  456. /* Change PLL PMSK values */
  457. pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) |
  458. (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) |
  459. (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT));
  460. pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) |
  461. (rate->pdiv << PLL0831X_PDIV_SHIFT) |
  462. (rate->sdiv << PLL0831X_SDIV_SHIFT);
  463. pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT);
  464. /*
  465. * kdiv is 16-bit 2's complement (s16), but stored as unsigned int.
  466. * Cast it to u16 to avoid leading 0xffff's in case of negative value.
  467. */
  468. pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT);
  469. /* Set PLL lock time */
  470. writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
  471. /* Write PMSK values */
  472. writel_relaxed(pll_con3, pll->con_reg);
  473. writel_relaxed(pll_con5, pll->con_reg + 8);
  474. /* Wait for PLL lock if the PLL is enabled */
  475. if (pll_con3 & BIT(pll->enable_offs))
  476. return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
  477. return 0;
  478. }
  479. static const struct clk_ops samsung_pll0831x_clk_ops = {
  480. .recalc_rate = samsung_pll0831x_recalc_rate,
  481. .set_rate = samsung_pll0831x_set_rate,
  482. .round_rate = samsung_pll_round_rate,
  483. .enable = samsung_pll3xxx_enable,
  484. .disable = samsung_pll3xxx_disable,
  485. };
  486. static const struct clk_ops samsung_pll0831x_clk_min_ops = {
  487. .recalc_rate = samsung_pll0831x_recalc_rate,
  488. };
  489. /*
  490. * PLL45xx Clock Type
  491. */
  492. #define PLL4502_LOCK_FACTOR 400
  493. #define PLL4508_LOCK_FACTOR 240
  494. #define PLL45XX_MDIV_MASK (0x3FF)
  495. #define PLL45XX_PDIV_MASK (0x3F)
  496. #define PLL45XX_SDIV_MASK (0x7)
  497. #define PLL45XX_AFC_MASK (0x1F)
  498. #define PLL45XX_MDIV_SHIFT (16)
  499. #define PLL45XX_PDIV_SHIFT (8)
  500. #define PLL45XX_SDIV_SHIFT (0)
  501. #define PLL45XX_AFC_SHIFT (0)
  502. #define PLL45XX_ENABLE BIT(31)
  503. #define PLL45XX_LOCKED BIT(29)
  504. static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
  505. unsigned long parent_rate)
  506. {
  507. struct samsung_clk_pll *pll = to_clk_pll(hw);
  508. u32 mdiv, pdiv, sdiv, pll_con;
  509. u64 fvco = parent_rate;
  510. pll_con = readl_relaxed(pll->con_reg);
  511. mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
  512. pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
  513. sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
  514. if (pll->type == pll_4508)
  515. sdiv = sdiv - 1;
  516. fvco *= mdiv;
  517. do_div(fvco, (pdiv << sdiv));
  518. return (unsigned long)fvco;
  519. }
  520. static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
  521. const struct samsung_pll_rate_table *rate)
  522. {
  523. u32 old_mdiv, old_pdiv, old_afc;
  524. old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
  525. old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
  526. old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
  527. return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
  528. || old_afc != rate->afc);
  529. }
  530. static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
  531. unsigned long prate)
  532. {
  533. struct samsung_clk_pll *pll = to_clk_pll(hw);
  534. const struct samsung_pll_rate_table *rate;
  535. u32 con0, con1;
  536. /* Get required rate settings from table */
  537. rate = samsung_get_pll_settings(pll, drate);
  538. if (!rate) {
  539. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  540. drate, clk_hw_get_name(hw));
  541. return -EINVAL;
  542. }
  543. con0 = readl_relaxed(pll->con_reg);
  544. con1 = readl_relaxed(pll->con_reg + 0x4);
  545. if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
  546. /* If only s change, change just s value only*/
  547. con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
  548. con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
  549. writel_relaxed(con0, pll->con_reg);
  550. return 0;
  551. }
  552. /* Set PLL PMS values. */
  553. con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
  554. (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
  555. (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
  556. con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
  557. (rate->pdiv << PLL45XX_PDIV_SHIFT) |
  558. (rate->sdiv << PLL45XX_SDIV_SHIFT);
  559. /* Set PLL AFC value. */
  560. con1 = readl_relaxed(pll->con_reg + 0x4);
  561. con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
  562. con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
  563. /* Set PLL lock time. */
  564. switch (pll->type) {
  565. case pll_4502:
  566. writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
  567. break;
  568. case pll_4508:
  569. writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
  570. break;
  571. default:
  572. break;
  573. }
  574. /* Set new configuration. */
  575. writel_relaxed(con1, pll->con_reg + 0x4);
  576. writel_relaxed(con0, pll->con_reg);
  577. /* Wait for PLL lock */
  578. return samsung_pll_lock_wait(pll, PLL45XX_LOCKED);
  579. }
  580. static const struct clk_ops samsung_pll45xx_clk_ops = {
  581. .recalc_rate = samsung_pll45xx_recalc_rate,
  582. .round_rate = samsung_pll_round_rate,
  583. .set_rate = samsung_pll45xx_set_rate,
  584. };
  585. static const struct clk_ops samsung_pll45xx_clk_min_ops = {
  586. .recalc_rate = samsung_pll45xx_recalc_rate,
  587. };
  588. /*
  589. * PLL46xx Clock Type
  590. */
  591. #define PLL46XX_LOCK_FACTOR 3000
  592. #define PLL46XX_VSEL_MASK (1)
  593. #define PLL46XX_MDIV_MASK (0x1FF)
  594. #define PLL1460X_MDIV_MASK (0x3FF)
  595. #define PLL46XX_PDIV_MASK (0x3F)
  596. #define PLL46XX_SDIV_MASK (0x7)
  597. #define PLL46XX_VSEL_SHIFT (27)
  598. #define PLL46XX_MDIV_SHIFT (16)
  599. #define PLL46XX_PDIV_SHIFT (8)
  600. #define PLL46XX_SDIV_SHIFT (0)
  601. #define PLL46XX_KDIV_MASK (0xFFFF)
  602. #define PLL4650C_KDIV_MASK (0xFFF)
  603. #define PLL46XX_KDIV_SHIFT (0)
  604. #define PLL46XX_MFR_MASK (0x3F)
  605. #define PLL46XX_MRR_MASK (0x1F)
  606. #define PLL46XX_KDIV_SHIFT (0)
  607. #define PLL46XX_MFR_SHIFT (16)
  608. #define PLL46XX_MRR_SHIFT (24)
  609. #define PLL46XX_ENABLE BIT(31)
  610. #define PLL46XX_LOCKED BIT(29)
  611. #define PLL46XX_VSEL BIT(27)
  612. static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
  613. unsigned long parent_rate)
  614. {
  615. struct samsung_clk_pll *pll = to_clk_pll(hw);
  616. u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
  617. u64 fvco = parent_rate;
  618. pll_con0 = readl_relaxed(pll->con_reg);
  619. pll_con1 = readl_relaxed(pll->con_reg + 4);
  620. mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
  621. PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
  622. pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
  623. sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
  624. kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
  625. pll_con1 & PLL46XX_KDIV_MASK;
  626. shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
  627. fvco *= (mdiv << shift) + kdiv;
  628. do_div(fvco, (pdiv << sdiv));
  629. fvco >>= shift;
  630. return (unsigned long)fvco;
  631. }
  632. static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
  633. const struct samsung_pll_rate_table *rate)
  634. {
  635. u32 old_mdiv, old_pdiv, old_kdiv;
  636. old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
  637. old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
  638. old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK;
  639. return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
  640. || old_kdiv != rate->kdiv);
  641. }
  642. static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
  643. unsigned long prate)
  644. {
  645. struct samsung_clk_pll *pll = to_clk_pll(hw);
  646. const struct samsung_pll_rate_table *rate;
  647. u32 con0, con1, lock;
  648. /* Get required rate settings from table */
  649. rate = samsung_get_pll_settings(pll, drate);
  650. if (!rate) {
  651. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  652. drate, clk_hw_get_name(hw));
  653. return -EINVAL;
  654. }
  655. con0 = readl_relaxed(pll->con_reg);
  656. con1 = readl_relaxed(pll->con_reg + 0x4);
  657. if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
  658. /* If only s change, change just s value only*/
  659. con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
  660. con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
  661. writel_relaxed(con0, pll->con_reg);
  662. return 0;
  663. }
  664. /* Set PLL lock time. */
  665. lock = rate->pdiv * PLL46XX_LOCK_FACTOR;
  666. if (lock > 0xffff)
  667. /* Maximum lock time bitfield is 16-bit. */
  668. lock = 0xffff;
  669. /* Set PLL PMS and VSEL values. */
  670. if (pll->type == pll_1460x) {
  671. con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
  672. (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
  673. (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
  674. } else {
  675. con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
  676. (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
  677. (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
  678. (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
  679. con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
  680. }
  681. con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
  682. (rate->pdiv << PLL46XX_PDIV_SHIFT) |
  683. (rate->sdiv << PLL46XX_SDIV_SHIFT);
  684. /* Set PLL K, MFR and MRR values. */
  685. con1 = readl_relaxed(pll->con_reg + 0x4);
  686. con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
  687. (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
  688. (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
  689. con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
  690. (rate->mfr << PLL46XX_MFR_SHIFT) |
  691. (rate->mrr << PLL46XX_MRR_SHIFT);
  692. /* Write configuration to PLL */
  693. writel_relaxed(lock, pll->lock_reg);
  694. writel_relaxed(con0, pll->con_reg);
  695. writel_relaxed(con1, pll->con_reg + 0x4);
  696. /* Wait for PLL lock */
  697. return samsung_pll_lock_wait(pll, PLL46XX_LOCKED);
  698. }
  699. static const struct clk_ops samsung_pll46xx_clk_ops = {
  700. .recalc_rate = samsung_pll46xx_recalc_rate,
  701. .round_rate = samsung_pll_round_rate,
  702. .set_rate = samsung_pll46xx_set_rate,
  703. };
  704. static const struct clk_ops samsung_pll46xx_clk_min_ops = {
  705. .recalc_rate = samsung_pll46xx_recalc_rate,
  706. };
  707. /*
  708. * PLL6552 Clock Type
  709. */
  710. #define PLL6552_MDIV_MASK 0x3ff
  711. #define PLL6552_PDIV_MASK 0x3f
  712. #define PLL6552_SDIV_MASK 0x7
  713. #define PLL6552_MDIV_SHIFT 16
  714. #define PLL6552_MDIV_SHIFT_2416 14
  715. #define PLL6552_PDIV_SHIFT 8
  716. #define PLL6552_PDIV_SHIFT_2416 5
  717. #define PLL6552_SDIV_SHIFT 0
  718. static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
  719. unsigned long parent_rate)
  720. {
  721. struct samsung_clk_pll *pll = to_clk_pll(hw);
  722. u32 mdiv, pdiv, sdiv, pll_con;
  723. u64 fvco = parent_rate;
  724. pll_con = readl_relaxed(pll->con_reg);
  725. if (pll->type == pll_6552_s3c2416) {
  726. mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK;
  727. pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK;
  728. } else {
  729. mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
  730. pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
  731. }
  732. sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
  733. fvco *= mdiv;
  734. do_div(fvco, (pdiv << sdiv));
  735. return (unsigned long)fvco;
  736. }
  737. static const struct clk_ops samsung_pll6552_clk_ops = {
  738. .recalc_rate = samsung_pll6552_recalc_rate,
  739. };
  740. /*
  741. * PLL6553 Clock Type
  742. */
  743. #define PLL6553_MDIV_MASK 0xff
  744. #define PLL6553_PDIV_MASK 0x3f
  745. #define PLL6553_SDIV_MASK 0x7
  746. #define PLL6553_KDIV_MASK 0xffff
  747. #define PLL6553_MDIV_SHIFT 16
  748. #define PLL6553_PDIV_SHIFT 8
  749. #define PLL6553_SDIV_SHIFT 0
  750. #define PLL6553_KDIV_SHIFT 0
  751. static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
  752. unsigned long parent_rate)
  753. {
  754. struct samsung_clk_pll *pll = to_clk_pll(hw);
  755. u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
  756. u64 fvco = parent_rate;
  757. pll_con0 = readl_relaxed(pll->con_reg);
  758. pll_con1 = readl_relaxed(pll->con_reg + 0x4);
  759. mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
  760. pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
  761. sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
  762. kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
  763. fvco *= (mdiv << 16) + kdiv;
  764. do_div(fvco, (pdiv << sdiv));
  765. fvco >>= 16;
  766. return (unsigned long)fvco;
  767. }
  768. static const struct clk_ops samsung_pll6553_clk_ops = {
  769. .recalc_rate = samsung_pll6553_recalc_rate,
  770. };
  771. /*
  772. * PLL Clock Type of S3C24XX before S3C2443
  773. */
  774. #define PLLS3C2410_MDIV_MASK (0xff)
  775. #define PLLS3C2410_PDIV_MASK (0x1f)
  776. #define PLLS3C2410_SDIV_MASK (0x3)
  777. #define PLLS3C2410_MDIV_SHIFT (12)
  778. #define PLLS3C2410_PDIV_SHIFT (4)
  779. #define PLLS3C2410_SDIV_SHIFT (0)
  780. #define PLLS3C2410_ENABLE_REG_OFFSET 0x10
  781. static unsigned long samsung_s3c2410_pll_recalc_rate(struct clk_hw *hw,
  782. unsigned long parent_rate)
  783. {
  784. struct samsung_clk_pll *pll = to_clk_pll(hw);
  785. u32 pll_con, mdiv, pdiv, sdiv;
  786. u64 fvco = parent_rate;
  787. pll_con = readl_relaxed(pll->con_reg);
  788. mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
  789. pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
  790. sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
  791. fvco *= (mdiv + 8);
  792. do_div(fvco, (pdiv + 2) << sdiv);
  793. return (unsigned int)fvco;
  794. }
  795. static unsigned long samsung_s3c2440_mpll_recalc_rate(struct clk_hw *hw,
  796. unsigned long parent_rate)
  797. {
  798. struct samsung_clk_pll *pll = to_clk_pll(hw);
  799. u32 pll_con, mdiv, pdiv, sdiv;
  800. u64 fvco = parent_rate;
  801. pll_con = readl_relaxed(pll->con_reg);
  802. mdiv = (pll_con >> PLLS3C2410_MDIV_SHIFT) & PLLS3C2410_MDIV_MASK;
  803. pdiv = (pll_con >> PLLS3C2410_PDIV_SHIFT) & PLLS3C2410_PDIV_MASK;
  804. sdiv = (pll_con >> PLLS3C2410_SDIV_SHIFT) & PLLS3C2410_SDIV_MASK;
  805. fvco *= (2 * (mdiv + 8));
  806. do_div(fvco, (pdiv + 2) << sdiv);
  807. return (unsigned int)fvco;
  808. }
  809. static int samsung_s3c2410_pll_set_rate(struct clk_hw *hw, unsigned long drate,
  810. unsigned long prate)
  811. {
  812. struct samsung_clk_pll *pll = to_clk_pll(hw);
  813. const struct samsung_pll_rate_table *rate;
  814. u32 tmp;
  815. /* Get required rate settings from table */
  816. rate = samsung_get_pll_settings(pll, drate);
  817. if (!rate) {
  818. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  819. drate, clk_hw_get_name(hw));
  820. return -EINVAL;
  821. }
  822. tmp = readl_relaxed(pll->con_reg);
  823. /* Change PLL PMS values */
  824. tmp &= ~((PLLS3C2410_MDIV_MASK << PLLS3C2410_MDIV_SHIFT) |
  825. (PLLS3C2410_PDIV_MASK << PLLS3C2410_PDIV_SHIFT) |
  826. (PLLS3C2410_SDIV_MASK << PLLS3C2410_SDIV_SHIFT));
  827. tmp |= (rate->mdiv << PLLS3C2410_MDIV_SHIFT) |
  828. (rate->pdiv << PLLS3C2410_PDIV_SHIFT) |
  829. (rate->sdiv << PLLS3C2410_SDIV_SHIFT);
  830. writel_relaxed(tmp, pll->con_reg);
  831. /* Time to settle according to the manual */
  832. udelay(300);
  833. return 0;
  834. }
  835. static int samsung_s3c2410_pll_enable(struct clk_hw *hw, int bit, bool enable)
  836. {
  837. struct samsung_clk_pll *pll = to_clk_pll(hw);
  838. u32 pll_en = readl_relaxed(pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
  839. u32 pll_en_orig = pll_en;
  840. if (enable)
  841. pll_en &= ~BIT(bit);
  842. else
  843. pll_en |= BIT(bit);
  844. writel_relaxed(pll_en, pll->lock_reg + PLLS3C2410_ENABLE_REG_OFFSET);
  845. /* if we started the UPLL, then allow to settle */
  846. if (enable && (pll_en_orig & BIT(bit)))
  847. udelay(300);
  848. return 0;
  849. }
  850. static int samsung_s3c2410_mpll_enable(struct clk_hw *hw)
  851. {
  852. return samsung_s3c2410_pll_enable(hw, 5, true);
  853. }
  854. static void samsung_s3c2410_mpll_disable(struct clk_hw *hw)
  855. {
  856. samsung_s3c2410_pll_enable(hw, 5, false);
  857. }
  858. static int samsung_s3c2410_upll_enable(struct clk_hw *hw)
  859. {
  860. return samsung_s3c2410_pll_enable(hw, 7, true);
  861. }
  862. static void samsung_s3c2410_upll_disable(struct clk_hw *hw)
  863. {
  864. samsung_s3c2410_pll_enable(hw, 7, false);
  865. }
  866. static const struct clk_ops samsung_s3c2410_mpll_clk_min_ops = {
  867. .recalc_rate = samsung_s3c2410_pll_recalc_rate,
  868. .enable = samsung_s3c2410_mpll_enable,
  869. .disable = samsung_s3c2410_mpll_disable,
  870. };
  871. static const struct clk_ops samsung_s3c2410_upll_clk_min_ops = {
  872. .recalc_rate = samsung_s3c2410_pll_recalc_rate,
  873. .enable = samsung_s3c2410_upll_enable,
  874. .disable = samsung_s3c2410_upll_disable,
  875. };
  876. static const struct clk_ops samsung_s3c2440_mpll_clk_min_ops = {
  877. .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
  878. .enable = samsung_s3c2410_mpll_enable,
  879. .disable = samsung_s3c2410_mpll_disable,
  880. };
  881. static const struct clk_ops samsung_s3c2410_mpll_clk_ops = {
  882. .recalc_rate = samsung_s3c2410_pll_recalc_rate,
  883. .enable = samsung_s3c2410_mpll_enable,
  884. .disable = samsung_s3c2410_mpll_disable,
  885. .round_rate = samsung_pll_round_rate,
  886. .set_rate = samsung_s3c2410_pll_set_rate,
  887. };
  888. static const struct clk_ops samsung_s3c2410_upll_clk_ops = {
  889. .recalc_rate = samsung_s3c2410_pll_recalc_rate,
  890. .enable = samsung_s3c2410_upll_enable,
  891. .disable = samsung_s3c2410_upll_disable,
  892. .round_rate = samsung_pll_round_rate,
  893. .set_rate = samsung_s3c2410_pll_set_rate,
  894. };
  895. static const struct clk_ops samsung_s3c2440_mpll_clk_ops = {
  896. .recalc_rate = samsung_s3c2440_mpll_recalc_rate,
  897. .enable = samsung_s3c2410_mpll_enable,
  898. .disable = samsung_s3c2410_mpll_disable,
  899. .round_rate = samsung_pll_round_rate,
  900. .set_rate = samsung_s3c2410_pll_set_rate,
  901. };
  902. /*
  903. * PLL2550x Clock Type
  904. */
  905. #define PLL2550X_R_MASK (0x1)
  906. #define PLL2550X_P_MASK (0x3F)
  907. #define PLL2550X_M_MASK (0x3FF)
  908. #define PLL2550X_S_MASK (0x7)
  909. #define PLL2550X_R_SHIFT (20)
  910. #define PLL2550X_P_SHIFT (14)
  911. #define PLL2550X_M_SHIFT (4)
  912. #define PLL2550X_S_SHIFT (0)
  913. static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
  914. unsigned long parent_rate)
  915. {
  916. struct samsung_clk_pll *pll = to_clk_pll(hw);
  917. u32 r, p, m, s, pll_stat;
  918. u64 fvco = parent_rate;
  919. pll_stat = readl_relaxed(pll->con_reg);
  920. r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
  921. if (!r)
  922. return 0;
  923. p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
  924. m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
  925. s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
  926. fvco *= m;
  927. do_div(fvco, (p << s));
  928. return (unsigned long)fvco;
  929. }
  930. static const struct clk_ops samsung_pll2550x_clk_ops = {
  931. .recalc_rate = samsung_pll2550x_recalc_rate,
  932. };
  933. /*
  934. * PLL2550xx Clock Type
  935. */
  936. /* Maximum lock time can be 270 * PDIV cycles */
  937. #define PLL2550XX_LOCK_FACTOR 270
  938. #define PLL2550XX_M_MASK 0x3FF
  939. #define PLL2550XX_P_MASK 0x3F
  940. #define PLL2550XX_S_MASK 0x7
  941. #define PLL2550XX_LOCK_STAT_MASK 0x1
  942. #define PLL2550XX_M_SHIFT 9
  943. #define PLL2550XX_P_SHIFT 3
  944. #define PLL2550XX_S_SHIFT 0
  945. #define PLL2550XX_LOCK_STAT_SHIFT 21
  946. static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
  947. unsigned long parent_rate)
  948. {
  949. struct samsung_clk_pll *pll = to_clk_pll(hw);
  950. u32 mdiv, pdiv, sdiv, pll_con;
  951. u64 fvco = parent_rate;
  952. pll_con = readl_relaxed(pll->con_reg);
  953. mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
  954. pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
  955. sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
  956. fvco *= mdiv;
  957. do_div(fvco, (pdiv << sdiv));
  958. return (unsigned long)fvco;
  959. }
  960. static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
  961. {
  962. u32 old_mdiv, old_pdiv;
  963. old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
  964. old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
  965. return mdiv != old_mdiv || pdiv != old_pdiv;
  966. }
  967. static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
  968. unsigned long prate)
  969. {
  970. struct samsung_clk_pll *pll = to_clk_pll(hw);
  971. const struct samsung_pll_rate_table *rate;
  972. u32 tmp;
  973. /* Get required rate settings from table */
  974. rate = samsung_get_pll_settings(pll, drate);
  975. if (!rate) {
  976. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  977. drate, clk_hw_get_name(hw));
  978. return -EINVAL;
  979. }
  980. tmp = readl_relaxed(pll->con_reg);
  981. if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
  982. /* If only s change, change just s value only*/
  983. tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
  984. tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
  985. writel_relaxed(tmp, pll->con_reg);
  986. return 0;
  987. }
  988. /* Set PLL lock time. */
  989. writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
  990. /* Change PLL PMS values */
  991. tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
  992. (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
  993. (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
  994. tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
  995. (rate->pdiv << PLL2550XX_P_SHIFT) |
  996. (rate->sdiv << PLL2550XX_S_SHIFT);
  997. writel_relaxed(tmp, pll->con_reg);
  998. /* Wait for PLL lock */
  999. return samsung_pll_lock_wait(pll,
  1000. PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT);
  1001. }
  1002. static const struct clk_ops samsung_pll2550xx_clk_ops = {
  1003. .recalc_rate = samsung_pll2550xx_recalc_rate,
  1004. .round_rate = samsung_pll_round_rate,
  1005. .set_rate = samsung_pll2550xx_set_rate,
  1006. };
  1007. static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
  1008. .recalc_rate = samsung_pll2550xx_recalc_rate,
  1009. };
  1010. /*
  1011. * PLL2650x Clock Type
  1012. */
  1013. /* Maximum lock time can be 3000 * PDIV cycles */
  1014. #define PLL2650X_LOCK_FACTOR 3000
  1015. #define PLL2650X_M_MASK 0x1ff
  1016. #define PLL2650X_P_MASK 0x3f
  1017. #define PLL2650X_S_MASK 0x7
  1018. #define PLL2650X_K_MASK 0xffff
  1019. #define PLL2650X_LOCK_STAT_MASK 0x1
  1020. #define PLL2650X_M_SHIFT 16
  1021. #define PLL2650X_P_SHIFT 8
  1022. #define PLL2650X_S_SHIFT 0
  1023. #define PLL2650X_K_SHIFT 0
  1024. #define PLL2650X_LOCK_STAT_SHIFT 29
  1025. #define PLL2650X_PLL_ENABLE_SHIFT 31
  1026. static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw,
  1027. unsigned long parent_rate)
  1028. {
  1029. struct samsung_clk_pll *pll = to_clk_pll(hw);
  1030. u64 fout = parent_rate;
  1031. u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
  1032. s16 kdiv;
  1033. pll_con0 = readl_relaxed(pll->con_reg);
  1034. mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK;
  1035. pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK;
  1036. sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK;
  1037. pll_con1 = readl_relaxed(pll->con_reg + 4);
  1038. kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK);
  1039. fout *= (mdiv << 16) + kdiv;
  1040. do_div(fout, (pdiv << sdiv));
  1041. fout >>= 16;
  1042. return (unsigned long)fout;
  1043. }
  1044. static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate,
  1045. unsigned long prate)
  1046. {
  1047. struct samsung_clk_pll *pll = to_clk_pll(hw);
  1048. const struct samsung_pll_rate_table *rate;
  1049. u32 con0, con1;
  1050. /* Get required rate settings from table */
  1051. rate = samsung_get_pll_settings(pll, drate);
  1052. if (!rate) {
  1053. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  1054. drate, clk_hw_get_name(hw));
  1055. return -EINVAL;
  1056. }
  1057. con0 = readl_relaxed(pll->con_reg);
  1058. con1 = readl_relaxed(pll->con_reg + 4);
  1059. /* Set PLL lock time. */
  1060. writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg);
  1061. /* Change PLL PMS values */
  1062. con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
  1063. (PLL2650X_P_MASK << PLL2650X_P_SHIFT) |
  1064. (PLL2650X_S_MASK << PLL2650X_S_SHIFT));
  1065. con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
  1066. (rate->pdiv << PLL2650X_P_SHIFT) |
  1067. (rate->sdiv << PLL2650X_S_SHIFT);
  1068. con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
  1069. writel_relaxed(con0, pll->con_reg);
  1070. con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT);
  1071. con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT);
  1072. writel_relaxed(con1, pll->con_reg + 4);
  1073. /* Wait for PLL lock */
  1074. return samsung_pll_lock_wait(pll,
  1075. PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT);
  1076. }
  1077. static const struct clk_ops samsung_pll2650x_clk_ops = {
  1078. .recalc_rate = samsung_pll2650x_recalc_rate,
  1079. .round_rate = samsung_pll_round_rate,
  1080. .set_rate = samsung_pll2650x_set_rate,
  1081. };
  1082. static const struct clk_ops samsung_pll2650x_clk_min_ops = {
  1083. .recalc_rate = samsung_pll2650x_recalc_rate,
  1084. };
  1085. /*
  1086. * PLL2650XX Clock Type
  1087. */
  1088. /* Maximum lock time can be 3000 * PDIV cycles */
  1089. #define PLL2650XX_LOCK_FACTOR 3000
  1090. #define PLL2650XX_MDIV_SHIFT 9
  1091. #define PLL2650XX_PDIV_SHIFT 3
  1092. #define PLL2650XX_SDIV_SHIFT 0
  1093. #define PLL2650XX_KDIV_SHIFT 0
  1094. #define PLL2650XX_MDIV_MASK 0x1ff
  1095. #define PLL2650XX_PDIV_MASK 0x3f
  1096. #define PLL2650XX_SDIV_MASK 0x7
  1097. #define PLL2650XX_KDIV_MASK 0xffff
  1098. #define PLL2650XX_PLL_ENABLE_SHIFT 23
  1099. #define PLL2650XX_PLL_LOCKTIME_SHIFT 21
  1100. #define PLL2650XX_PLL_FOUTMASK_SHIFT 31
  1101. static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
  1102. unsigned long parent_rate)
  1103. {
  1104. struct samsung_clk_pll *pll = to_clk_pll(hw);
  1105. u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
  1106. s16 kdiv;
  1107. u64 fvco = parent_rate;
  1108. pll_con0 = readl_relaxed(pll->con_reg);
  1109. pll_con2 = readl_relaxed(pll->con_reg + 8);
  1110. mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
  1111. pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
  1112. sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
  1113. kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
  1114. fvco *= (mdiv << 16) + kdiv;
  1115. do_div(fvco, (pdiv << sdiv));
  1116. fvco >>= 16;
  1117. return (unsigned long)fvco;
  1118. }
  1119. static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
  1120. unsigned long parent_rate)
  1121. {
  1122. struct samsung_clk_pll *pll = to_clk_pll(hw);
  1123. u32 pll_con0, pll_con2;
  1124. const struct samsung_pll_rate_table *rate;
  1125. rate = samsung_get_pll_settings(pll, drate);
  1126. if (!rate) {
  1127. pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
  1128. drate, clk_hw_get_name(hw));
  1129. return -EINVAL;
  1130. }
  1131. pll_con0 = readl_relaxed(pll->con_reg);
  1132. pll_con2 = readl_relaxed(pll->con_reg + 8);
  1133. /* Change PLL PMS values */
  1134. pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
  1135. PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
  1136. PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
  1137. pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
  1138. pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
  1139. pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
  1140. pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
  1141. pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
  1142. pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
  1143. pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
  1144. << PLL2650XX_KDIV_SHIFT;
  1145. /* Set PLL lock time. */
  1146. writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
  1147. writel_relaxed(pll_con0, pll->con_reg);
  1148. writel_relaxed(pll_con2, pll->con_reg + 8);
  1149. return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT);
  1150. }
  1151. static const struct clk_ops samsung_pll2650xx_clk_ops = {
  1152. .recalc_rate = samsung_pll2650xx_recalc_rate,
  1153. .set_rate = samsung_pll2650xx_set_rate,
  1154. .round_rate = samsung_pll_round_rate,
  1155. };
  1156. static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
  1157. .recalc_rate = samsung_pll2650xx_recalc_rate,
  1158. };
  1159. static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
  1160. const struct samsung_pll_clock *pll_clk,
  1161. void __iomem *base)
  1162. {
  1163. struct samsung_clk_pll *pll;
  1164. struct clk_init_data init;
  1165. int ret, len;
  1166. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  1167. if (!pll) {
  1168. pr_err("%s: could not allocate pll clk %s\n",
  1169. __func__, pll_clk->name);
  1170. return;
  1171. }
  1172. init.name = pll_clk->name;
  1173. init.flags = pll_clk->flags;
  1174. init.parent_names = &pll_clk->parent_name;
  1175. init.num_parents = 1;
  1176. if (pll_clk->rate_table) {
  1177. /* find count of rates in rate_table */
  1178. for (len = 0; pll_clk->rate_table[len].rate != 0; )
  1179. len++;
  1180. pll->rate_count = len;
  1181. pll->rate_table = kmemdup(pll_clk->rate_table,
  1182. pll->rate_count *
  1183. sizeof(struct samsung_pll_rate_table),
  1184. GFP_KERNEL);
  1185. WARN(!pll->rate_table,
  1186. "%s: could not allocate rate table for %s\n",
  1187. __func__, pll_clk->name);
  1188. }
  1189. switch (pll_clk->type) {
  1190. case pll_2126:
  1191. init.ops = &samsung_pll2126_clk_ops;
  1192. break;
  1193. case pll_3000:
  1194. init.ops = &samsung_pll3000_clk_ops;
  1195. break;
  1196. /* clk_ops for 35xx and 2550 are similar */
  1197. case pll_35xx:
  1198. case pll_2550:
  1199. case pll_1450x:
  1200. case pll_1451x:
  1201. case pll_1452x:
  1202. case pll_142xx:
  1203. pll->enable_offs = PLL35XX_ENABLE_SHIFT;
  1204. pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
  1205. if (!pll->rate_table)
  1206. init.ops = &samsung_pll35xx_clk_min_ops;
  1207. else
  1208. init.ops = &samsung_pll35xx_clk_ops;
  1209. break;
  1210. case pll_1417x:
  1211. case pll_0822x:
  1212. pll->enable_offs = PLL0822X_ENABLE_SHIFT;
  1213. pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
  1214. if (!pll->rate_table)
  1215. init.ops = &samsung_pll0822x_clk_min_ops;
  1216. else
  1217. init.ops = &samsung_pll0822x_clk_ops;
  1218. break;
  1219. case pll_4500:
  1220. init.ops = &samsung_pll45xx_clk_min_ops;
  1221. break;
  1222. case pll_4502:
  1223. case pll_4508:
  1224. if (!pll->rate_table)
  1225. init.ops = &samsung_pll45xx_clk_min_ops;
  1226. else
  1227. init.ops = &samsung_pll45xx_clk_ops;
  1228. break;
  1229. /* clk_ops for 36xx and 2650 are similar */
  1230. case pll_36xx:
  1231. case pll_2650:
  1232. pll->enable_offs = PLL36XX_ENABLE_SHIFT;
  1233. pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
  1234. if (!pll->rate_table)
  1235. init.ops = &samsung_pll36xx_clk_min_ops;
  1236. else
  1237. init.ops = &samsung_pll36xx_clk_ops;
  1238. break;
  1239. case pll_0831x:
  1240. pll->enable_offs = PLL0831X_ENABLE_SHIFT;
  1241. pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
  1242. if (!pll->rate_table)
  1243. init.ops = &samsung_pll0831x_clk_min_ops;
  1244. else
  1245. init.ops = &samsung_pll0831x_clk_ops;
  1246. break;
  1247. case pll_6552:
  1248. case pll_6552_s3c2416:
  1249. init.ops = &samsung_pll6552_clk_ops;
  1250. break;
  1251. case pll_6553:
  1252. init.ops = &samsung_pll6553_clk_ops;
  1253. break;
  1254. case pll_4600:
  1255. case pll_4650:
  1256. case pll_4650c:
  1257. case pll_1460x:
  1258. if (!pll->rate_table)
  1259. init.ops = &samsung_pll46xx_clk_min_ops;
  1260. else
  1261. init.ops = &samsung_pll46xx_clk_ops;
  1262. break;
  1263. case pll_s3c2410_mpll:
  1264. if (!pll->rate_table)
  1265. init.ops = &samsung_s3c2410_mpll_clk_min_ops;
  1266. else
  1267. init.ops = &samsung_s3c2410_mpll_clk_ops;
  1268. break;
  1269. case pll_s3c2410_upll:
  1270. if (!pll->rate_table)
  1271. init.ops = &samsung_s3c2410_upll_clk_min_ops;
  1272. else
  1273. init.ops = &samsung_s3c2410_upll_clk_ops;
  1274. break;
  1275. case pll_s3c2440_mpll:
  1276. if (!pll->rate_table)
  1277. init.ops = &samsung_s3c2440_mpll_clk_min_ops;
  1278. else
  1279. init.ops = &samsung_s3c2440_mpll_clk_ops;
  1280. break;
  1281. case pll_2550x:
  1282. init.ops = &samsung_pll2550x_clk_ops;
  1283. break;
  1284. case pll_2550xx:
  1285. if (!pll->rate_table)
  1286. init.ops = &samsung_pll2550xx_clk_min_ops;
  1287. else
  1288. init.ops = &samsung_pll2550xx_clk_ops;
  1289. break;
  1290. case pll_2650x:
  1291. if (!pll->rate_table)
  1292. init.ops = &samsung_pll2650x_clk_min_ops;
  1293. else
  1294. init.ops = &samsung_pll2650x_clk_ops;
  1295. break;
  1296. case pll_2650xx:
  1297. if (!pll->rate_table)
  1298. init.ops = &samsung_pll2650xx_clk_min_ops;
  1299. else
  1300. init.ops = &samsung_pll2650xx_clk_ops;
  1301. break;
  1302. default:
  1303. pr_warn("%s: Unknown pll type for pll clk %s\n",
  1304. __func__, pll_clk->name);
  1305. }
  1306. pll->hw.init = &init;
  1307. pll->type = pll_clk->type;
  1308. pll->lock_reg = base + pll_clk->lock_offset;
  1309. pll->con_reg = base + pll_clk->con_offset;
  1310. ret = clk_hw_register(ctx->dev, &pll->hw);
  1311. if (ret) {
  1312. pr_err("%s: failed to register pll clock %s : %d\n",
  1313. __func__, pll_clk->name, ret);
  1314. kfree(pll->rate_table);
  1315. kfree(pll);
  1316. return;
  1317. }
  1318. samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
  1319. }
  1320. void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
  1321. const struct samsung_pll_clock *pll_list,
  1322. unsigned int nr_pll, void __iomem *base)
  1323. {
  1324. int cnt;
  1325. for (cnt = 0; cnt < nr_pll; cnt++)
  1326. _samsung_clk_register_pll(ctx, &pll_list[cnt], base);
  1327. }